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41a1c9ec | 1 | // SPDX-License-Identifier: GPL-2.0-only |
505a1495 SP |
2 | /* |
3 | * TI QSPI driver | |
4 | * | |
5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
6 | * Author: Sourav Poddar <sourav.poddar@ti.com> | |
505a1495 SP |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/omap-dma.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/pinctrl/consumer.h> | |
4dea6c9b V |
27 | #include <linux/mfd/syscon.h> |
28 | #include <linux/regmap.h> | |
c687c46e | 29 | #include <linux/sizes.h> |
505a1495 SP |
30 | |
31 | #include <linux/spi/spi.h> | |
b95cb394 | 32 | #include <linux/spi/spi-mem.h> |
505a1495 SP |
33 | |
34 | struct ti_qspi_regs { | |
35 | u32 clkctrl; | |
36 | }; | |
37 | ||
38 | struct ti_qspi { | |
5720ec0a V |
39 | struct completion transfer_complete; |
40 | ||
505a1495 SP |
41 | /* list synchronization */ |
42 | struct mutex list_lock; | |
43 | ||
44 | struct spi_master *master; | |
45 | void __iomem *base; | |
6b3938ae | 46 | void __iomem *mmap_base; |
b95cb394 | 47 | size_t mmap_size; |
4dea6c9b V |
48 | struct regmap *ctrl_base; |
49 | unsigned int ctrl_reg; | |
505a1495 SP |
50 | struct clk *fclk; |
51 | struct device *dev; | |
52 | ||
53 | struct ti_qspi_regs ctx_reg; | |
54 | ||
5720ec0a | 55 | dma_addr_t mmap_phys_base; |
c687c46e V |
56 | dma_addr_t rx_bb_dma_addr; |
57 | void *rx_bb_addr; | |
5720ec0a V |
58 | struct dma_chan *rx_chan; |
59 | ||
505a1495 SP |
60 | u32 spi_max_frequency; |
61 | u32 cmd; | |
62 | u32 dc; | |
6b3938ae | 63 | |
4dea6c9b | 64 | bool mmap_enabled; |
c52c91bb | 65 | int current_cs; |
505a1495 SP |
66 | }; |
67 | ||
68 | #define QSPI_PID (0x0) | |
69 | #define QSPI_SYSCONFIG (0x10) | |
505a1495 SP |
70 | #define QSPI_SPI_CLOCK_CNTRL_REG (0x40) |
71 | #define QSPI_SPI_DC_REG (0x44) | |
72 | #define QSPI_SPI_CMD_REG (0x48) | |
73 | #define QSPI_SPI_STATUS_REG (0x4c) | |
74 | #define QSPI_SPI_DATA_REG (0x50) | |
4dea6c9b | 75 | #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n)) |
505a1495 | 76 | #define QSPI_SPI_SWITCH_REG (0x64) |
505a1495 SP |
77 | #define QSPI_SPI_DATA_REG_1 (0x68) |
78 | #define QSPI_SPI_DATA_REG_2 (0x6c) | |
79 | #define QSPI_SPI_DATA_REG_3 (0x70) | |
80 | ||
81 | #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) | |
82 | ||
505a1495 SP |
83 | /* Clock Control */ |
84 | #define QSPI_CLK_EN (1 << 31) | |
85 | #define QSPI_CLK_DIV_MAX 0xffff | |
86 | ||
87 | /* Command */ | |
88 | #define QSPI_EN_CS(n) (n << 28) | |
89 | #define QSPI_WLEN(n) ((n - 1) << 19) | |
90 | #define QSPI_3_PIN (1 << 18) | |
91 | #define QSPI_RD_SNGL (1 << 16) | |
92 | #define QSPI_WR_SNGL (2 << 16) | |
93 | #define QSPI_RD_DUAL (3 << 16) | |
94 | #define QSPI_RD_QUAD (7 << 16) | |
95 | #define QSPI_INVAL (4 << 16) | |
505a1495 | 96 | #define QSPI_FLEN(n) ((n - 1) << 0) |
f682c4ff V |
97 | #define QSPI_WLEN_MAX_BITS 128 |
98 | #define QSPI_WLEN_MAX_BYTES 16 | |
ea1b60fb | 99 | #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS) |
505a1495 SP |
100 | |
101 | /* STATUS REGISTER */ | |
00611047 | 102 | #define BUSY 0x01 |
505a1495 SP |
103 | #define WC 0x02 |
104 | ||
505a1495 SP |
105 | /* Device Control */ |
106 | #define QSPI_DD(m, n) (m << (3 + n * 8)) | |
107 | #define QSPI_CKPHA(n) (1 << (2 + n * 8)) | |
108 | #define QSPI_CSPOL(n) (1 << (1 + n * 8)) | |
109 | #define QSPI_CKPOL(n) (1 << (n * 8)) | |
110 | ||
111 | #define QSPI_FRAME 4096 | |
112 | ||
113 | #define QSPI_AUTOSUSPEND_TIMEOUT 2000 | |
114 | ||
4dea6c9b V |
115 | #define MEM_CS_EN(n) ((n + 1) << 8) |
116 | #define MEM_CS_MASK (7 << 8) | |
117 | ||
118 | #define MM_SWITCH 0x1 | |
119 | ||
120 | #define QSPI_SETUP_RD_NORMAL (0x0 << 12) | |
121 | #define QSPI_SETUP_RD_DUAL (0x1 << 12) | |
122 | #define QSPI_SETUP_RD_QUAD (0x3 << 12) | |
123 | #define QSPI_SETUP_ADDR_SHIFT 8 | |
124 | #define QSPI_SETUP_DUMMY_SHIFT 10 | |
125 | ||
c687c46e V |
126 | #define QSPI_DMA_BUFFER_SIZE SZ_64K |
127 | ||
505a1495 SP |
128 | static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, |
129 | unsigned long reg) | |
130 | { | |
131 | return readl(qspi->base + reg); | |
132 | } | |
133 | ||
134 | static inline void ti_qspi_write(struct ti_qspi *qspi, | |
135 | unsigned long val, unsigned long reg) | |
136 | { | |
137 | writel(val, qspi->base + reg); | |
138 | } | |
139 | ||
140 | static int ti_qspi_setup(struct spi_device *spi) | |
141 | { | |
142 | struct ti_qspi *qspi = spi_master_get_devdata(spi->master); | |
143 | struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; | |
144 | int clk_div = 0, ret; | |
145 | u32 clk_ctrl_reg, clk_rate, clk_mask; | |
146 | ||
147 | if (spi->master->busy) { | |
77cca63a | 148 | dev_dbg(qspi->dev, "master busy doing other transfers\n"); |
505a1495 SP |
149 | return -EBUSY; |
150 | } | |
151 | ||
152 | if (!qspi->spi_max_frequency) { | |
153 | dev_err(qspi->dev, "spi max frequency not defined\n"); | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | clk_rate = clk_get_rate(qspi->fclk); | |
158 | ||
159 | clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; | |
160 | ||
161 | if (clk_div < 0) { | |
162 | dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | if (clk_div > QSPI_CLK_DIV_MAX) { | |
167 | dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", | |
168 | QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
172 | dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", | |
173 | qspi->spi_max_frequency, clk_div); | |
174 | ||
175 | ret = pm_runtime_get_sync(qspi->dev); | |
05b96675 | 176 | if (ret < 0) { |
505a1495 SP |
177 | dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); |
178 | return ret; | |
179 | } | |
180 | ||
181 | clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); | |
182 | ||
183 | clk_ctrl_reg &= ~QSPI_CLK_EN; | |
184 | ||
185 | /* disable SCLK */ | |
186 | ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); | |
187 | ||
188 | /* enable SCLK */ | |
189 | clk_mask = QSPI_CLK_EN | clk_div; | |
190 | ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); | |
191 | ctx_reg->clkctrl = clk_mask; | |
192 | ||
193 | pm_runtime_mark_last_busy(qspi->dev); | |
194 | ret = pm_runtime_put_autosuspend(qspi->dev); | |
195 | if (ret < 0) { | |
196 | dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); | |
197 | return ret; | |
198 | } | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | static void ti_qspi_restore_ctx(struct ti_qspi *qspi) | |
204 | { | |
205 | struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; | |
206 | ||
207 | ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); | |
208 | } | |
209 | ||
00611047 M |
210 | static inline u32 qspi_is_busy(struct ti_qspi *qspi) |
211 | { | |
212 | u32 stat; | |
213 | unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; | |
214 | ||
215 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | |
216 | while ((stat & BUSY) && time_after(timeout, jiffies)) { | |
217 | cpu_relax(); | |
218 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | |
219 | } | |
220 | ||
221 | WARN(stat & BUSY, "qspi busy\n"); | |
222 | return stat & BUSY; | |
223 | } | |
224 | ||
57c2ecd9 V |
225 | static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) |
226 | { | |
227 | u32 stat; | |
228 | unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; | |
229 | ||
230 | do { | |
231 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | |
232 | if (stat & WC) | |
233 | return 0; | |
234 | cpu_relax(); | |
235 | } while (time_after(timeout, jiffies)); | |
236 | ||
237 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | |
238 | if (stat & WC) | |
239 | return 0; | |
240 | return -ETIMEDOUT; | |
241 | } | |
242 | ||
1ff7760f BH |
243 | static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, |
244 | int count) | |
505a1495 | 245 | { |
1ff7760f | 246 | int wlen, xfer_len; |
505a1495 SP |
247 | unsigned int cmd; |
248 | const u8 *txbuf; | |
f682c4ff | 249 | u32 data; |
505a1495 SP |
250 | |
251 | txbuf = t->tx_buf; | |
252 | cmd = qspi->cmd | QSPI_WR_SNGL; | |
3ab54620 | 253 | wlen = t->bits_per_word >> 3; /* in bytes */ |
f682c4ff | 254 | xfer_len = wlen; |
505a1495 SP |
255 | |
256 | while (count) { | |
00611047 M |
257 | if (qspi_is_busy(qspi)) |
258 | return -EBUSY; | |
259 | ||
505a1495 | 260 | switch (wlen) { |
3ab54620 | 261 | case 1: |
505a1495 SP |
262 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", |
263 | cmd, qspi->dc, *txbuf); | |
f682c4ff V |
264 | if (count >= QSPI_WLEN_MAX_BYTES) { |
265 | u32 *txp = (u32 *)txbuf; | |
266 | ||
267 | data = cpu_to_be32(*txp++); | |
268 | writel(data, qspi->base + | |
269 | QSPI_SPI_DATA_REG_3); | |
270 | data = cpu_to_be32(*txp++); | |
271 | writel(data, qspi->base + | |
272 | QSPI_SPI_DATA_REG_2); | |
273 | data = cpu_to_be32(*txp++); | |
274 | writel(data, qspi->base + | |
275 | QSPI_SPI_DATA_REG_1); | |
276 | data = cpu_to_be32(*txp++); | |
277 | writel(data, qspi->base + | |
278 | QSPI_SPI_DATA_REG); | |
279 | xfer_len = QSPI_WLEN_MAX_BYTES; | |
280 | cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS); | |
281 | } else { | |
282 | writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); | |
283 | cmd = qspi->cmd | QSPI_WR_SNGL; | |
284 | xfer_len = wlen; | |
285 | cmd |= QSPI_WLEN(wlen); | |
286 | } | |
505a1495 | 287 | break; |
3ab54620 | 288 | case 2: |
505a1495 SP |
289 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", |
290 | cmd, qspi->dc, *txbuf); | |
291 | writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); | |
505a1495 | 292 | break; |
3ab54620 | 293 | case 4: |
505a1495 SP |
294 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", |
295 | cmd, qspi->dc, *txbuf); | |
296 | writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); | |
505a1495 SP |
297 | break; |
298 | } | |
3ab54620 AL |
299 | |
300 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); | |
57c2ecd9 | 301 | if (ti_qspi_poll_wc(qspi)) { |
3ab54620 AL |
302 | dev_err(qspi->dev, "write timed out\n"); |
303 | return -ETIMEDOUT; | |
304 | } | |
f682c4ff V |
305 | txbuf += xfer_len; |
306 | count -= xfer_len; | |
505a1495 SP |
307 | } |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
1ff7760f BH |
312 | static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, |
313 | int count) | |
505a1495 | 314 | { |
1ff7760f | 315 | int wlen; |
505a1495 SP |
316 | unsigned int cmd; |
317 | u8 *rxbuf; | |
318 | ||
319 | rxbuf = t->rx_buf; | |
70e2e976 SP |
320 | cmd = qspi->cmd; |
321 | switch (t->rx_nbits) { | |
322 | case SPI_NBITS_DUAL: | |
323 | cmd |= QSPI_RD_DUAL; | |
324 | break; | |
325 | case SPI_NBITS_QUAD: | |
326 | cmd |= QSPI_RD_QUAD; | |
327 | break; | |
328 | default: | |
329 | cmd |= QSPI_RD_SNGL; | |
330 | break; | |
331 | } | |
3ab54620 | 332 | wlen = t->bits_per_word >> 3; /* in bytes */ |
505a1495 SP |
333 | |
334 | while (count) { | |
335 | dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); | |
00611047 M |
336 | if (qspi_is_busy(qspi)) |
337 | return -EBUSY; | |
338 | ||
505a1495 | 339 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); |
57c2ecd9 | 340 | if (ti_qspi_poll_wc(qspi)) { |
505a1495 SP |
341 | dev_err(qspi->dev, "read timed out\n"); |
342 | return -ETIMEDOUT; | |
343 | } | |
344 | switch (wlen) { | |
3ab54620 | 345 | case 1: |
505a1495 | 346 | *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 | 347 | break; |
3ab54620 | 348 | case 2: |
505a1495 | 349 | *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 | 350 | break; |
3ab54620 | 351 | case 4: |
505a1495 | 352 | *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 SP |
353 | break; |
354 | } | |
3ab54620 AL |
355 | rxbuf += wlen; |
356 | count -= wlen; | |
505a1495 SP |
357 | } |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
1ff7760f BH |
362 | static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, |
363 | int count) | |
505a1495 SP |
364 | { |
365 | int ret; | |
366 | ||
367 | if (t->tx_buf) { | |
1ff7760f | 368 | ret = qspi_write_msg(qspi, t, count); |
505a1495 SP |
369 | if (ret) { |
370 | dev_dbg(qspi->dev, "Error while writing\n"); | |
371 | return ret; | |
372 | } | |
373 | } | |
374 | ||
375 | if (t->rx_buf) { | |
1ff7760f | 376 | ret = qspi_read_msg(qspi, t, count); |
505a1495 SP |
377 | if (ret) { |
378 | dev_dbg(qspi->dev, "Error while reading\n"); | |
379 | return ret; | |
380 | } | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
5720ec0a V |
386 | static void ti_qspi_dma_callback(void *param) |
387 | { | |
388 | struct ti_qspi *qspi = param; | |
389 | ||
390 | complete(&qspi->transfer_complete); | |
391 | } | |
392 | ||
393 | static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, | |
394 | dma_addr_t dma_src, size_t len) | |
395 | { | |
396 | struct dma_chan *chan = qspi->rx_chan; | |
5720ec0a V |
397 | dma_cookie_t cookie; |
398 | enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
399 | struct dma_async_tx_descriptor *tx; | |
400 | int ret; | |
401 | ||
1351aaeb | 402 | tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags); |
5720ec0a V |
403 | if (!tx) { |
404 | dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); | |
405 | return -EIO; | |
406 | } | |
407 | ||
408 | tx->callback = ti_qspi_dma_callback; | |
409 | tx->callback_param = qspi; | |
410 | cookie = tx->tx_submit(tx); | |
d06a3507 | 411 | reinit_completion(&qspi->transfer_complete); |
5720ec0a V |
412 | |
413 | ret = dma_submit_error(cookie); | |
414 | if (ret) { | |
415 | dev_err(qspi->dev, "dma_submit_error %d\n", cookie); | |
416 | return -EIO; | |
417 | } | |
418 | ||
419 | dma_async_issue_pending(chan); | |
420 | ret = wait_for_completion_timeout(&qspi->transfer_complete, | |
421 | msecs_to_jiffies(len)); | |
422 | if (ret <= 0) { | |
423 | dmaengine_terminate_sync(chan); | |
424 | dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); | |
425 | return -ETIMEDOUT; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
b95cb394 BB |
431 | static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, |
432 | void *to, size_t readsize) | |
c687c46e | 433 | { |
b95cb394 | 434 | dma_addr_t dma_src = qspi->mmap_phys_base + offs; |
c687c46e V |
435 | int ret = 0; |
436 | ||
437 | /* | |
438 | * Use bounce buffer as FS like jffs2, ubifs may pass | |
439 | * buffers that does not belong to kernel lowmem region. | |
440 | */ | |
441 | while (readsize != 0) { | |
442 | size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE, | |
443 | readsize); | |
444 | ||
445 | ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, | |
446 | dma_src, xfer_len); | |
447 | if (ret != 0) | |
448 | return ret; | |
449 | memcpy(to, qspi->rx_bb_addr, xfer_len); | |
450 | readsize -= xfer_len; | |
451 | dma_src += xfer_len; | |
452 | to += xfer_len; | |
453 | } | |
454 | ||
455 | return ret; | |
456 | } | |
457 | ||
5720ec0a V |
458 | static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, |
459 | loff_t from) | |
460 | { | |
461 | struct scatterlist *sg; | |
462 | dma_addr_t dma_src = qspi->mmap_phys_base + from; | |
463 | dma_addr_t dma_dst; | |
464 | int i, len, ret; | |
465 | ||
466 | for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) { | |
467 | dma_dst = sg_dma_address(sg); | |
468 | len = sg_dma_len(sg); | |
469 | ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); | |
470 | if (ret) | |
471 | return ret; | |
472 | dma_src += len; | |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
4dea6c9b V |
478 | static void ti_qspi_enable_memory_map(struct spi_device *spi) |
479 | { | |
480 | struct ti_qspi *qspi = spi_master_get_devdata(spi->master); | |
481 | ||
482 | ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); | |
483 | if (qspi->ctrl_base) { | |
484 | regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, | |
673c865e V |
485 | MEM_CS_MASK, |
486 | MEM_CS_EN(spi->chip_select)); | |
4dea6c9b V |
487 | } |
488 | qspi->mmap_enabled = true; | |
c52c91bb | 489 | qspi->current_cs = spi->chip_select; |
4dea6c9b V |
490 | } |
491 | ||
492 | static void ti_qspi_disable_memory_map(struct spi_device *spi) | |
493 | { | |
494 | struct ti_qspi *qspi = spi_master_get_devdata(spi->master); | |
495 | ||
496 | ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); | |
497 | if (qspi->ctrl_base) | |
498 | regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, | |
673c865e | 499 | MEM_CS_MASK, 0); |
4dea6c9b | 500 | qspi->mmap_enabled = false; |
c52c91bb | 501 | qspi->current_cs = -1; |
4dea6c9b V |
502 | } |
503 | ||
b95cb394 BB |
504 | static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode, |
505 | u8 data_nbits, u8 addr_width, | |
506 | u8 dummy_bytes) | |
4dea6c9b V |
507 | { |
508 | struct ti_qspi *qspi = spi_master_get_devdata(spi->master); | |
b95cb394 | 509 | u32 memval = opcode; |
4dea6c9b | 510 | |
b95cb394 | 511 | switch (data_nbits) { |
4dea6c9b V |
512 | case SPI_NBITS_QUAD: |
513 | memval |= QSPI_SETUP_RD_QUAD; | |
514 | break; | |
515 | case SPI_NBITS_DUAL: | |
516 | memval |= QSPI_SETUP_RD_DUAL; | |
517 | break; | |
518 | default: | |
519 | memval |= QSPI_SETUP_RD_NORMAL; | |
520 | break; | |
521 | } | |
b95cb394 BB |
522 | memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | |
523 | dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); | |
4dea6c9b V |
524 | ti_qspi_write(qspi, memval, |
525 | QSPI_SPI_SETUP_REG(spi->chip_select)); | |
526 | } | |
527 | ||
b95cb394 BB |
528 | static int ti_qspi_exec_mem_op(struct spi_mem *mem, |
529 | const struct spi_mem_op *op) | |
530 | { | |
531 | struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master); | |
532 | u32 from = 0; | |
533 | int ret = 0; | |
534 | ||
535 | /* Only optimize read path. */ | |
536 | if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || | |
537 | !op->addr.nbytes || op->addr.nbytes > 4) | |
538 | return -ENOTSUPP; | |
539 | ||
540 | /* Address exceeds MMIO window size, fall back to regular mode. */ | |
541 | from = op->addr.val; | |
542 | if (from + op->data.nbytes > qspi->mmap_size) | |
543 | return -ENOTSUPP; | |
544 | ||
545 | mutex_lock(&qspi->list_lock); | |
546 | ||
c52c91bb | 547 | if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) |
b95cb394 BB |
548 | ti_qspi_enable_memory_map(mem->spi); |
549 | ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, | |
550 | op->addr.nbytes, op->dummy.nbytes); | |
551 | ||
552 | if (qspi->rx_chan) { | |
553 | struct sg_table sgt; | |
554 | ||
555 | if (virt_addr_valid(op->data.buf.in) && | |
556 | !spi_controller_dma_map_mem_op_data(mem->spi->master, op, | |
557 | &sgt)) { | |
558 | ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); | |
559 | spi_controller_dma_unmap_mem_op_data(mem->spi->master, | |
560 | op, &sgt); | |
561 | } else { | |
562 | ret = ti_qspi_dma_bounce_buffer(qspi, from, | |
563 | op->data.buf.in, | |
564 | op->data.nbytes); | |
565 | } | |
566 | } else { | |
567 | memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, | |
568 | op->data.nbytes); | |
569 | } | |
570 | ||
571 | mutex_unlock(&qspi->list_lock); | |
572 | ||
573 | return ret; | |
574 | } | |
575 | ||
576 | static const struct spi_controller_mem_ops ti_qspi_mem_ops = { | |
577 | .exec_op = ti_qspi_exec_mem_op, | |
578 | }; | |
579 | ||
505a1495 SP |
580 | static int ti_qspi_start_transfer_one(struct spi_master *master, |
581 | struct spi_message *m) | |
582 | { | |
583 | struct ti_qspi *qspi = spi_master_get_devdata(master); | |
584 | struct spi_device *spi = m->spi; | |
585 | struct spi_transfer *t; | |
586 | int status = 0, ret; | |
1ff7760f BH |
587 | unsigned int frame_len_words, transfer_len_words; |
588 | int wlen; | |
505a1495 SP |
589 | |
590 | /* setup device control reg */ | |
591 | qspi->dc = 0; | |
592 | ||
593 | if (spi->mode & SPI_CPHA) | |
594 | qspi->dc |= QSPI_CKPHA(spi->chip_select); | |
595 | if (spi->mode & SPI_CPOL) | |
596 | qspi->dc |= QSPI_CKPOL(spi->chip_select); | |
597 | if (spi->mode & SPI_CS_HIGH) | |
598 | qspi->dc |= QSPI_CSPOL(spi->chip_select); | |
599 | ||
ea1b60fb BH |
600 | frame_len_words = 0; |
601 | list_for_each_entry(t, &m->transfers, transfer_list) | |
602 | frame_len_words += t->len / (t->bits_per_word >> 3); | |
603 | frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME); | |
505a1495 SP |
604 | |
605 | /* setup command reg */ | |
606 | qspi->cmd = 0; | |
607 | qspi->cmd |= QSPI_EN_CS(spi->chip_select); | |
ea1b60fb | 608 | qspi->cmd |= QSPI_FLEN(frame_len_words); |
505a1495 | 609 | |
505a1495 SP |
610 | ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); |
611 | ||
612 | mutex_lock(&qspi->list_lock); | |
613 | ||
4dea6c9b V |
614 | if (qspi->mmap_enabled) |
615 | ti_qspi_disable_memory_map(spi); | |
616 | ||
505a1495 | 617 | list_for_each_entry(t, &m->transfers, transfer_list) { |
ea1b60fb BH |
618 | qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | |
619 | QSPI_WLEN(t->bits_per_word)); | |
505a1495 | 620 | |
1ff7760f BH |
621 | wlen = t->bits_per_word >> 3; |
622 | transfer_len_words = min(t->len / wlen, frame_len_words); | |
623 | ||
624 | ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); | |
505a1495 SP |
625 | if (ret) { |
626 | dev_dbg(qspi->dev, "transfer message failed\n"); | |
b6460366 | 627 | mutex_unlock(&qspi->list_lock); |
505a1495 SP |
628 | return -EINVAL; |
629 | } | |
630 | ||
1ff7760f BH |
631 | m->actual_length += transfer_len_words * wlen; |
632 | frame_len_words -= transfer_len_words; | |
633 | if (frame_len_words == 0) | |
634 | break; | |
505a1495 SP |
635 | } |
636 | ||
637 | mutex_unlock(&qspi->list_lock); | |
638 | ||
bc27a539 | 639 | ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); |
505a1495 SP |
640 | m->status = status; |
641 | spi_finalize_current_message(master); | |
642 | ||
505a1495 SP |
643 | return status; |
644 | } | |
645 | ||
505a1495 SP |
646 | static int ti_qspi_runtime_resume(struct device *dev) |
647 | { | |
648 | struct ti_qspi *qspi; | |
505a1495 | 649 | |
f17414c4 | 650 | qspi = dev_get_drvdata(dev); |
505a1495 SP |
651 | ti_qspi_restore_ctx(qspi); |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | static const struct of_device_id ti_qspi_match[] = { | |
657 | {.compatible = "ti,dra7xxx-qspi" }, | |
09222fc3 | 658 | {.compatible = "ti,am4372-qspi" }, |
505a1495 SP |
659 | {}, |
660 | }; | |
e1432d30 | 661 | MODULE_DEVICE_TABLE(of, ti_qspi_match); |
505a1495 SP |
662 | |
663 | static int ti_qspi_probe(struct platform_device *pdev) | |
664 | { | |
665 | struct ti_qspi *qspi; | |
666 | struct spi_master *master; | |
4dea6c9b | 667 | struct resource *r, *res_mmap; |
505a1495 SP |
668 | struct device_node *np = pdev->dev.of_node; |
669 | u32 max_freq; | |
670 | int ret = 0, num_cs, irq; | |
5720ec0a | 671 | dma_cap_mask_t mask; |
505a1495 SP |
672 | |
673 | master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); | |
674 | if (!master) | |
675 | return -ENOMEM; | |
676 | ||
633795b9 | 677 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; |
505a1495 | 678 | |
505a1495 SP |
679 | master->flags = SPI_MASTER_HALF_DUPLEX; |
680 | master->setup = ti_qspi_setup; | |
681 | master->auto_runtime_pm = true; | |
682 | master->transfer_one_message = ti_qspi_start_transfer_one; | |
683 | master->dev.of_node = pdev->dev.of_node; | |
aa188f90 AL |
684 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
685 | SPI_BPW_MASK(8); | |
b95cb394 | 686 | master->mem_ops = &ti_qspi_mem_ops; |
505a1495 SP |
687 | |
688 | if (!of_property_read_u32(np, "num-cs", &num_cs)) | |
689 | master->num_chipselect = num_cs; | |
690 | ||
505a1495 SP |
691 | qspi = spi_master_get_devdata(master); |
692 | qspi->master = master; | |
693 | qspi->dev = &pdev->dev; | |
160a0613 | 694 | platform_set_drvdata(pdev, qspi); |
505a1495 | 695 | |
6b3938ae SP |
696 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); |
697 | if (r == NULL) { | |
698 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
699 | if (r == NULL) { | |
700 | dev_err(&pdev->dev, "missing platform data\n"); | |
cce59c22 P |
701 | ret = -ENODEV; |
702 | goto free_master; | |
6b3938ae SP |
703 | } |
704 | } | |
505a1495 | 705 | |
6b3938ae SP |
706 | res_mmap = platform_get_resource_byname(pdev, |
707 | IORESOURCE_MEM, "qspi_mmap"); | |
708 | if (res_mmap == NULL) { | |
709 | res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
710 | if (res_mmap == NULL) { | |
711 | dev_err(&pdev->dev, | |
712 | "memory mapped resource not required\n"); | |
6b3938ae SP |
713 | } |
714 | } | |
6282f122 BB |
715 | |
716 | if (res_mmap) | |
717 | qspi->mmap_size = resource_size(res_mmap); | |
6b3938ae | 718 | |
505a1495 SP |
719 | irq = platform_get_irq(pdev, 0); |
720 | if (irq < 0) { | |
cce59c22 P |
721 | ret = irq; |
722 | goto free_master; | |
505a1495 SP |
723 | } |
724 | ||
505a1495 SP |
725 | mutex_init(&qspi->list_lock); |
726 | ||
727 | qspi->base = devm_ioremap_resource(&pdev->dev, r); | |
728 | if (IS_ERR(qspi->base)) { | |
729 | ret = PTR_ERR(qspi->base); | |
730 | goto free_master; | |
731 | } | |
732 | ||
4dea6c9b V |
733 | |
734 | if (of_property_read_bool(np, "syscon-chipselects")) { | |
735 | qspi->ctrl_base = | |
736 | syscon_regmap_lookup_by_phandle(np, | |
737 | "syscon-chipselects"); | |
cce59c22 P |
738 | if (IS_ERR(qspi->ctrl_base)) { |
739 | ret = PTR_ERR(qspi->ctrl_base); | |
740 | goto free_master; | |
741 | } | |
4dea6c9b V |
742 | ret = of_property_read_u32_index(np, |
743 | "syscon-chipselects", | |
744 | 1, &qspi->ctrl_reg); | |
745 | if (ret) { | |
746 | dev_err(&pdev->dev, | |
747 | "couldn't get ctrl_mod reg index\n"); | |
cce59c22 | 748 | goto free_master; |
6b3938ae SP |
749 | } |
750 | } | |
751 | ||
505a1495 SP |
752 | qspi->fclk = devm_clk_get(&pdev->dev, "fck"); |
753 | if (IS_ERR(qspi->fclk)) { | |
754 | ret = PTR_ERR(qspi->fclk); | |
755 | dev_err(&pdev->dev, "could not get clk: %d\n", ret); | |
756 | } | |
757 | ||
505a1495 SP |
758 | pm_runtime_use_autosuspend(&pdev->dev); |
759 | pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); | |
760 | pm_runtime_enable(&pdev->dev); | |
761 | ||
762 | if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) | |
763 | qspi->spi_max_frequency = max_freq; | |
764 | ||
5720ec0a V |
765 | dma_cap_zero(mask); |
766 | dma_cap_set(DMA_MEMCPY, mask); | |
505a1495 | 767 | |
5720ec0a | 768 | qspi->rx_chan = dma_request_chan_by_mask(&mask); |
7abfe04c | 769 | if (IS_ERR(qspi->rx_chan)) { |
5720ec0a V |
770 | dev_err(qspi->dev, |
771 | "No Rx DMA available, trying mmap mode\n"); | |
7abfe04c | 772 | qspi->rx_chan = NULL; |
5720ec0a V |
773 | ret = 0; |
774 | goto no_dma; | |
775 | } | |
c687c46e V |
776 | qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, |
777 | QSPI_DMA_BUFFER_SIZE, | |
778 | &qspi->rx_bb_dma_addr, | |
779 | GFP_KERNEL | GFP_DMA); | |
780 | if (!qspi->rx_bb_addr) { | |
781 | dev_err(qspi->dev, | |
782 | "dma_alloc_coherent failed, using PIO mode\n"); | |
783 | dma_release_channel(qspi->rx_chan); | |
784 | goto no_dma; | |
785 | } | |
5720ec0a V |
786 | master->dma_rx = qspi->rx_chan; |
787 | init_completion(&qspi->transfer_complete); | |
788 | if (res_mmap) | |
789 | qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; | |
790 | ||
791 | no_dma: | |
792 | if (!qspi->rx_chan && res_mmap) { | |
793 | qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); | |
794 | if (IS_ERR(qspi->mmap_base)) { | |
795 | dev_info(&pdev->dev, | |
796 | "mmap failed with error %ld using PIO mode\n", | |
797 | PTR_ERR(qspi->mmap_base)); | |
798 | qspi->mmap_base = NULL; | |
b95cb394 | 799 | master->mem_ops = NULL; |
5720ec0a V |
800 | } |
801 | } | |
802 | qspi->mmap_enabled = false; | |
c52c91bb | 803 | qspi->current_cs = -1; |
5720ec0a V |
804 | |
805 | ret = devm_spi_register_master(&pdev->dev, master); | |
806 | if (!ret) | |
807 | return 0; | |
505a1495 | 808 | |
cce59c22 | 809 | pm_runtime_disable(&pdev->dev); |
505a1495 SP |
810 | free_master: |
811 | spi_master_put(master); | |
812 | return ret; | |
813 | } | |
814 | ||
815 | static int ti_qspi_remove(struct platform_device *pdev) | |
816 | { | |
3ac066e2 JJH |
817 | struct ti_qspi *qspi = platform_get_drvdata(pdev); |
818 | int rc; | |
819 | ||
820 | rc = spi_master_suspend(qspi->master); | |
821 | if (rc) | |
822 | return rc; | |
823 | ||
e6b5140b | 824 | pm_runtime_put_sync(&pdev->dev); |
cbcabb7a SP |
825 | pm_runtime_disable(&pdev->dev); |
826 | ||
c687c46e V |
827 | if (qspi->rx_bb_addr) |
828 | dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, | |
829 | qspi->rx_bb_addr, | |
830 | qspi->rx_bb_dma_addr); | |
5720ec0a V |
831 | if (qspi->rx_chan) |
832 | dma_release_channel(qspi->rx_chan); | |
833 | ||
505a1495 SP |
834 | return 0; |
835 | } | |
836 | ||
837 | static const struct dev_pm_ops ti_qspi_pm_ops = { | |
838 | .runtime_resume = ti_qspi_runtime_resume, | |
839 | }; | |
840 | ||
841 | static struct platform_driver ti_qspi_driver = { | |
842 | .probe = ti_qspi_probe, | |
dabefd56 | 843 | .remove = ti_qspi_remove, |
505a1495 | 844 | .driver = { |
5a33d30f | 845 | .name = "ti-qspi", |
505a1495 SP |
846 | .pm = &ti_qspi_pm_ops, |
847 | .of_match_table = ti_qspi_match, | |
848 | } | |
849 | }; | |
850 | ||
851 | module_platform_driver(ti_qspi_driver); | |
852 | ||
853 | MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); | |
854 | MODULE_LICENSE("GPL v2"); | |
855 | MODULE_DESCRIPTION("TI QSPI controller driver"); | |
5a33d30f | 856 | MODULE_ALIAS("platform:ti-qspi"); |