[linux-2.6-block.git] / drivers / spi / spi-ti-qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * Author: Sourav Poddar <sourav.poddar@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GPLv2.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>

#include <linux/spi/spi.h>

struct ti_qspi_regs {
	u32 clkctrl;
};

struct ti_qspi {
	/* list synchronization */
	struct mutex            list_lock;

	struct spi_master	*master;
	void __iomem            *base;
	void __iomem            *ctrl_base;
	void __iomem            *mmap_base;
	struct clk		*fclk;
	struct device           *dev;

	struct ti_qspi_regs     ctx_reg;

	u32 spi_max_frequency;
	u32 cmd;
	u32 dc;

	bool ctrl_mod;
};

#define QSPI_PID			(0x0)
#define QSPI_SYSCONFIG			(0x10)
#define QSPI_SPI_CLOCK_CNTRL_REG	(0x40)
#define QSPI_SPI_DC_REG			(0x44)
#define QSPI_SPI_CMD_REG		(0x48)
#define QSPI_SPI_STATUS_REG		(0x4c)
#define QSPI_SPI_DATA_REG		(0x50)
#define QSPI_SPI_SETUP0_REG		(0x54)
#define QSPI_SPI_SWITCH_REG		(0x64)
#define QSPI_SPI_SETUP1_REG		(0x58)
#define QSPI_SPI_SETUP2_REG		(0x5c)
#define QSPI_SPI_SETUP3_REG		(0x60)
#define QSPI_SPI_DATA_REG_1		(0x68)
#define QSPI_SPI_DATA_REG_2		(0x6c)
#define QSPI_SPI_DATA_REG_3		(0x70)

#define QSPI_COMPLETION_TIMEOUT		msecs_to_jiffies(2000)

#define QSPI_FCLK			192000000

/* Clock Control */
#define QSPI_CLK_EN			(1 << 31)
#define QSPI_CLK_DIV_MAX		0xffff

/* Command */
#define QSPI_EN_CS(n)			(n << 28)
#define QSPI_WLEN(n)			((n - 1) << 19)
#define QSPI_3_PIN			(1 << 18)
#define QSPI_RD_SNGL			(1 << 16)
#define QSPI_WR_SNGL			(2 << 16)
#define QSPI_RD_DUAL			(3 << 16)
#define QSPI_RD_QUAD			(7 << 16)
#define QSPI_INVAL			(4 << 16)
#define QSPI_FLEN(n)			((n - 1) << 0)
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		16

/* STATUS REGISTER */
#define BUSY				0x01
#define WC				0x02

/* Device Control */
#define QSPI_DD(m, n)			(m << (3 + n * 8))
#define QSPI_CKPHA(n)			(1 << (2 + n * 8))
#define QSPI_CSPOL(n)			(1 << (1 + n * 8))
#define QSPI_CKPOL(n)			(1 << (n * 8))

#define	QSPI_FRAME			4096

#define QSPI_AUTOSUSPEND_TIMEOUT         2000

static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
		unsigned long reg)
{
	return readl(qspi->base + reg);
}

static inline void ti_qspi_write(struct ti_qspi *qspi,
		unsigned long val, unsigned long reg)
{
	writel(val, qspi->base + reg);
}

static int ti_qspi_setup(struct spi_device *spi)
{
	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	int clk_div = 0, ret;
	u32 clk_ctrl_reg, clk_rate, clk_mask;

	if (spi->master->busy) {
		dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
		return -EBUSY;
	}

	if (!qspi->spi_max_frequency) {
		dev_err(qspi->dev, "spi max frequency not defined\n");
		return -EINVAL;
	}

	clk_rate = clk_get_rate(qspi->fclk);

	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;

	if (clk_div < 0) {
		dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
		return -EINVAL;
	}

	if (clk_div > QSPI_CLK_DIV_MAX) {
		dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
				QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
		return -EINVAL;
	}

	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
			qspi->spi_max_frequency, clk_div);

	ret = pm_runtime_get_sync(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);

	clk_ctrl_reg &= ~QSPI_CLK_EN;

	/* disable SCLK */
	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);

	/* enable SCLK */
	clk_mask = QSPI_CLK_EN | clk_div;
	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	ctx_reg->clkctrl = clk_mask;

	pm_runtime_mark_last_busy(qspi->dev);
	ret = pm_runtime_put_autosuspend(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
		return ret;
	}

	return 0;
}

static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;

	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
}

static inline u32 qspi_is_busy(struct ti_qspi *qspi)
{
	u32 stat;
	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	while ((stat & BUSY) && time_after(timeout, jiffies)) {
		cpu_relax();
		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	}

	WARN(stat & BUSY, "qspi busy\n");
	return stat & BUSY;
}

static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
{
	u32 stat;
	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;

	do {
		stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
		if (stat & WC)
			return 0;
		cpu_relax();
	} while (time_after(timeout, jiffies));

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	if (stat & WC)
		return 0;
	return  -ETIMEDOUT;
}

static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count, xfer_len;
	unsigned int cmd;
	const u8 *txbuf;
	u32 data;

	txbuf = t->tx_buf;
	cmd = qspi->cmd | QSPI_WR_SNGL;
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */
	xfer_len = wlen;

	while (count) {
		if (qspi_is_busy(qspi))
			return -EBUSY;

		switch (wlen) {
		case 1:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
					cmd, qspi->dc, *txbuf);
			if (count >= QSPI_WLEN_MAX_BYTES) {
				u32 *txp = (u32 *)txbuf;

				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_3);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_2);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG_1);
				data = cpu_to_be32(*txp++);
				writel(data, qspi->base +
				       QSPI_SPI_DATA_REG);
				xfer_len = QSPI_WLEN_MAX_BYTES;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
			} else {
				writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
				cmd = qspi->cmd | QSPI_WR_SNGL;
				xfer_len = wlen;
				cmd |= QSPI_WLEN(wlen);
			}
			break;
		case 2:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
					cmd, qspi->dc, *txbuf);
			writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
					cmd, qspi->dc, *txbuf);
			writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			break;
		}

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (ti_qspi_poll_wc(qspi)) {
			dev_err(qspi->dev, "write timed out\n");
			return -ETIMEDOUT;
		}
		txbuf += xfer_len;
		count -= xfer_len;
	}

	return 0;
}

static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count;
	unsigned int cmd;
	u8 *rxbuf;

	rxbuf = t->rx_buf;
	cmd = qspi->cmd;
	switch (t->rx_nbits) {
	case SPI_NBITS_DUAL:
		cmd |= QSPI_RD_DUAL;
		break;
	case SPI_NBITS_QUAD:
		cmd |= QSPI_RD_QUAD;
		break;
	default:
		cmd |= QSPI_RD_SNGL;
		break;
	}
	count = t->len;
	wlen = t->bits_per_word >> 3;	/* in bytes */

	while (count) {
		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
		if (qspi_is_busy(qspi))
			return -EBUSY;

		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		if (ti_qspi_poll_wc(qspi)) {
			dev_err(qspi->dev, "read timed out\n");
			return -ETIMEDOUT;
		}
		switch (wlen) {
		case 1:
			*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 2:
			*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
			break;
		case 4:
			*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
			break;
		}
		rxbuf += wlen;
		count -= wlen;
	}

	return 0;
}

static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int ret;

	if (t->tx_buf) {
		ret = qspi_write_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while writing\n");
			return ret;
		}
	}

	if (t->rx_buf) {
		ret = qspi_read_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while reading\n");
			return ret;
		}
	}

	return 0;
}

static int ti_qspi_start_transfer_one(struct spi_master *master,
		struct spi_message *m)
{
	struct ti_qspi *qspi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	int status = 0, ret;
	int frame_length;

	/* setup device control reg */
	qspi->dc = 0;

	if (spi->mode & SPI_CPHA)
		qspi->dc |= QSPI_CKPHA(spi->chip_select);
	if (spi->mode & SPI_CPOL)
		qspi->dc |= QSPI_CKPOL(spi->chip_select);
	if (spi->mode & SPI_CS_HIGH)
		qspi->dc |= QSPI_CSPOL(spi->chip_select);

	frame_length = (m->frame_length << 3) / spi->bits_per_word;

	frame_length = clamp(frame_length, 0, QSPI_FRAME);

	/* setup command reg */
	qspi->cmd = 0;
	qspi->cmd |= QSPI_EN_CS(spi->chip_select);
	qspi->cmd |= QSPI_FLEN(frame_length);

	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);

	mutex_lock(&qspi->list_lock);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		qspi->cmd |= QSPI_WLEN(t->bits_per_word);

		ret = qspi_transfer_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "transfer message failed\n");
			mutex_unlock(&qspi->list_lock);
			return -EINVAL;
		}

		m->actual_length += t->len;
	}

	mutex_unlock(&qspi->list_lock);

	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int ti_qspi_runtime_resume(struct device *dev)
{
	struct ti_qspi      *qspi;

	qspi = dev_get_drvdata(dev);
	ti_qspi_restore_ctx(qspi);

	return 0;
}

static const struct of_device_id ti_qspi_match[] = {
	{.compatible = "ti,dra7xxx-qspi" },
	{.compatible = "ti,am4372-qspi" },
	{},
};
MODULE_DEVICE_TABLE(of, ti_qspi_match);

static int ti_qspi_probe(struct platform_device *pdev)
{
	struct  ti_qspi *qspi;
	struct spi_master *master;
	struct resource         *r, *res_ctrl, *res_mmap;
	struct device_node *np = pdev->dev.of_node;
	u32 max_freq;
	int ret = 0, num_cs, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	if (!master)
		return -ENOMEM;

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;

	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->setup = ti_qspi_setup;
	master->auto_runtime_pm = true;
	master->transfer_one_message = ti_qspi_start_transfer_one;
	master->dev.of_node = pdev->dev.of_node;
	master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
				     SPI_BPW_MASK(8);

	if (!of_property_read_u32(np, "num-cs", &num_cs))
		master->num_chipselect = num_cs;

	qspi = spi_master_get_devdata(master);
	qspi->master = master;
	qspi->dev = &pdev->dev;
	platform_set_drvdata(pdev, qspi);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	if (r == NULL) {
		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (r == NULL) {
			dev_err(&pdev->dev, "missing platform data\n");
			return -ENODEV;
		}
	}

	res_mmap = platform_get_resource_byname(pdev,
			IORESOURCE_MEM, "qspi_mmap");
	if (res_mmap == NULL) {
		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
		if (res_mmap == NULL) {
			dev_err(&pdev->dev,
				"memory mapped resource not required\n");
		}
	}

	res_ctrl = platform_get_resource_byname(pdev,
			IORESOURCE_MEM, "qspi_ctrlmod");
	if (res_ctrl == NULL) {
		res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
		if (res_ctrl == NULL) {
			dev_dbg(&pdev->dev,
				"control module resources not required\n");
		}
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	mutex_init(&qspi->list_lock);

	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(qspi->base)) {
		ret = PTR_ERR(qspi->base);
		goto free_master;
	}

	if (res_ctrl) {
		qspi->ctrl_mod = true;
		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
		if (IS_ERR(qspi->ctrl_base)) {
			ret = PTR_ERR(qspi->ctrl_base);
			goto free_master;
		}
	}

	if (res_mmap) {
		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
		if (IS_ERR(qspi->mmap_base)) {
			ret = PTR_ERR(qspi->mmap_base);
			goto free_master;
		}
	}

	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(qspi->fclk)) {
		ret = PTR_ERR(qspi->fclk);
		dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	}

	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
		qspi->spi_max_frequency = max_freq;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret)
		goto free_master;

	return 0;

free_master:
	spi_master_put(master);
	return ret;
}

static int ti_qspi_remove(struct platform_device *pdev)
{
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct dev_pm_ops ti_qspi_pm_ops = {
	.runtime_resume = ti_qspi_runtime_resume,
};

static struct platform_driver ti_qspi_driver = {
	.probe	= ti_qspi_probe,
	.remove = ti_qspi_remove,
	.driver = {
		.name	= "ti-qspi",
		.pm =   &ti_qspi_pm_ops,
		.of_match_table = ti_qspi_match,
	}
};

module_platform_driver(ti_qspi_driver);

MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI QSPI controller driver");
MODULE_ALIAS("platform:ti-qspi");
Commit	Line	Data
505a1495 SP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* Author: Sourav Poddar <sourav.poddar@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GPLv2.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/module.h>
	20	#include <linux/device.h>
	21	#include <linux/delay.h>
	22	#include <linux/dma-mapping.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/omap-dma.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29	#include <linux/slab.h>
	30	#include <linux/pm_runtime.h>
	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33	#include <linux/pinctrl/consumer.h>
	34
	35	#include <linux/spi/spi.h>
	36
	37	struct ti_qspi_regs {
	38	u32 clkctrl;
	39	};
	40
	41	struct ti_qspi {
505a1495 SP	42	/* list synchronization */
	43	struct mutex list_lock;
	44
	45	struct spi_master *master;
	46	void __iomem *base;
6b3938ae SP	47	void __iomem *ctrl_base;
6b3938ae SP	48	void __iomem *mmap_base;
505a1495 SP	49	struct clk *fclk;
	50	struct device *dev;
	51
	52	struct ti_qspi_regs ctx_reg;
	53
	54	u32 spi_max_frequency;
	55	u32 cmd;
	56	u32 dc;
6b3938ae SP	57
6b3938ae SP	58	bool ctrl_mod;
505a1495 SP	59	};
	60
	61	#define QSPI_PID (0x0)
	62	#define QSPI_SYSCONFIG (0x10)
505a1495 SP	63	#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
	64	#define QSPI_SPI_DC_REG (0x44)
	65	#define QSPI_SPI_CMD_REG (0x48)
	66	#define QSPI_SPI_STATUS_REG (0x4c)
	67	#define QSPI_SPI_DATA_REG (0x50)
	68	#define QSPI_SPI_SETUP0_REG (0x54)
	69	#define QSPI_SPI_SWITCH_REG (0x64)
	70	#define QSPI_SPI_SETUP1_REG (0x58)
	71	#define QSPI_SPI_SETUP2_REG (0x5c)
	72	#define QSPI_SPI_SETUP3_REG (0x60)
	73	#define QSPI_SPI_DATA_REG_1 (0x68)
	74	#define QSPI_SPI_DATA_REG_2 (0x6c)
	75	#define QSPI_SPI_DATA_REG_3 (0x70)
	76
	77	#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
	78
	79	#define QSPI_FCLK 192000000
	80
	81	/* Clock Control */
	82	#define QSPI_CLK_EN (1 << 31)
	83	#define QSPI_CLK_DIV_MAX 0xffff
	84
	85	/* Command */
	86	#define QSPI_EN_CS(n) (n << 28)
	87	#define QSPI_WLEN(n) ((n - 1) << 19)
	88	#define QSPI_3_PIN (1 << 18)
	89	#define QSPI_RD_SNGL (1 << 16)
	90	#define QSPI_WR_SNGL (2 << 16)
	91	#define QSPI_RD_DUAL (3 << 16)
	92	#define QSPI_RD_QUAD (7 << 16)
	93	#define QSPI_INVAL (4 << 16)
505a1495	94	#define QSPI_FLEN(n) ((n - 1) << 0)
f682c4ff V	95	#define QSPI_WLEN_MAX_BITS 128
f682c4ff V	96	#define QSPI_WLEN_MAX_BYTES 16
505a1495 SP	97
505a1495 SP	98	/* STATUS REGISTER */
00611047	99	#define BUSY 0x01
505a1495 SP	100	#define WC 0x02
505a1495 SP	101
505a1495 SP	102	/* Device Control */
	103	#define QSPI_DD(m, n) (m << (3 + n * 8))
	104	#define QSPI_CKPHA(n) (1 << (2 + n * 8))
	105	#define QSPI_CSPOL(n) (1 << (1 + n * 8))
	106	#define QSPI_CKPOL(n) (1 << (n * 8))
	107
	108	#define QSPI_FRAME 4096
	109
	110	#define QSPI_AUTOSUSPEND_TIMEOUT 2000
	111
	112	static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
	113	unsigned long reg)
	114	{
	115	return readl(qspi->base + reg);
	116	}
	117
	118	static inline void ti_qspi_write(struct ti_qspi *qspi,
	119	unsigned long val, unsigned long reg)
	120	{
	121	writel(val, qspi->base + reg);
	122	}
	123
	124	static int ti_qspi_setup(struct spi_device *spi)
	125	{
	126	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
	127	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	128	int clk_div = 0, ret;
	129	u32 clk_ctrl_reg, clk_rate, clk_mask;
	130
	131	if (spi->master->busy) {
	132	dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
	133	return -EBUSY;
	134	}
	135
	136	if (!qspi->spi_max_frequency) {
	137	dev_err(qspi->dev, "spi max frequency not defined\n");
	138	return -EINVAL;
	139	}
	140
	141	clk_rate = clk_get_rate(qspi->fclk);
	142
	143	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
	144
	145	if (clk_div < 0) {
	146	dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
	147	return -EINVAL;
	148	}
	149
	150	if (clk_div > QSPI_CLK_DIV_MAX) {
	151	dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
	152	QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
	153	return -EINVAL;
	154	}
	155
	156	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
	157	qspi->spi_max_frequency, clk_div);
	158
	159	ret = pm_runtime_get_sync(qspi->dev);
05b96675	160	if (ret < 0) {
505a1495 SP	161	dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
	162	return ret;
	163	}
	164
	165	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
	166
	167	clk_ctrl_reg &= ~QSPI_CLK_EN;
	168
	169	/* disable SCLK */
	170	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
	171
	172	/* enable SCLK */
	173	clk_mask = QSPI_CLK_EN \| clk_div;
	174	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	175	ctx_reg->clkctrl = clk_mask;
	176
	177	pm_runtime_mark_last_busy(qspi->dev);
	178	ret = pm_runtime_put_autosuspend(qspi->dev);
	179	if (ret < 0) {
	180	dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
	181	return ret;
	182	}
	183
	184	return 0;
	185	}
	186
	187	static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
	188	{
	189	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	190
	191	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
	192	}
	193
00611047 M	194	static inline u32 qspi_is_busy(struct ti_qspi *qspi)
	195	{
	196	u32 stat;
	197	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
	198
	199	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	200	while ((stat & BUSY) && time_after(timeout, jiffies)) {
	201	cpu_relax();
	202	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	203	}
	204
	205	WARN(stat & BUSY, "qspi busy\n");
	206	return stat & BUSY;
	207	}
	208
57c2ecd9 V	209	static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
	210	{
	211	u32 stat;
	212	unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
	213
	214	do {
	215	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	216	if (stat & WC)
	217	return 0;
	218	cpu_relax();
	219	} while (time_after(timeout, jiffies));
	220
	221	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
	222	if (stat & WC)
	223	return 0;
	224	return -ETIMEDOUT;
	225	}
	226
505a1495 SP	227	static int qspi_write_msg(struct ti_qspi qspi, struct spi_transfer t)
505a1495 SP	228	{
f682c4ff	229	int wlen, count, xfer_len;
505a1495 SP	230	unsigned int cmd;
505a1495 SP	231	const u8 *txbuf;
f682c4ff	232	u32 data;
505a1495 SP	233
	234	txbuf = t->tx_buf;
	235	cmd = qspi->cmd \| QSPI_WR_SNGL;
	236	count = t->len;
3ab54620	237	wlen = t->bits_per_word >> 3; /* in bytes */
f682c4ff	238	xfer_len = wlen;
505a1495 SP	239
505a1495 SP	240	while (count) {
00611047 M	241	if (qspi_is_busy(qspi))
	242	return -EBUSY;
	243
505a1495	244	switch (wlen) {
3ab54620	245	case 1:
505a1495 SP	246	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
505a1495 SP	247	cmd, qspi->dc, *txbuf);
f682c4ff V	248	if (count >= QSPI_WLEN_MAX_BYTES) {
	249	u32 txp = (u32 )txbuf;
	250
	251	data = cpu_to_be32(*txp++);
	252	writel(data, qspi->base +
	253	QSPI_SPI_DATA_REG_3);
	254	data = cpu_to_be32(*txp++);
	255	writel(data, qspi->base +
	256	QSPI_SPI_DATA_REG_2);
	257	data = cpu_to_be32(*txp++);
	258	writel(data, qspi->base +
	259	QSPI_SPI_DATA_REG_1);
	260	data = cpu_to_be32(*txp++);
	261	writel(data, qspi->base +
	262	QSPI_SPI_DATA_REG);
	263	xfer_len = QSPI_WLEN_MAX_BYTES;
	264	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	265	} else {
	266	writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
	267	cmd = qspi->cmd \| QSPI_WR_SNGL;
	268	xfer_len = wlen;
	269	cmd \|= QSPI_WLEN(wlen);
	270	}
505a1495	271	break;
3ab54620	272	case 2:
505a1495 SP	273	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
	274	cmd, qspi->dc, *txbuf);
	275	writew(((u16 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495	276	break;
3ab54620	277	case 4:
505a1495 SP	278	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
	279	cmd, qspi->dc, *txbuf);
	280	writel(((u32 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	281	break;
505a1495 SP	282	}
3ab54620 AL	283
3ab54620 AL	284	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
57c2ecd9	285	if (ti_qspi_poll_wc(qspi)) {
3ab54620 AL	286	dev_err(qspi->dev, "write timed out\n");
	287	return -ETIMEDOUT;
	288	}
f682c4ff V	289	txbuf += xfer_len;
f682c4ff V	290	count -= xfer_len;
505a1495 SP	291	}
	292
	293	return 0;
	294	}
	295
	296	static int qspi_read_msg(struct ti_qspi qspi, struct spi_transfer t)
	297	{
060556a9	298	int wlen, count;
505a1495 SP	299	unsigned int cmd;
	300	u8 *rxbuf;
	301
	302	rxbuf = t->rx_buf;
70e2e976 SP	303	cmd = qspi->cmd;
	304	switch (t->rx_nbits) {
	305	case SPI_NBITS_DUAL:
	306	cmd \|= QSPI_RD_DUAL;
	307	break;
	308	case SPI_NBITS_QUAD:
	309	cmd \|= QSPI_RD_QUAD;
	310	break;
	311	default:
	312	cmd \|= QSPI_RD_SNGL;
	313	break;
	314	}
505a1495	315	count = t->len;
3ab54620	316	wlen = t->bits_per_word >> 3; /* in bytes */
505a1495 SP	317
	318	while (count) {
	319	dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
00611047 M	320	if (qspi_is_busy(qspi))
	321	return -EBUSY;
	322
505a1495	323	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
57c2ecd9	324	if (ti_qspi_poll_wc(qspi)) {
505a1495 SP	325	dev_err(qspi->dev, "read timed out\n");
	326	return -ETIMEDOUT;
	327	}
	328	switch (wlen) {
3ab54620	329	case 1:
505a1495	330	*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
505a1495	331	break;
3ab54620	332	case 2:
505a1495	333	((u16 )rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
505a1495	334	break;
3ab54620	335	case 4:
505a1495	336	((u32 )rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
505a1495 SP	337	break;
505a1495 SP	338	}
3ab54620 AL	339	rxbuf += wlen;
3ab54620 AL	340	count -= wlen;
505a1495 SP	341	}
	342
	343	return 0;
	344	}
	345
	346	static int qspi_transfer_msg(struct ti_qspi qspi, struct spi_transfer t)
	347	{
	348	int ret;
	349
	350	if (t->tx_buf) {
	351	ret = qspi_write_msg(qspi, t);
	352	if (ret) {
	353	dev_dbg(qspi->dev, "Error while writing\n");
	354	return ret;
	355	}
	356	}
	357
	358	if (t->rx_buf) {
	359	ret = qspi_read_msg(qspi, t);
	360	if (ret) {
	361	dev_dbg(qspi->dev, "Error while reading\n");
	362	return ret;
	363	}
	364	}
	365
	366	return 0;
	367	}
	368
	369	static int ti_qspi_start_transfer_one(struct spi_master *master,
	370	struct spi_message *m)
	371	{
	372	struct ti_qspi *qspi = spi_master_get_devdata(master);
	373	struct spi_device *spi = m->spi;
	374	struct spi_transfer *t;
	375	int status = 0, ret;
	376	int frame_length;
	377
	378	/* setup device control reg */
	379	qspi->dc = 0;
	380
	381	if (spi->mode & SPI_CPHA)
	382	qspi->dc \|= QSPI_CKPHA(spi->chip_select);
	383	if (spi->mode & SPI_CPOL)
	384	qspi->dc \|= QSPI_CKPOL(spi->chip_select);
	385	if (spi->mode & SPI_CS_HIGH)
	386	qspi->dc \|= QSPI_CSPOL(spi->chip_select);
	387
	388	frame_length = (m->frame_length << 3) / spi->bits_per_word;
	389
	390	frame_length = clamp(frame_length, 0, QSPI_FRAME);
	391
	392	/* setup command reg */
	393	qspi->cmd = 0;
	394	qspi->cmd \|= QSPI_EN_CS(spi->chip_select);
	395	qspi->cmd \|= QSPI_FLEN(frame_length);
505a1495	396
505a1495 SP	397	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
	398
	399	mutex_lock(&qspi->list_lock);
	400
	401	list_for_each_entry(t, &m->transfers, transfer_list) {
	402	qspi->cmd \|= QSPI_WLEN(t->bits_per_word);
	403
	404	ret = qspi_transfer_msg(qspi, t);
	405	if (ret) {
	406	dev_dbg(qspi->dev, "transfer message failed\n");
b6460366	407	mutex_unlock(&qspi->list_lock);
505a1495 SP	408	return -EINVAL;
	409	}
	410
	411	m->actual_length += t->len;
	412	}
	413
	414	mutex_unlock(&qspi->list_lock);
	415
bc27a539	416	ti_qspi_write(qspi, qspi->cmd \| QSPI_INVAL, QSPI_SPI_CMD_REG);
505a1495 SP	417	m->status = status;
	418	spi_finalize_current_message(master);
	419
505a1495 SP	420	return status;
	421	}
	422
505a1495 SP	423	static int ti_qspi_runtime_resume(struct device *dev)
	424	{
	425	struct ti_qspi *qspi;
505a1495	426
f17414c4	427	qspi = dev_get_drvdata(dev);
505a1495 SP	428	ti_qspi_restore_ctx(qspi);
	429
	430	return 0;
	431	}
	432
	433	static const struct of_device_id ti_qspi_match[] = {
	434	{.compatible = "ti,dra7xxx-qspi" },
09222fc3	435	{.compatible = "ti,am4372-qspi" },
505a1495 SP	436	{},
505a1495 SP	437	};
e1432d30	438	MODULE_DEVICE_TABLE(of, ti_qspi_match);
505a1495 SP	439
	440	static int ti_qspi_probe(struct platform_device *pdev)
	441	{
	442	struct ti_qspi *qspi;
	443	struct spi_master *master;
6b3938ae	444	struct resource r, res_ctrl, *res_mmap;
505a1495 SP	445	struct device_node *np = pdev->dev.of_node;
	446	u32 max_freq;
	447	int ret = 0, num_cs, irq;
	448
	449	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	450	if (!master)
	451	return -ENOMEM;
	452
633795b9	453	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_RX_DUAL \| SPI_RX_QUAD;
505a1495	454
505a1495 SP	455	master->flags = SPI_MASTER_HALF_DUPLEX;
	456	master->setup = ti_qspi_setup;
	457	master->auto_runtime_pm = true;
	458	master->transfer_one_message = ti_qspi_start_transfer_one;
	459	master->dev.of_node = pdev->dev.of_node;
aa188f90 AL	460	master->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(16) \|
aa188f90 AL	461	SPI_BPW_MASK(8);
505a1495 SP	462
	463	if (!of_property_read_u32(np, "num-cs", &num_cs))
	464	master->num_chipselect = num_cs;
	465
505a1495 SP	466	qspi = spi_master_get_devdata(master);
	467	qspi->master = master;
	468	qspi->dev = &pdev->dev;
160a0613	469	platform_set_drvdata(pdev, qspi);
505a1495	470
6b3938ae SP	471	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
	472	if (r == NULL) {
	473	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	474	if (r == NULL) {
	475	dev_err(&pdev->dev, "missing platform data\n");
	476	return -ENODEV;
	477	}
	478	}
505a1495	479
6b3938ae SP	480	res_mmap = platform_get_resource_byname(pdev,
	481	IORESOURCE_MEM, "qspi_mmap");
	482	if (res_mmap == NULL) {
	483	res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	484	if (res_mmap == NULL) {
	485	dev_err(&pdev->dev,
	486	"memory mapped resource not required\n");
6b3938ae SP	487	}
	488	}
	489
	490	res_ctrl = platform_get_resource_byname(pdev,
	491	IORESOURCE_MEM, "qspi_ctrlmod");
	492	if (res_ctrl == NULL) {
	493	res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	494	if (res_ctrl == NULL) {
	495	dev_dbg(&pdev->dev,
	496	"control module resources not required\n");
	497	}
	498	}
505a1495 SP	499
	500	irq = platform_get_irq(pdev, 0);
	501	if (irq < 0) {
	502	dev_err(&pdev->dev, "no irq resource?\n");
	503	return irq;
	504	}
	505
505a1495 SP	506	mutex_init(&qspi->list_lock);
	507
	508	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	509	if (IS_ERR(qspi->base)) {
	510	ret = PTR_ERR(qspi->base);
	511	goto free_master;
	512	}
	513
6b3938ae SP	514	if (res_ctrl) {
	515	qspi->ctrl_mod = true;
	516	qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
	517	if (IS_ERR(qspi->ctrl_base)) {
	518	ret = PTR_ERR(qspi->ctrl_base);
	519	goto free_master;
	520	}
	521	}
	522
	523	if (res_mmap) {
	524	qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
	525	if (IS_ERR(qspi->mmap_base)) {
	526	ret = PTR_ERR(qspi->mmap_base);
	527	goto free_master;
	528	}
	529	}
	530
505a1495 SP	531	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	532	if (IS_ERR(qspi->fclk)) {
	533	ret = PTR_ERR(qspi->fclk);
	534	dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	535	}
	536
505a1495 SP	537	pm_runtime_use_autosuspend(&pdev->dev);
	538	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	539	pm_runtime_enable(&pdev->dev);
	540
	541	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
	542	qspi->spi_max_frequency = max_freq;
	543
7388c03b	544	ret = devm_spi_register_master(&pdev->dev, master);
505a1495 SP	545	if (ret)
	546	goto free_master;
	547
	548	return 0;
	549
	550	free_master:
	551	spi_master_put(master);
	552	return ret;
	553	}
	554
	555	static int ti_qspi_remove(struct platform_device *pdev)
	556	{
e6b5140b	557	pm_runtime_put_sync(&pdev->dev);
cbcabb7a SP	558	pm_runtime_disable(&pdev->dev);
cbcabb7a SP	559
505a1495 SP	560	return 0;
	561	}
	562
	563	static const struct dev_pm_ops ti_qspi_pm_ops = {
	564	.runtime_resume = ti_qspi_runtime_resume,
	565	};
	566
	567	static struct platform_driver ti_qspi_driver = {
	568	.probe = ti_qspi_probe,
dabefd56	569	.remove = ti_qspi_remove,
505a1495	570	.driver = {
5a33d30f	571	.name = "ti-qspi",
505a1495 SP	572	.pm = &ti_qspi_pm_ops,
	573	.of_match_table = ti_qspi_match,
	574	}
	575	};
	576
	577	module_platform_driver(ti_qspi_driver);
	578
	579	MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
	580	MODULE_LICENSE("GPL v2");
	581	MODULE_DESCRIPTION("TI QSPI controller driver");
5a33d30f	582	MODULE_ALIAS("platform:ti-qspi");