[linux-2.6-block.git] / drivers / spi / spi-ti-qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * Author: Sourav Poddar <sourav.poddar@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GPLv2.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>

#include <linux/spi/spi.h>

struct ti_qspi_regs {
	u32 clkctrl;
};

struct ti_qspi {
	struct completion       transfer_complete;

	/* IRQ synchronization */
	spinlock_t              lock;

	/* list synchronization */
	struct mutex            list_lock;

	struct spi_master	*master;
	void __iomem            *base;
	struct clk		*fclk;
	struct device           *dev;

	struct ti_qspi_regs     ctx_reg;

	u32 spi_max_frequency;
	u32 cmd;
	u32 dc;
	u32 stat;
};

#define QSPI_PID			(0x0)
#define QSPI_SYSCONFIG			(0x10)
#define QSPI_INTR_STATUS_RAW_SET	(0x20)
#define QSPI_INTR_STATUS_ENABLED_CLEAR	(0x24)
#define QSPI_INTR_ENABLE_SET_REG	(0x28)
#define QSPI_INTR_ENABLE_CLEAR_REG	(0x2c)
#define QSPI_SPI_CLOCK_CNTRL_REG	(0x40)
#define QSPI_SPI_DC_REG			(0x44)
#define QSPI_SPI_CMD_REG		(0x48)
#define QSPI_SPI_STATUS_REG		(0x4c)
#define QSPI_SPI_DATA_REG		(0x50)
#define QSPI_SPI_SETUP0_REG		(0x54)
#define QSPI_SPI_SWITCH_REG		(0x64)
#define QSPI_SPI_SETUP1_REG		(0x58)
#define QSPI_SPI_SETUP2_REG		(0x5c)
#define QSPI_SPI_SETUP3_REG		(0x60)
#define QSPI_SPI_DATA_REG_1		(0x68)
#define QSPI_SPI_DATA_REG_2		(0x6c)
#define QSPI_SPI_DATA_REG_3		(0x70)

#define QSPI_COMPLETION_TIMEOUT		msecs_to_jiffies(2000)

#define QSPI_FCLK			192000000

/* Clock Control */
#define QSPI_CLK_EN			(1 << 31)
#define QSPI_CLK_DIV_MAX		0xffff

/* Command */
#define QSPI_EN_CS(n)			(n << 28)
#define QSPI_WLEN(n)			((n - 1) << 19)
#define QSPI_3_PIN			(1 << 18)
#define QSPI_RD_SNGL			(1 << 16)
#define QSPI_WR_SNGL			(2 << 16)
#define QSPI_RD_DUAL			(3 << 16)
#define QSPI_RD_QUAD			(7 << 16)
#define QSPI_INVAL			(4 << 16)
#define QSPI_WC_CMD_INT_EN			(1 << 14)
#define QSPI_FLEN(n)			((n - 1) << 0)

/* STATUS REGISTER */
#define WC				0x02

/* INTERRUPT REGISTER */
#define QSPI_WC_INT_EN				(1 << 1)
#define QSPI_WC_INT_DISABLE			(1 << 1)

/* Device Control */
#define QSPI_DD(m, n)			(m << (3 + n * 8))
#define QSPI_CKPHA(n)			(1 << (2 + n * 8))
#define QSPI_CSPOL(n)			(1 << (1 + n * 8))
#define QSPI_CKPOL(n)			(1 << (n * 8))

#define	QSPI_FRAME			4096

#define QSPI_AUTOSUSPEND_TIMEOUT         2000

static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
		unsigned long reg)
{
	return readl(qspi->base + reg);
}

static inline void ti_qspi_write(struct ti_qspi *qspi,
		unsigned long val, unsigned long reg)
{
	writel(val, qspi->base + reg);
}

static int ti_qspi_setup(struct spi_device *spi)
{
	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
	int clk_div = 0, ret;
	u32 clk_ctrl_reg, clk_rate, clk_mask;

	if (spi->master->busy) {
		dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
		return -EBUSY;
	}

	if (!qspi->spi_max_frequency) {
		dev_err(qspi->dev, "spi max frequency not defined\n");
		return -EINVAL;
	}

	clk_rate = clk_get_rate(qspi->fclk);

	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;

	if (clk_div < 0) {
		dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
		return -EINVAL;
	}

	if (clk_div > QSPI_CLK_DIV_MAX) {
		dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
				QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
		return -EINVAL;
	}

	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
			qspi->spi_max_frequency, clk_div);

	ret = pm_runtime_get_sync(qspi->dev);
	if (ret) {
		dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);

	clk_ctrl_reg &= ~QSPI_CLK_EN;

	/* disable SCLK */
	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);

	/* enable SCLK */
	clk_mask = QSPI_CLK_EN | clk_div;
	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
	ctx_reg->clkctrl = clk_mask;

	pm_runtime_mark_last_busy(qspi->dev);
	ret = pm_runtime_put_autosuspend(qspi->dev);
	if (ret < 0) {
		dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
		return ret;
	}

	return 0;
}

static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;

	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
}

static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count, ret;
	unsigned int cmd;
	const u8 *txbuf;

	txbuf = t->tx_buf;
	cmd = qspi->cmd | QSPI_WR_SNGL;
	count = t->len;
	wlen = t->bits_per_word;

	while (count) {
		switch (wlen) {
		case 8:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
					cmd, qspi->dc, *txbuf);
			writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
			ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
			ret = wait_for_completion_timeout(&qspi->transfer_complete,
					QSPI_COMPLETION_TIMEOUT);
			if (ret == 0) {
				dev_err(qspi->dev, "write timed out\n");
				return -ETIMEDOUT;
			}
			txbuf += 1;
			count -= 1;
			break;
		case 16:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
					cmd, qspi->dc, *txbuf);
			writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
			ret = wait_for_completion_timeout(&qspi->transfer_complete,
				QSPI_COMPLETION_TIMEOUT);
			if (ret == 0) {
				dev_err(qspi->dev, "write timed out\n");
				return -ETIMEDOUT;
			}
			txbuf += 2;
			count -= 2;
			break;
		case 32:
			dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
					cmd, qspi->dc, *txbuf);
			writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
			ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
			ret = wait_for_completion_timeout(&qspi->transfer_complete,
				QSPI_COMPLETION_TIMEOUT);
			if (ret == 0) {
				dev_err(qspi->dev, "write timed out\n");
				return -ETIMEDOUT;
			}
			txbuf += 4;
			count -= 4;
			break;
		}
	}

	return 0;
}

static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int wlen, count, ret;
	unsigned int cmd;
	u8 *rxbuf;

	rxbuf = t->rx_buf;
	cmd = qspi->cmd | QSPI_RD_SNGL;
	count = t->len;
	wlen = t->bits_per_word;

	while (count) {
		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
		ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
		ret = wait_for_completion_timeout(&qspi->transfer_complete,
				QSPI_COMPLETION_TIMEOUT);
		if (ret == 0) {
			dev_err(qspi->dev, "read timed out\n");
			return -ETIMEDOUT;
		}
		switch (wlen) {
		case 8:
			*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
			rxbuf += 1;
			count -= 1;
			break;
		case 16:
			*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
			rxbuf += 2;
			count -= 2;
			break;
		case 32:
			*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
			rxbuf += 4;
			count -= 4;
			break;
		}
	}

	return 0;
}

static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
	int ret;

	if (t->tx_buf) {
		ret = qspi_write_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while writing\n");
			return ret;
		}
	}

	if (t->rx_buf) {
		ret = qspi_read_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "Error while reading\n");
			return ret;
		}
	}

	return 0;
}

static int ti_qspi_start_transfer_one(struct spi_master *master,
		struct spi_message *m)
{
	struct ti_qspi *qspi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	int status = 0, ret;
	int frame_length;

	/* setup device control reg */
	qspi->dc = 0;

	if (spi->mode & SPI_CPHA)
		qspi->dc |= QSPI_CKPHA(spi->chip_select);
	if (spi->mode & SPI_CPOL)
		qspi->dc |= QSPI_CKPOL(spi->chip_select);
	if (spi->mode & SPI_CS_HIGH)
		qspi->dc |= QSPI_CSPOL(spi->chip_select);

	frame_length = (m->frame_length << 3) / spi->bits_per_word;

	frame_length = clamp(frame_length, 0, QSPI_FRAME);

	/* setup command reg */
	qspi->cmd = 0;
	qspi->cmd |= QSPI_EN_CS(spi->chip_select);
	qspi->cmd |= QSPI_FLEN(frame_length);
	qspi->cmd |= QSPI_WC_CMD_INT_EN;

	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);

	mutex_lock(&qspi->list_lock);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		qspi->cmd |= QSPI_WLEN(t->bits_per_word);

		ret = qspi_transfer_msg(qspi, t);
		if (ret) {
			dev_dbg(qspi->dev, "transfer message failed\n");
			return -EINVAL;
		}

		m->actual_length += t->len;
	}

	mutex_unlock(&qspi->list_lock);

	m->status = status;
	spi_finalize_current_message(master);

	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);

	return status;
}

static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
{
	struct ti_qspi *qspi = dev_id;
	u16 int_stat;

	irqreturn_t ret = IRQ_HANDLED;

	spin_lock(&qspi->lock);

	int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
	qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);

	if (!int_stat) {
		dev_dbg(qspi->dev, "No IRQ triggered\n");
		ret = IRQ_NONE;
		goto out;
	}

	ret = IRQ_WAKE_THREAD;

	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
				QSPI_INTR_STATUS_ENABLED_CLEAR);

out:
	spin_unlock(&qspi->lock);

	return ret;
}

static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
{
	struct ti_qspi *qspi = dev_id;
	unsigned long flags;

	spin_lock_irqsave(&qspi->lock, flags);

	if (qspi->stat & WC)
		complete(&qspi->transfer_complete);

	spin_unlock_irqrestore(&qspi->lock, flags);

	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);

	return IRQ_HANDLED;
}

static int ti_qspi_runtime_resume(struct device *dev)
{
	struct ti_qspi      *qspi;
	struct spi_master       *master;

	master = dev_get_drvdata(dev);
	qspi = spi_master_get_devdata(master);
	ti_qspi_restore_ctx(qspi);

	return 0;
}

static const struct of_device_id ti_qspi_match[] = {
	{.compatible = "ti,dra7xxx-qspi" },
	{},
};
MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);

static int ti_qspi_probe(struct platform_device *pdev)
{
	struct  ti_qspi *qspi;
	struct spi_master *master;
	struct resource         *r;
	struct device_node *np = pdev->dev.of_node;
	u32 max_freq;
	int ret = 0, num_cs, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
	if (!master)
		return -ENOMEM;

	master->mode_bits = SPI_CPOL | SPI_CPHA;

	master->bus_num = -1;
	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->setup = ti_qspi_setup;
	master->auto_runtime_pm = true;
	master->transfer_one_message = ti_qspi_start_transfer_one;
	master->dev.of_node = pdev->dev.of_node;
	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);

	if (!of_property_read_u32(np, "num-cs", &num_cs))
		master->num_chipselect = num_cs;

	platform_set_drvdata(pdev, master);

	qspi = spi_master_get_devdata(master);
	qspi->master = master;
	qspi->dev = &pdev->dev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	spin_lock_init(&qspi->lock);
	mutex_init(&qspi->list_lock);

	qspi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(qspi->base)) {
		ret = PTR_ERR(qspi->base);
		goto free_master;
	}

	ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,
			ti_qspi_threaded_isr, 0,
			dev_name(&pdev->dev), qspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
				irq);
		goto free_master;
	}

	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(qspi->fclk)) {
		ret = PTR_ERR(qspi->fclk);
		dev_err(&pdev->dev, "could not get clk: %d\n", ret);
	}

	init_completion(&qspi->transfer_complete);

	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
		qspi->spi_max_frequency = max_freq;

	ret = spi_register_master(master);
	if (ret)
		goto free_master;

	return 0;

free_master:
	spi_master_put(master);
	return ret;
}

static int ti_qspi_remove(struct platform_device *pdev)
{
	struct	ti_qspi *qspi = platform_get_drvdata(pdev);

	spi_unregister_master(qspi->master);

	return 0;
}

static const struct dev_pm_ops ti_qspi_pm_ops = {
	.runtime_resume = ti_qspi_runtime_resume,
};

static struct platform_driver ti_qspi_driver = {
	.probe	= ti_qspi_probe,
	.remove	= ti_qspi_remove,
	.driver = {
		.name	= "ti,dra7xxx-qspi",
		.owner	= THIS_MODULE,
		.pm =   &ti_qspi_pm_ops,
		.of_match_table = ti_qspi_match,
	}
};

module_platform_driver(ti_qspi_driver);

MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI QSPI controller driver");
Commit	Line	Data
505a1495 SP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* Author: Sourav Poddar <sourav.poddar@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GPLv2.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/module.h>
	20	#include <linux/device.h>
	21	#include <linux/delay.h>
	22	#include <linux/dma-mapping.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/omap-dma.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29	#include <linux/slab.h>
	30	#include <linux/pm_runtime.h>
	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33	#include <linux/pinctrl/consumer.h>
	34
	35	#include <linux/spi/spi.h>
	36
	37	struct ti_qspi_regs {
	38	u32 clkctrl;
	39	};
	40
	41	struct ti_qspi {
	42	struct completion transfer_complete;
	43
	44	/* IRQ synchronization */
	45	spinlock_t lock;
	46
	47	/* list synchronization */
	48	struct mutex list_lock;
	49
	50	struct spi_master *master;
	51	void __iomem *base;
	52	struct clk *fclk;
	53	struct device *dev;
	54
	55	struct ti_qspi_regs ctx_reg;
	56
	57	u32 spi_max_frequency;
	58	u32 cmd;
	59	u32 dc;
	60	u32 stat;
	61	};
	62
	63	#define QSPI_PID (0x0)
	64	#define QSPI_SYSCONFIG (0x10)
65	#define QSPI_INTR_STATUS_RAW_SET (0x20)
66	#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
67	#define QSPI_INTR_ENABLE_SET_REG (0x28)
68	#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
69	#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
70	#define QSPI_SPI_DC_REG (0x44)
71	#define QSPI_SPI_CMD_REG (0x48)
72	#define QSPI_SPI_STATUS_REG (0x4c)
73	#define QSPI_SPI_DATA_REG (0x50)
74	#define QSPI_SPI_SETUP0_REG (0x54)
75	#define QSPI_SPI_SWITCH_REG (0x64)
76	#define QSPI_SPI_SETUP1_REG (0x58)
77	#define QSPI_SPI_SETUP2_REG (0x5c)
78	#define QSPI_SPI_SETUP3_REG (0x60)
79	#define QSPI_SPI_DATA_REG_1 (0x68)
80	#define QSPI_SPI_DATA_REG_2 (0x6c)
81	#define QSPI_SPI_DATA_REG_3 (0x70)
82
83	#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
84
85	#define QSPI_FCLK 192000000
86
87	/* Clock Control */
88	#define QSPI_CLK_EN (1 << 31)
89	#define QSPI_CLK_DIV_MAX 0xffff
90
91	/* Command */
92	#define QSPI_EN_CS(n) (n << 28)
93	#define QSPI_WLEN(n) ((n - 1) << 19)
94	#define QSPI_3_PIN (1 << 18)
95	#define QSPI_RD_SNGL (1 << 16)
96	#define QSPI_WR_SNGL (2 << 16)
97	#define QSPI_RD_DUAL (3 << 16)
98	#define QSPI_RD_QUAD (7 << 16)
99	#define QSPI_INVAL (4 << 16)
100	#define QSPI_WC_CMD_INT_EN (1 << 14)
101	#define QSPI_FLEN(n) ((n - 1) << 0)
102
103	/* STATUS REGISTER */
104	#define WC 0x02
105
106	/* INTERRUPT REGISTER */
107	#define QSPI_WC_INT_EN (1 << 1)
108	#define QSPI_WC_INT_DISABLE (1 << 1)
109
110	/* Device Control */
111	#define QSPI_DD(m, n) (m << (3 + n * 8))
112	#define QSPI_CKPHA(n) (1 << (2 + n * 8))
113	#define QSPI_CSPOL(n) (1 << (1 + n * 8))
114	#define QSPI_CKPOL(n) (1 << (n * 8))
115
116	#define QSPI_FRAME 4096
117
118	#define QSPI_AUTOSUSPEND_TIMEOUT 2000
119
120	static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
121	unsigned long reg)
122	{
123	return readl(qspi->base + reg);
124	}
125
126	static inline void ti_qspi_write(struct ti_qspi *qspi,
127	unsigned long val, unsigned long reg)
128	{
129	writel(val, qspi->base + reg);
130	}
131
132	static int ti_qspi_setup(struct spi_device *spi)
133	{
134	struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
135	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
136	int clk_div = 0, ret;
137	u32 clk_ctrl_reg, clk_rate, clk_mask;
138
139	if (spi->master->busy) {
140	dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
141	return -EBUSY;
142	}
143
144	if (!qspi->spi_max_frequency) {
145	dev_err(qspi->dev, "spi max frequency not defined\n");
146	return -EINVAL;
147	}
148
149	clk_rate = clk_get_rate(qspi->fclk);
150
151	clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
152
153	if (clk_div < 0) {
154	dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
155	return -EINVAL;
156	}
157
158	if (clk_div > QSPI_CLK_DIV_MAX) {
159	dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
160	QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
161	return -EINVAL;
162	}
163
164	dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
165	qspi->spi_max_frequency, clk_div);
166
167	ret = pm_runtime_get_sync(qspi->dev);
168	if (ret) {
169	dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
170	return ret;
171	}
172
173	clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
174
175	clk_ctrl_reg &= ~QSPI_CLK_EN;
176
177	/* disable SCLK */
178	ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
179
180	/* enable SCLK */
181	clk_mask = QSPI_CLK_EN \| clk_div;
182	ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
183	ctx_reg->clkctrl = clk_mask;
184
185	pm_runtime_mark_last_busy(qspi->dev);
186	ret = pm_runtime_put_autosuspend(qspi->dev);
187	if (ret < 0) {
188	dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
189	return ret;
190	}
191
192	return 0;
193	}
194
195	static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
196	{
197	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
198
199	ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
200	}
201
202	static int qspi_write_msg(struct ti_qspi qspi, struct spi_transfer t)
203	{
204	int wlen, count, ret;
205	unsigned int cmd;
206	const u8 *txbuf;
207
208	txbuf = t->tx_buf;
209	cmd = qspi->cmd \| QSPI_WR_SNGL;
210	count = t->len;
211	wlen = t->bits_per_word;
212
213	while (count) {
214	switch (wlen) {
215	case 8:
216	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
217	cmd, qspi->dc, *txbuf);
218	writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
219	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
220	ret = wait_for_completion_timeout(&qspi->transfer_complete,
221	QSPI_COMPLETION_TIMEOUT);
222	if (ret == 0) {
223	dev_err(qspi->dev, "write timed out\n");
224	return -ETIMEDOUT;
225	}
226	txbuf += 1;
227	count -= 1;
228	break;
229	case 16:
230	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
231	cmd, qspi->dc, *txbuf);
232	writew(((u16 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
233	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
234	ret = wait_for_completion_timeout(&qspi->transfer_complete,
235	QSPI_COMPLETION_TIMEOUT);
236	if (ret == 0) {
237	dev_err(qspi->dev, "write timed out\n");
238	return -ETIMEDOUT;
239	}
240	txbuf += 2;
241	count -= 2;
242	break;
243	case 32:
244	dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
245	cmd, qspi->dc, *txbuf);
246	writel(((u32 )txbuf), qspi->base + QSPI_SPI_DATA_REG);
247	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
248	ret = wait_for_completion_timeout(&qspi->transfer_complete,
249	QSPI_COMPLETION_TIMEOUT);
250	if (ret == 0) {
251	dev_err(qspi->dev, "write timed out\n");
252	return -ETIMEDOUT;
253	}
254	txbuf += 4;
255	count -= 4;
256	break;
257	}
258	}
259
260	return 0;
261	}
262
263	static int qspi_read_msg(struct ti_qspi qspi, struct spi_transfer t)
264	{
265	int wlen, count, ret;
266	unsigned int cmd;
267	u8 *rxbuf;
268
269	rxbuf = t->rx_buf;
270	cmd = qspi->cmd \| QSPI_RD_SNGL;
271	count = t->len;
272	wlen = t->bits_per_word;
273
274	while (count) {
275	dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
276	ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
277	ret = wait_for_completion_timeout(&qspi->transfer_complete,
278	QSPI_COMPLETION_TIMEOUT);
279	if (ret == 0) {
280	dev_err(qspi->dev, "read timed out\n");
281	return -ETIMEDOUT;
282	}
283	switch (wlen) {
284	case 8:
285	*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
286	rxbuf += 1;
287	count -= 1;
288	break;
289	case 16:
290	((u16 )rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
291	rxbuf += 2;
292	count -= 2;
293	break;
294	case 32:
295	((u32 )rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
296	rxbuf += 4;
297	count -= 4;
298	break;
299	}
300	}
301
302	return 0;
303	}
304
305	static int qspi_transfer_msg(struct ti_qspi qspi, struct spi_transfer t)
306	{
307	int ret;
308
309	if (t->tx_buf) {
310	ret = qspi_write_msg(qspi, t);
311	if (ret) {
312	dev_dbg(qspi->dev, "Error while writing\n");
313	return ret;
314	}
315	}
316
317	if (t->rx_buf) {
318	ret = qspi_read_msg(qspi, t);
319	if (ret) {
320	dev_dbg(qspi->dev, "Error while reading\n");
321	return ret;
322	}
323	}
324
325	return 0;
326	}
327
328	static int ti_qspi_start_transfer_one(struct spi_master *master,
329	struct spi_message *m)
330	{
331	struct ti_qspi *qspi = spi_master_get_devdata(master);
332	struct spi_device *spi = m->spi;
333	struct spi_transfer *t;
334	int status = 0, ret;
335	int frame_length;
336
337	/* setup device control reg */
338	qspi->dc = 0;
339
340	if (spi->mode & SPI_CPHA)
341	qspi->dc \|= QSPI_CKPHA(spi->chip_select);
342	if (spi->mode & SPI_CPOL)
343	qspi->dc \|= QSPI_CKPOL(spi->chip_select);
344	if (spi->mode & SPI_CS_HIGH)
345	qspi->dc \|= QSPI_CSPOL(spi->chip_select);
346
347	frame_length = (m->frame_length << 3) / spi->bits_per_word;
348
349	frame_length = clamp(frame_length, 0, QSPI_FRAME);
350
351	/* setup command reg */
352	qspi->cmd = 0;
353	qspi->cmd \|= QSPI_EN_CS(spi->chip_select);
354	qspi->cmd \|= QSPI_FLEN(frame_length);
355	qspi->cmd \|= QSPI_WC_CMD_INT_EN;
356
357	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
358	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
359
360	mutex_lock(&qspi->list_lock);
361
362	list_for_each_entry(t, &m->transfers, transfer_list) {
363	qspi->cmd \|= QSPI_WLEN(t->bits_per_word);
364
365	ret = qspi_transfer_msg(qspi, t);
366	if (ret) {
367	dev_dbg(qspi->dev, "transfer message failed\n");
368	return -EINVAL;
369	}
370
371	m->actual_length += t->len;
372	}
373
374	mutex_unlock(&qspi->list_lock);
375
376	m->status = status;
377	spi_finalize_current_message(master);
378
379	ti_qspi_write(qspi, qspi->cmd \| QSPI_INVAL, QSPI_SPI_CMD_REG);
380
381	return status;
382	}
383
384	static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
385	{
386	struct ti_qspi *qspi = dev_id;
387	u16 int_stat;
388
389	irqreturn_t ret = IRQ_HANDLED;
390
391	spin_lock(&qspi->lock);
392
393	int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
394	qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
395
396	if (!int_stat) {
397	dev_dbg(qspi->dev, "No IRQ triggered\n");
398	ret = IRQ_NONE;
399	goto out;
400	}
401
402	ret = IRQ_WAKE_THREAD;
403
404	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
405	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
406	QSPI_INTR_STATUS_ENABLED_CLEAR);
407
408	out:
409	spin_unlock(&qspi->lock);
410
411	return ret;
412	}
413
414	static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
415	{
416	struct ti_qspi *qspi = dev_id;
417	unsigned long flags;
418
419	spin_lock_irqsave(&qspi->lock, flags);
420
421	if (qspi->stat & WC)
422	complete(&qspi->transfer_complete);
423
424	spin_unlock_irqrestore(&qspi->lock, flags);
425
426	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
427
428	return IRQ_HANDLED;
429	}
430
431	static int ti_qspi_runtime_resume(struct device *dev)
432	{
433	struct ti_qspi *qspi;
434	struct spi_master *master;
435
436	master = dev_get_drvdata(dev);
437	qspi = spi_master_get_devdata(master);
438	ti_qspi_restore_ctx(qspi);
439
440	return 0;
441	}
442
443	static const struct of_device_id ti_qspi_match[] = {
444	{.compatible = "ti,dra7xxx-qspi" },
445	{},
446	};
447	MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);
448
449	static int ti_qspi_probe(struct platform_device *pdev)
450	{
451	struct ti_qspi *qspi;
452	struct spi_master *master;
453	struct resource *r;
454	struct device_node *np = pdev->dev.of_node;
455	u32 max_freq;
456	int ret = 0, num_cs, irq;
457
458	master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
459	if (!master)
460	return -ENOMEM;
461
462	master->mode_bits = SPI_CPOL \| SPI_CPHA;
463
464	master->bus_num = -1;
465	master->flags = SPI_MASTER_HALF_DUPLEX;
466	master->setup = ti_qspi_setup;
467	master->auto_runtime_pm = true;
468	master->transfer_one_message = ti_qspi_start_transfer_one;
469	master->dev.of_node = pdev->dev.of_node;
470	master->bits_per_word_mask = BIT(32 - 1) \| BIT(16 - 1) \| BIT(8 - 1);
471
472	if (!of_property_read_u32(np, "num-cs", &num_cs))
473	master->num_chipselect = num_cs;
474
475	platform_set_drvdata(pdev, master);
476
477	qspi = spi_master_get_devdata(master);
478	qspi->master = master;
479	qspi->dev = &pdev->dev;
480
481	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
482
483	irq = platform_get_irq(pdev, 0);
484	if (irq < 0) {
485	dev_err(&pdev->dev, "no irq resource?\n");
486	return irq;
487	}
488
489	spin_lock_init(&qspi->lock);
490	mutex_init(&qspi->list_lock);
491
492	qspi->base = devm_ioremap_resource(&pdev->dev, r);
493	if (IS_ERR(qspi->base)) {
494	ret = PTR_ERR(qspi->base);
495	goto free_master;
496	}
497
498	ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,
499	ti_qspi_threaded_isr, 0,
500	dev_name(&pdev->dev), qspi);
501	if (ret < 0) {
502	dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
503	irq);
504	goto free_master;
505	}
506
507	qspi->fclk = devm_clk_get(&pdev->dev, "fck");
508	if (IS_ERR(qspi->fclk)) {
509	ret = PTR_ERR(qspi->fclk);
510	dev_err(&pdev->dev, "could not get clk: %d\n", ret);
511	}
512
513	init_completion(&qspi->transfer_complete);
514
515	pm_runtime_use_autosuspend(&pdev->dev);
516	pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
517	pm_runtime_enable(&pdev->dev);
518
519	if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
520	qspi->spi_max_frequency = max_freq;
521
522	ret = spi_register_master(master);
523	if (ret)
524	goto free_master;
525
526	return 0;
527
528	free_master:
529	spi_master_put(master);
530	return ret;
531	}
532
533	static int ti_qspi_remove(struct platform_device *pdev)
534	{
535	struct ti_qspi *qspi = platform_get_drvdata(pdev);
536
537	spi_unregister_master(qspi->master);
538
539	return 0;
540	}
541
542	static const struct dev_pm_ops ti_qspi_pm_ops = {
543	.runtime_resume = ti_qspi_runtime_resume,
544	};
545
546	static struct platform_driver ti_qspi_driver = {
547	.probe = ti_qspi_probe,
548	.remove = ti_qspi_remove,
549	.driver = {
550	.name = "ti,dra7xxx-qspi",
551	.owner = THIS_MODULE,
552	.pm = &ti_qspi_pm_ops,
553	.of_match_table = ti_qspi_match,
554	}
555	};
556
557	module_platform_driver(ti_qspi_driver);
558
559	MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
560	MODULE_LICENSE("GPL v2");
561	MODULE_DESCRIPTION("TI QSPI controller driver");