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Merge tag 'amd-drm-fixes-5.10-2020-11-25' of git://people.freedesktop.org/~agd5f...
[linux-block.git] / drivers / spi / spi-tegra20-slink.c
CommitLineData
9952f691 1// SPDX-License-Identifier: GPL-2.0-only
dc4dc360
LD		 2/*
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 *
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
dc4dc360
LD		 6 */
7
8#include <linux/clk.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmapool.h>
14#include <linux/err.h>
dc4dc360
LD		 15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
ff2251e3 24#include <linux/reset.h>
dc4dc360 25#include <linux/spi/spi.h>
dc4dc360
LD		 26
27#define SLINK_COMMAND 0x000
28#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
29#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
30#define SLINK_BOTH_EN (1 << 10)
31#define SLINK_CS_SW (1 << 11)
32#define SLINK_CS_VALUE (1 << 12)
33#define SLINK_CS_POLARITY (1 << 13)
34#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
35#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
36#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
37#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
38#define SLINK_IDLE_SDA_MASK (3 << 16)
39#define SLINK_CS_POLARITY1 (1 << 20)
40#define SLINK_CK_SDA (1 << 21)
41#define SLINK_CS_POLARITY2 (1 << 22)
42#define SLINK_CS_POLARITY3 (1 << 23)
43#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
44#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
45#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
46#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
47#define SLINK_IDLE_SCLK_MASK (3 << 24)
48#define SLINK_M_S (1 << 28)
49#define SLINK_WAIT (1 << 29)
50#define SLINK_GO (1 << 30)
51#define SLINK_ENB (1 << 31)
52
53#define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
54
55#define SLINK_COMMAND2 0x004
56#define SLINK_LSBFE (1 << 0)
57#define SLINK_SSOE (1 << 1)
58#define SLINK_SPIE (1 << 4)
59#define SLINK_BIDIROE (1 << 6)
60#define SLINK_MODFEN (1 << 7)
61#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
62#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
63#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
64#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
65#define SLINK_FIFO_REFILLS_0 (0 << 22)
66#define SLINK_FIFO_REFILLS_1 (1 << 22)
67#define SLINK_FIFO_REFILLS_2 (2 << 22)
68#define SLINK_FIFO_REFILLS_3 (3 << 22)
69#define SLINK_FIFO_REFILLS_MASK (3 << 22)
70#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
71#define SLINK_SPC0 (1 << 29)
72#define SLINK_TXEN (1 << 30)
73#define SLINK_RXEN (1 << 31)
74
75#define SLINK_STATUS 0x008
76#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
77#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
78#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
79#define SLINK_MODF (1 << 16)
80#define SLINK_RX_UNF (1 << 18)
81#define SLINK_TX_OVF (1 << 19)
82#define SLINK_TX_FULL (1 << 20)
83#define SLINK_TX_EMPTY (1 << 21)
84#define SLINK_RX_FULL (1 << 22)
85#define SLINK_RX_EMPTY (1 << 23)
86#define SLINK_TX_UNF (1 << 24)
87#define SLINK_RX_OVF (1 << 25)
88#define SLINK_TX_FLUSH (1 << 26)
89#define SLINK_RX_FLUSH (1 << 27)
90#define SLINK_SCLK (1 << 28)
91#define SLINK_ERR (1 << 29)
92#define SLINK_RDY (1 << 30)
93#define SLINK_BSY (1 << 31)
94#define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
95 SLINK_TX_UNF | SLINK_RX_OVF)
96
97#define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
98
99#define SLINK_MAS_DATA 0x010
100#define SLINK_SLAVE_DATA 0x014
101
102#define SLINK_DMA_CTL 0x018
103#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
104#define SLINK_TX_TRIG_1 (0 << 16)
105#define SLINK_TX_TRIG_4 (1 << 16)
106#define SLINK_TX_TRIG_8 (2 << 16)
107#define SLINK_TX_TRIG_16 (3 << 16)
108#define SLINK_TX_TRIG_MASK (3 << 16)
109#define SLINK_RX_TRIG_1 (0 << 18)
110#define SLINK_RX_TRIG_4 (1 << 18)
111#define SLINK_RX_TRIG_8 (2 << 18)
112#define SLINK_RX_TRIG_16 (3 << 18)
113#define SLINK_RX_TRIG_MASK (3 << 18)
114#define SLINK_PACKED (1 << 20)
115#define SLINK_PACK_SIZE_4 (0 << 21)
116#define SLINK_PACK_SIZE_8 (1 << 21)
117#define SLINK_PACK_SIZE_16 (2 << 21)
118#define SLINK_PACK_SIZE_32 (3 << 21)
119#define SLINK_PACK_SIZE_MASK (3 << 21)
120#define SLINK_IE_TXC (1 << 26)
121#define SLINK_IE_RXC (1 << 27)
122#define SLINK_DMA_EN (1 << 31)
123
124#define SLINK_STATUS2 0x01c
125#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
126#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
127#define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
128
129#define SLINK_TX_FIFO 0x100
130#define SLINK_RX_FIFO 0x180
131
132#define DATA_DIR_TX (1 << 0)
133#define DATA_DIR_RX (1 << 1)
134
135#define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
136
137#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
138#define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
139#define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
140
141#define SLINK_STATUS2_RESET \
142 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
143
144#define MAX_CHIP_SELECT 4
145#define SLINK_FIFO_DEPTH 32
146
147struct tegra_slink_chip_data {
148 bool cs_hold_time;
149};
150
151struct tegra_slink_data {
152 struct device *dev;
153 struct spi_master *master;
154 const struct tegra_slink_chip_data *chip_data;
155 spinlock_t lock;
156
157 struct clk *clk;
ff2251e3 158 struct reset_control *rst;
dc4dc360
LD		 159 void __iomem *base;
160 phys_addr_t phys;
161 unsigned irq;
dc4dc360
LD		 162 u32 cur_speed;
163
164 struct spi_device *cur_spi;
165 unsigned cur_pos;
166 unsigned cur_len;
167 unsigned words_per_32bit;
168 unsigned bytes_per_word;
169 unsigned curr_dma_words;
170 unsigned cur_direction;
171
172 unsigned cur_rx_pos;
173 unsigned cur_tx_pos;
174
175 unsigned dma_buf_size;
176 unsigned max_buf_size;
177 bool is_curr_dma_xfer;
dc4dc360
LD		 178
179 struct completion rx_dma_complete;
180 struct completion tx_dma_complete;
181
182 u32 tx_status;
183 u32 rx_status;
184 u32 status_reg;
185 bool is_packed;
5fd38677 186 u32 packed_size;
dc4dc360
LD		 187
188 u32 command_reg;
189 u32 command2_reg;
190 u32 dma_control_reg;
191 u32 def_command_reg;
192 u32 def_command2_reg;
193
194 struct completion xfer_completion;
195 struct spi_transfer *curr_xfer;
196 struct dma_chan *rx_dma_chan;
197 u32 *rx_dma_buf;
198 dma_addr_t rx_dma_phys;
199 struct dma_async_tx_descriptor *rx_dma_desc;
200
201 struct dma_chan *tx_dma_chan;
202 u32 *tx_dma_buf;
203 dma_addr_t tx_dma_phys;
204 struct dma_async_tx_descriptor *tx_dma_desc;
205};
206
207static int tegra_slink_runtime_suspend(struct device *dev);
208static int tegra_slink_runtime_resume(struct device *dev);
209
5fd38677 210static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
dc4dc360
LD		 211 unsigned long reg)
212{
213 return readl(tspi->base + reg);
214}
215
216static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
5fd38677 217 u32 val, unsigned long reg)
dc4dc360
LD		 218{
219 writel(val, tspi->base + reg);
220
221 /* Read back register to make sure that register writes completed */
222 if (reg != SLINK_TX_FIFO)
223 readl(tspi->base + SLINK_MAS_DATA);
224}
225
226static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
227{
5fd38677 228 u32 val_write;
dc4dc360 229
5fd38677 230 tegra_slink_readl(tspi, SLINK_STATUS);
dc4dc360
LD		 231
232 /* Write 1 to clear status register */
233 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
234 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
235}
236
5fd38677 237static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
dc4dc360
LD		 238 struct spi_transfer *t)
239{
dc4dc360
LD		 240 switch (tspi->bytes_per_word) {
241 case 0:
5fd38677 242 return SLINK_PACK_SIZE_4;
dc4dc360 243 case 1:
5fd38677 244 return SLINK_PACK_SIZE_8;
dc4dc360 245 case 2:
5fd38677 246 return SLINK_PACK_SIZE_16;
dc4dc360 247 case 4:
5fd38677 248 return SLINK_PACK_SIZE_32;
dc4dc360 249 default:
5fd38677 250 return 0;
dc4dc360 251 }
dc4dc360
LD		 252}
253
254static unsigned tegra_slink_calculate_curr_xfer_param(
255 struct spi_device *spi, struct tegra_slink_data *tspi,
256 struct spi_transfer *t)
257{
258 unsigned remain_len = t->len - tspi->cur_pos;
259 unsigned max_word;
3cb7b407 260 unsigned bits_per_word;
dc4dc360
LD		 261 unsigned max_len;
262 unsigned total_fifo_words;
263
766ed704 264 bits_per_word = t->bits_per_word;
e91d2352 265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
dc4dc360
LD		 266
267 if (bits_per_word == 8 || bits_per_word == 16) {
2172a332 268 tspi->is_packed = true;
dc4dc360
LD		 269 tspi->words_per_32bit = 32/bits_per_word;
270 } else {
2172a332 271 tspi->is_packed = false;
dc4dc360
LD		 272 tspi->words_per_32bit = 1;
273 }
274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
275
276 if (tspi->is_packed) {
277 max_len = min(remain_len, tspi->max_buf_size);
278 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
279 total_fifo_words = max_len/4;
280 } else {
281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
282 max_word = min(max_word, tspi->max_buf_size/4);
283 tspi->curr_dma_words = max_word;
284 total_fifo_words = max_word;
285 }
286 return total_fifo_words;
287}
288
289static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
290 struct tegra_slink_data *tspi, struct spi_transfer *t)
291{
292 unsigned nbytes;
293 unsigned tx_empty_count;
5fd38677 294 u32 fifo_status;
dc4dc360
LD		 295 unsigned max_n_32bit;
296 unsigned i, count;
dc4dc360
LD		 297 unsigned int written_words;
298 unsigned fifo_words_left;
299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
300
301 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
302 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
303
304 if (tspi->is_packed) {
305 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
306 written_words = min(fifo_words_left, tspi->curr_dma_words);
307 nbytes = written_words * tspi->bytes_per_word;
308 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
309 for (count = 0; count < max_n_32bit; count++) {
5fd38677 310 u32 x = 0;
dc4dc360 311 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
5fd38677 312 x |= (u32)(*tx_buf++) << (i * 8);
dc4dc360
LD		 313 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
314 }
315 } else {
316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
317 written_words = max_n_32bit;
318 nbytes = written_words * tspi->bytes_per_word;
319 for (count = 0; count < max_n_32bit; count++) {
5fd38677 320 u32 x = 0;
dc4dc360
LD		 321 for (i = 0; nbytes && (i < tspi->bytes_per_word);
322 i++, nbytes--)
5fd38677 323 x |= (u32)(*tx_buf++) << (i * 8);
dc4dc360
LD		 324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
325 }
326 }
327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
328 return written_words;
329}
330
331static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
332 struct tegra_slink_data *tspi, struct spi_transfer *t)
333{
334 unsigned rx_full_count;
5fd38677 335 u32 fifo_status;
dc4dc360 336 unsigned i, count;
dc4dc360
LD		 337 unsigned int read_words = 0;
338 unsigned len;
339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
340
341 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
342 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
343 if (tspi->is_packed) {
344 len = tspi->curr_dma_words * tspi->bytes_per_word;
345 for (count = 0; count < rx_full_count; count++) {
5fd38677 346 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
dc4dc360
LD		 347 for (i = 0; len && (i < 4); i++, len--)
348 *rx_buf++ = (x >> i*8) & 0xFF;
349 }
350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
351 read_words += tspi->curr_dma_words;
352 } else {
dc4dc360 353 for (count = 0; count < rx_full_count; count++) {
5fd38677 354 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
dc4dc360
LD		 355 for (i = 0; (i < tspi->bytes_per_word); i++)
356 *rx_buf++ = (x >> (i*8)) & 0xFF;
357 }
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
359 read_words += rx_full_count;
360 }
361 return read_words;
362}
363
364static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
365 struct tegra_slink_data *tspi, struct spi_transfer *t)
366{
dc4dc360
LD		 367 /* Make the dma buffer to read by cpu */
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
369 tspi->dma_buf_size, DMA_TO_DEVICE);
370
371 if (tspi->is_packed) {
5fd38677 372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
dc4dc360
LD		 373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
374 } else {
375 unsigned int i;
376 unsigned int count;
377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
dc4dc360
LD		 379
380 for (count = 0; count < tspi->curr_dma_words; count++) {
5fd38677 381 u32 x = 0;
dc4dc360
LD		 382 for (i = 0; consume && (i < tspi->bytes_per_word);
383 i++, consume--)
5fd38677 384 x |= (u32)(*tx_buf++) << (i * 8);
dc4dc360
LD		 385 tspi->tx_dma_buf[count] = x;
386 }
387 }
388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
389
390 /* Make the dma buffer to read by dma */
391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
392 tspi->dma_buf_size, DMA_TO_DEVICE);
393}
394
395static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
396 struct tegra_slink_data *tspi, struct spi_transfer *t)
397{
398 unsigned len;
399
400 /* Make the dma buffer to read by cpu */
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
402 tspi->dma_buf_size, DMA_FROM_DEVICE);
403
404 if (tspi->is_packed) {
405 len = tspi->curr_dma_words * tspi->bytes_per_word;
406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
407 } else {
408 unsigned int i;
409 unsigned int count;
410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
5fd38677 411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
dc4dc360 412
dc4dc360 413 for (count = 0; count < tspi->curr_dma_words; count++) {
5fd38677 414 u32 x = tspi->rx_dma_buf[count] & rx_mask;
dc4dc360
LD		 415 for (i = 0; (i < tspi->bytes_per_word); i++)
416 *rx_buf++ = (x >> (i*8)) & 0xFF;
417 }
418 }
419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
420
421 /* Make the dma buffer to read by dma */
422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
424}
425
426static void tegra_slink_dma_complete(void *args)
427{
428 struct completion *dma_complete = args;
429
430 complete(dma_complete);
431}
432
433static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
434{
16735d02 435 reinit_completion(&tspi->tx_dma_complete);
dc4dc360
LD		 436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
72919f34 438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
dc4dc360
LD		 439 if (!tspi->tx_dma_desc) {
440 dev_err(tspi->dev, "Not able to get desc for Tx\n");
441 return -EIO;
442 }
443
444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
446
447 dmaengine_submit(tspi->tx_dma_desc);
448 dma_async_issue_pending(tspi->tx_dma_chan);
449 return 0;
450}
451
452static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
453{
16735d02 454 reinit_completion(&tspi->rx_dma_complete);
dc4dc360
LD		 455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
72919f34 457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
dc4dc360
LD		 458 if (!tspi->rx_dma_desc) {
459 dev_err(tspi->dev, "Not able to get desc for Rx\n");
460 return -EIO;
461 }
462
463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
465
466 dmaengine_submit(tspi->rx_dma_desc);
467 dma_async_issue_pending(tspi->rx_dma_chan);
468 return 0;
469}
470
471static int tegra_slink_start_dma_based_transfer(
472 struct tegra_slink_data *tspi, struct spi_transfer *t)
473{
5fd38677 474 u32 val;
dc4dc360
LD		 475 unsigned int len;
476 int ret = 0;
5fd38677 477 u32 status;
dc4dc360
LD		 478
479 /* Make sure that Rx and Tx fifo are empty */
480 status = tegra_slink_readl(tspi, SLINK_STATUS);
481 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
5fd38677
MN		 482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
483 (unsigned)status);
dc4dc360
LD		 484 return -EIO;
485 }
486
487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
488 val |= tspi->packed_size;
489 if (tspi->is_packed)
490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
491 4) * 4;
492 else
493 len = tspi->curr_dma_words * 4;
494
495 /* Set attention level based on length of transfer */
496 if (len & 0xF)
497 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
498 else if (((len) >> 4) & 0x1)
499 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
500 else
501 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
502
503 if (tspi->cur_direction & DATA_DIR_TX)
504 val |= SLINK_IE_TXC;
505
506 if (tspi->cur_direction & DATA_DIR_RX)
507 val |= SLINK_IE_RXC;
508
509 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
510 tspi->dma_control_reg = val;
511
512 if (tspi->cur_direction & DATA_DIR_TX) {
513 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
514 wmb();
515 ret = tegra_slink_start_tx_dma(tspi, len);
516 if (ret < 0) {
517 dev_err(tspi->dev,
518 "Starting tx dma failed, err %d\n", ret);
519 return ret;
520 }
521
522 /* Wait for tx fifo to be fill before starting slink */
5fd38677
MN		 523 status = tegra_slink_readl(tspi, SLINK_STATUS);
524 while (!(status & SLINK_TX_FULL))
525 status = tegra_slink_readl(tspi, SLINK_STATUS);
dc4dc360
LD		 526 }
527
528 if (tspi->cur_direction & DATA_DIR_RX) {
529 /* Make the dma buffer to read by dma */
530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
531 tspi->dma_buf_size, DMA_FROM_DEVICE);
532
533 ret = tegra_slink_start_rx_dma(tspi, len);
534 if (ret < 0) {
535 dev_err(tspi->dev,
536 "Starting rx dma failed, err %d\n", ret);
537 if (tspi->cur_direction & DATA_DIR_TX)
538 dmaengine_terminate_all(tspi->tx_dma_chan);
539 return ret;
540 }
541 }
542 tspi->is_curr_dma_xfer = true;
543 if (tspi->is_packed) {
544 val |= SLINK_PACKED;
545 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
546 /* HW need small delay after settign Packed mode */
547 udelay(1);
548 }
549 tspi->dma_control_reg = val;
550
551 val |= SLINK_DMA_EN;
552 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
553 return ret;
554}
555
556static int tegra_slink_start_cpu_based_transfer(
557 struct tegra_slink_data *tspi, struct spi_transfer *t)
558{
5fd38677 559 u32 val;
dc4dc360
LD		 560 unsigned cur_words;
561
562 val = tspi->packed_size;
563 if (tspi->cur_direction & DATA_DIR_TX)
564 val |= SLINK_IE_TXC;
565
566 if (tspi->cur_direction & DATA_DIR_RX)
567 val |= SLINK_IE_RXC;
568
569 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
570 tspi->dma_control_reg = val;
571
572 if (tspi->cur_direction & DATA_DIR_TX)
573 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
574 else
575 cur_words = tspi->curr_dma_words;
576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
578 tspi->dma_control_reg = val;
579
580 tspi->is_curr_dma_xfer = false;
581 if (tspi->is_packed) {
582 val |= SLINK_PACKED;
583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
584 udelay(1);
585 wmb();
586 }
587 tspi->dma_control_reg = val;
588 val |= SLINK_DMA_EN;
589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
590 return 0;
591}
592
593static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
594 bool dma_to_memory)
595{
596 struct dma_chan *dma_chan;
597 u32 *dma_buf;
598 dma_addr_t dma_phys;
599 int ret;
600 struct dma_slave_config dma_sconfig;
dc4dc360 601
912a7df4 602 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
7708aff1
KK		 603 if (IS_ERR(dma_chan))
604 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
605 "Dma channel is not available\n");
dc4dc360
LD		 606
607 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
608 &dma_phys, GFP_KERNEL);
609 if (!dma_buf) {
610 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
611 dma_release_channel(dma_chan);
612 return -ENOMEM;
613 }
614
dc4dc360
LD		 615 if (dma_to_memory) {
616 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
617 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
618 dma_sconfig.src_maxburst = 0;
619 } else {
620 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
621 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
622 dma_sconfig.dst_maxburst = 0;
623 }
624
625 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
626 if (ret)
627 goto scrub;
628 if (dma_to_memory) {
629 tspi->rx_dma_chan = dma_chan;
630 tspi->rx_dma_buf = dma_buf;
631 tspi->rx_dma_phys = dma_phys;
632 } else {
633 tspi->tx_dma_chan = dma_chan;
634 tspi->tx_dma_buf = dma_buf;
635 tspi->tx_dma_phys = dma_phys;
636 }
637 return 0;
638
639scrub:
640 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
641 dma_release_channel(dma_chan);
642 return ret;
643}
644
645static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
646 bool dma_to_memory)
647{
648 u32 *dma_buf;
649 dma_addr_t dma_phys;
650 struct dma_chan *dma_chan;
651
652 if (dma_to_memory) {
653 dma_buf = tspi->rx_dma_buf;
654 dma_chan = tspi->rx_dma_chan;
655 dma_phys = tspi->rx_dma_phys;
656 tspi->rx_dma_chan = NULL;
657 tspi->rx_dma_buf = NULL;
658 } else {
659 dma_buf = tspi->tx_dma_buf;
660 dma_chan = tspi->tx_dma_chan;
661 dma_phys = tspi->tx_dma_phys;
662 tspi->tx_dma_buf = NULL;
663 tspi->tx_dma_chan = NULL;
664 }
665 if (!dma_chan)
666 return;
667
668 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
669 dma_release_channel(dma_chan);
670}
671
672static int tegra_slink_start_transfer_one(struct spi_device *spi,
f178e3de 673 struct spi_transfer *t)
dc4dc360
LD		 674{
675 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
676 u32 speed;
677 u8 bits_per_word;
678 unsigned total_fifo_words;
679 int ret;
5fd38677
MN		 680 u32 command;
681 u32 command2;
dc4dc360 682
e6811d1d 683 bits_per_word = t->bits_per_word;
beb96c2a 684 speed = t->speed_hz;
dc4dc360
LD		 685 if (speed != tspi->cur_speed) {
686 clk_set_rate(tspi->clk, speed * 4);
687 tspi->cur_speed = speed;
688 }
689
690 tspi->cur_spi = spi;
691 tspi->cur_pos = 0;
692 tspi->cur_rx_pos = 0;
693 tspi->cur_tx_pos = 0;
694 tspi->curr_xfer = t;
695 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
696
f178e3de
MB		 697 command = tspi->command_reg;
698 command &= ~SLINK_BIT_LENGTH(~0);
699 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
dc4dc360 700
f178e3de
MB		 701 command2 = tspi->command2_reg;
702 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
dc4dc360 703
dc4dc360
LD		 704 tspi->cur_direction = 0;
705 if (t->rx_buf) {
706 command2 |= SLINK_RXEN;
707 tspi->cur_direction |= DATA_DIR_RX;
708 }
709 if (t->tx_buf) {
710 command2 |= SLINK_TXEN;
711 tspi->cur_direction |= DATA_DIR_TX;
712 }
0e694df3
RM		 713
714 /*
715 * Writing to the command2 register bevore the command register prevents
716 * a spike in chip_select line 0. This selects the chip_select line
717 * before changing the chip_select value.
718 */
dc4dc360
LD		 719 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
720 tspi->command2_reg = command2;
721
0e694df3
RM		 722 tegra_slink_writel(tspi, command, SLINK_COMMAND);
723 tspi->command_reg = command;
724
dc4dc360
LD		 725 if (total_fifo_words > SLINK_FIFO_DEPTH)
726 ret = tegra_slink_start_dma_based_transfer(tspi, t);
727 else
728 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
729 return ret;
730}
731
732static int tegra_slink_setup(struct spi_device *spi)
733{
5fd38677 734 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
dc4dc360
LD		 735 SLINK_CS_POLARITY,
736 SLINK_CS_POLARITY1,
737 SLINK_CS_POLARITY2,
738 SLINK_CS_POLARITY3,
739 };
740
5fd38677
MN		 741 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
742 u32 val;
743 unsigned long flags;
744 int ret;
745
dc4dc360
LD		 746 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
747 spi->bits_per_word,
748 spi->mode & SPI_CPOL ? "" : "~",
749 spi->mode & SPI_CPHA ? "" : "~",
750 spi->max_speed_hz);
751
dc4dc360
LD		 752 ret = pm_runtime_get_sync(tspi->dev);
753 if (ret < 0) {
754 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
755 return ret;
756 }
757
758 spin_lock_irqsave(&tspi->lock, flags);
759 val = tspi->def_command_reg;
760 if (spi->mode & SPI_CS_HIGH)
761 val |= cs_pol_bit[spi->chip_select];
762 else
763 val &= ~cs_pol_bit[spi->chip_select];
764 tspi->def_command_reg = val;
765 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
766 spin_unlock_irqrestore(&tspi->lock, flags);
767
768 pm_runtime_put(tspi->dev);
769 return 0;
770}
771
63fc184c
MB		 772static int tegra_slink_prepare_message(struct spi_master *master,
773 struct spi_message *msg)
dc4dc360 774{
dc4dc360 775 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
dc4dc360 776 struct spi_device *spi = msg->spi;
dc4dc360 777
f178e3de 778 tegra_slink_clear_status(tspi);
d558c473 779
f178e3de
MB		 780 tspi->command_reg = tspi->def_command_reg;
781 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
dc4dc360 782
f178e3de
MB		 783 tspi->command2_reg = tspi->def_command2_reg;
784 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
785
786 tspi->command_reg &= ~SLINK_MODES;
787 if (spi->mode & SPI_CPHA)
788 tspi->command_reg |= SLINK_CK_SDA;
789
790 if (spi->mode & SPI_CPOL)
791 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
792 else
793 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
d558c473 794
63fc184c
MB		 795 return 0;
796}
dc4dc360 797
63fc184c
MB		 798static int tegra_slink_transfer_one(struct spi_master *master,
799 struct spi_device *spi,
800 struct spi_transfer *xfer)
801{
802 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
803 int ret;
804
16735d02 805 reinit_completion(&tspi->xfer_completion);
f178e3de 806 ret = tegra_slink_start_transfer_one(spi, xfer);
63fc184c
MB		 807 if (ret < 0) {
808 dev_err(tspi->dev,
809 "spi can not start transfer, err %d\n", ret);
810 return ret;
dc4dc360 811 }
f178e3de 812
63fc184c
MB		 813 ret = wait_for_completion_timeout(&tspi->xfer_completion,
814 SLINK_DMA_TIMEOUT);
815 if (WARN_ON(ret == 0)) {
816 dev_err(tspi->dev,
bfca7618 817 "spi transfer timeout, err %d\n", ret);
63fc184c
MB		 818 return -EIO;
819 }
820
821 if (tspi->tx_status)
822 return tspi->tx_status;
823 if (tspi->rx_status)
824 return tspi->rx_status;
825
826 return 0;
827}
828
829static int tegra_slink_unprepare_message(struct spi_master *master,
830 struct spi_message *msg)
831{
832 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
833
dc4dc360
LD		 834 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
835 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
63fc184c
MB		 836
837 return 0;
dc4dc360
LD		 838}
839
840static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
841{
842 struct spi_transfer *t = tspi->curr_xfer;
843 unsigned long flags;
844
845 spin_lock_irqsave(&tspi->lock, flags);
846 if (tspi->tx_status || tspi->rx_status ||
847 (tspi->status_reg & SLINK_BSY)) {
848 dev_err(tspi->dev,
849 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
850 dev_err(tspi->dev,
851 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
852 tspi->command2_reg, tspi->dma_control_reg);
ff2251e3 853 reset_control_assert(tspi->rst);
dc4dc360 854 udelay(2);
ff2251e3 855 reset_control_deassert(tspi->rst);
dc4dc360
LD		 856 complete(&tspi->xfer_completion);
857 goto exit;
858 }
859
860 if (tspi->cur_direction & DATA_DIR_RX)
861 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
862
863 if (tspi->cur_direction & DATA_DIR_TX)
864 tspi->cur_pos = tspi->cur_tx_pos;
865 else
866 tspi->cur_pos = tspi->cur_rx_pos;
867
868 if (tspi->cur_pos == t->len) {
869 complete(&tspi->xfer_completion);
870 goto exit;
871 }
872
873 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
874 tegra_slink_start_cpu_based_transfer(tspi, t);
875exit:
876 spin_unlock_irqrestore(&tspi->lock, flags);
877 return IRQ_HANDLED;
878}
879
880static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
881{
882 struct spi_transfer *t = tspi->curr_xfer;
883 long wait_status;
884 int err = 0;
885 unsigned total_fifo_words;
886 unsigned long flags;
887
888 /* Abort dmas if any error */
889 if (tspi->cur_direction & DATA_DIR_TX) {
890 if (tspi->tx_status) {
891 dmaengine_terminate_all(tspi->tx_dma_chan);
892 err += 1;
893 } else {
894 wait_status = wait_for_completion_interruptible_timeout(
895 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
896 if (wait_status <= 0) {
897 dmaengine_terminate_all(tspi->tx_dma_chan);
898 dev_err(tspi->dev, "TxDma Xfer failed\n");
899 err += 1;
900 }
901 }
902 }
903
904 if (tspi->cur_direction & DATA_DIR_RX) {
905 if (tspi->rx_status) {
906 dmaengine_terminate_all(tspi->rx_dma_chan);
907 err += 2;
908 } else {
909 wait_status = wait_for_completion_interruptible_timeout(
910 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
911 if (wait_status <= 0) {
912 dmaengine_terminate_all(tspi->rx_dma_chan);
913 dev_err(tspi->dev, "RxDma Xfer failed\n");
914 err += 2;
915 }
916 }
917 }
918
919 spin_lock_irqsave(&tspi->lock, flags);
920 if (err) {
921 dev_err(tspi->dev,
922 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
923 dev_err(tspi->dev,
924 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
925 tspi->command2_reg, tspi->dma_control_reg);
ff2251e3 926 reset_control_assert(tspi->rst);
dc4dc360 927 udelay(2);
ff2251e3 928 reset_control_assert(tspi->rst);
dc4dc360
LD		 929 complete(&tspi->xfer_completion);
930 spin_unlock_irqrestore(&tspi->lock, flags);
931 return IRQ_HANDLED;
932 }
933
934 if (tspi->cur_direction & DATA_DIR_RX)
935 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
936
937 if (tspi->cur_direction & DATA_DIR_TX)
938 tspi->cur_pos = tspi->cur_tx_pos;
939 else
940 tspi->cur_pos = tspi->cur_rx_pos;
941
942 if (tspi->cur_pos == t->len) {
943 complete(&tspi->xfer_completion);
944 goto exit;
945 }
946
947 /* Continue transfer in current message */
948 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
949 tspi, t);
950 if (total_fifo_words > SLINK_FIFO_DEPTH)
951 err = tegra_slink_start_dma_based_transfer(tspi, t);
952 else
953 err = tegra_slink_start_cpu_based_transfer(tspi, t);
954
955exit:
956 spin_unlock_irqrestore(&tspi->lock, flags);
957 return IRQ_HANDLED;
958}
959
960static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
961{
962 struct tegra_slink_data *tspi = context_data;
963
964 if (!tspi->is_curr_dma_xfer)
965 return handle_cpu_based_xfer(tspi);
966 return handle_dma_based_xfer(tspi);
967}
968
969static irqreturn_t tegra_slink_isr(int irq, void *context_data)
970{
971 struct tegra_slink_data *tspi = context_data;
972
973 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
974 if (tspi->cur_direction & DATA_DIR_TX)
975 tspi->tx_status = tspi->status_reg &
976 (SLINK_TX_OVF | SLINK_TX_UNF);
977
978 if (tspi->cur_direction & DATA_DIR_RX)
979 tspi->rx_status = tspi->status_reg &
980 (SLINK_RX_OVF | SLINK_RX_UNF);
981 tegra_slink_clear_status(tspi);
982
983 return IRQ_WAKE_THREAD;
984}
985
8b0bebe2 986static const struct tegra_slink_chip_data tegra30_spi_cdata = {
dc4dc360
LD		 987 .cs_hold_time = true,
988};
989
8b0bebe2 990static const struct tegra_slink_chip_data tegra20_spi_cdata = {
dc4dc360
LD		 991 .cs_hold_time = false,
992};
993
b2fb1872 994static const struct of_device_id tegra_slink_of_match[] = {
dc4dc360 995 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
24bc8971 996 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
dc4dc360
LD		 997 {}
998};
999MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1000
fd4a319b 1001static int tegra_slink_probe(struct platform_device *pdev)
dc4dc360
LD		 1002{
1003 struct spi_master *master;
1004 struct tegra_slink_data *tspi;
1005 struct resource *r;
dc4dc360
LD		 1006 int ret, spi_irq;
1007 const struct tegra_slink_chip_data *cdata = NULL;
1008 const struct of_device_id *match;
1009
c60fea02 1010 match = of_match_device(tegra_slink_of_match, &pdev->dev);
dc4dc360
LD		 1011 if (!match) {
1012 dev_err(&pdev->dev, "Error: No device match found\n");
1013 return -ENODEV;
1014 }
1015 cdata = match->data;
dc4dc360
LD		 1016
1017 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1018 if (!master) {
1019 dev_err(&pdev->dev, "master allocation failed\n");
1020 return -ENOMEM;
1021 }
1022
1023 /* the spi->mode bits understood by this driver: */
1024 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1025 master->setup = tegra_slink_setup;
63fc184c
MB		 1026 master->prepare_message = tegra_slink_prepare_message;
1027 master->transfer_one = tegra_slink_transfer_one;
1028 master->unprepare_message = tegra_slink_unprepare_message;
ce74ac80 1029 master->auto_runtime_pm = true;
dc4dc360 1030 master->num_chipselect = MAX_CHIP_SELECT;
dc4dc360 1031
24b5a82c 1032 platform_set_drvdata(pdev, master);
dc4dc360
LD		 1033 tspi = spi_master_get_devdata(master);
1034 tspi->master = master;
dc4dc360
LD		 1035 tspi->dev = &pdev->dev;
1036 tspi->chip_data = cdata;
1037 spin_lock_init(&tspi->lock);
1038
3c604de4
AL		 1039 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1040 &master->max_speed_hz))
1041 master->max_speed_hz = 25000000; /* 25MHz */
c60fea02 1042
dc4dc360
LD		 1043 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044 if (!r) {
1045 dev_err(&pdev->dev, "No IO memory resource\n");
1046 ret = -ENODEV;
1047 goto exit_free_master;
1048 }
1049 tspi->phys = r->start;
b0ee5605
TR		 1050 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1051 if (IS_ERR(tspi->base)) {
1052 ret = PTR_ERR(tspi->base);
dc4dc360
LD		 1053 goto exit_free_master;
1054 }
1055
7001cab1
MZ		 1056 /* disabled clock may cause interrupt storm upon request */
1057 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1058 if (IS_ERR(tspi->clk)) {
1059 ret = PTR_ERR(tspi->clk);
1060 dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1061 goto exit_free_master;
1062 }
1063 ret = clk_prepare(tspi->clk);
1064 if (ret < 0) {
1065 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
1066 goto exit_free_master;
1067 }
1068 ret = clk_enable(tspi->clk);
1069 if (ret < 0) {
1070 dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
04358e40 1071 goto exit_clk_unprepare;
7001cab1
MZ		 1072 }
1073
dc4dc360
LD		 1074 spi_irq = platform_get_irq(pdev, 0);
1075 tspi->irq = spi_irq;
1076 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1077 tegra_slink_isr_thread, IRQF_ONESHOT,
1078 dev_name(&pdev->dev), tspi);
1079 if (ret < 0) {
1080 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1081 tspi->irq);
7001cab1 1082 goto exit_clk_disable;
dc4dc360
LD		 1083 }
1084
73b32756 1085 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
ff2251e3
SW		 1086 if (IS_ERR(tspi->rst)) {
1087 dev_err(&pdev->dev, "can not get reset\n");
1088 ret = PTR_ERR(tspi->rst);
1089 goto exit_free_irq;
1090 }
1091
dc4dc360
LD		 1092 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1093 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
dc4dc360 1094
a915d150
SW		 1095 ret = tegra_slink_init_dma_param(tspi, true);
1096 if (ret < 0)
1097 goto exit_free_irq;
1098 ret = tegra_slink_init_dma_param(tspi, false);
1099 if (ret < 0)
1100 goto exit_rx_dma_free;
1101 tspi->max_buf_size = tspi->dma_buf_size;
1102 init_completion(&tspi->tx_dma_complete);
1103 init_completion(&tspi->rx_dma_complete);
dc4dc360
LD		 1104
1105 init_completion(&tspi->xfer_completion);
1106
1107 pm_runtime_enable(&pdev->dev);
1108 if (!pm_runtime_enabled(&pdev->dev)) {
1109 ret = tegra_slink_runtime_resume(&pdev->dev);
1110 if (ret)
1111 goto exit_pm_disable;
1112 }
1113
1114 ret = pm_runtime_get_sync(&pdev->dev);
1115 if (ret < 0) {
1116 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
faedcc17 1117 pm_runtime_put_noidle(&pdev->dev);
dc4dc360
LD		 1118 goto exit_pm_disable;
1119 }
1120 tspi->def_command_reg = SLINK_M_S;
1121 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1122 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1123 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1124 pm_runtime_put(&pdev->dev);
1125
1126 master->dev.of_node = pdev->dev.of_node;
716db5d6 1127 ret = devm_spi_register_master(&pdev->dev, master);
dc4dc360
LD		 1128 if (ret < 0) {
1129 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1130 goto exit_pm_disable;
1131 }
1132 return ret;
1133
1134exit_pm_disable:
1135 pm_runtime_disable(&pdev->dev);
1136 if (!pm_runtime_status_suspended(&pdev->dev))
1137 tegra_slink_runtime_suspend(&pdev->dev);
1138 tegra_slink_deinit_dma_param(tspi, false);
1139exit_rx_dma_free:
1140 tegra_slink_deinit_dma_param(tspi, true);
1141exit_free_irq:
1142 free_irq(spi_irq, tspi);
7001cab1
MZ		 1143exit_clk_disable:
1144 clk_disable(tspi->clk);
04358e40
CY		 1145exit_clk_unprepare:
1146 clk_unprepare(tspi->clk);
dc4dc360
LD		 1147exit_free_master:
1148 spi_master_put(master);
1149 return ret;
1150}
1151
fd4a319b 1152static int tegra_slink_remove(struct platform_device *pdev)
dc4dc360 1153{
24b5a82c 1154 struct spi_master *master = platform_get_drvdata(pdev);
dc4dc360
LD		 1155 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1156
1157 free_irq(tspi->irq, tspi);
dc4dc360 1158
7001cab1 1159 clk_disable(tspi->clk);
04358e40 1160 clk_unprepare(tspi->clk);
7001cab1 1161
dc4dc360
LD		 1162 if (tspi->tx_dma_chan)
1163 tegra_slink_deinit_dma_param(tspi, false);
1164
1165 if (tspi->rx_dma_chan)
1166 tegra_slink_deinit_dma_param(tspi, true);
1167
1168 pm_runtime_disable(&pdev->dev);
1169 if (!pm_runtime_status_suspended(&pdev->dev))
1170 tegra_slink_runtime_suspend(&pdev->dev);
1171
1172 return 0;
1173}
1174
1175#ifdef CONFIG_PM_SLEEP
1176static int tegra_slink_suspend(struct device *dev)
1177{
1178 struct spi_master *master = dev_get_drvdata(dev);
1179
1180 return spi_master_suspend(master);
1181}
1182
1183static int tegra_slink_resume(struct device *dev)
1184{
1185 struct spi_master *master = dev_get_drvdata(dev);
1186 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1187 int ret;
1188
1189 ret = pm_runtime_get_sync(dev);
1190 if (ret < 0) {
1191 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1192 return ret;
1193 }
1194 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1195 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1196 pm_runtime_put(dev);
1197
1198 return spi_master_resume(master);
1199}
1200#endif
1201
1202static int tegra_slink_runtime_suspend(struct device *dev)
1203{
1204 struct spi_master *master = dev_get_drvdata(dev);
1205 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1206
1207 /* Flush all write which are in PPSB queue by reading back */
1208 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1209
1210 clk_disable_unprepare(tspi->clk);
1211 return 0;
1212}
1213
1214static int tegra_slink_runtime_resume(struct device *dev)
1215{
1216 struct spi_master *master = dev_get_drvdata(dev);
1217 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1218 int ret;
1219
1220 ret = clk_prepare_enable(tspi->clk);
1221 if (ret < 0) {
1222 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1223 return ret;
1224 }
1225 return 0;
1226}
1227
1228static const struct dev_pm_ops slink_pm_ops = {
1229 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1230 tegra_slink_runtime_resume, NULL)
1231 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1232};
1233static struct platform_driver tegra_slink_driver = {
1234 .driver = {
1235 .name = "spi-tegra-slink",
dc4dc360 1236 .pm = &slink_pm_ops,
c60fea02 1237 .of_match_table = tegra_slink_of_match,
dc4dc360
LD		 1238 },
1239 .probe = tegra_slink_probe,
fd4a319b 1240 .remove = tegra_slink_remove,
dc4dc360
LD		 1241};
1242module_platform_driver(tegra_slink_driver);
1243
1244MODULE_ALIAS("platform:spi-tegra-slink");
1245MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1246MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1247MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)