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spi: tegra114: flush fifos
[linux-block.git] / drivers / spi / spi-tegra114.c
CommitLineData
f333a331
LD		 1/*
2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
f333a331
LD		 20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h>
25#include <linux/err.h>
f333a331
LD		 26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
ff2251e3 35#include <linux/reset.h>
f333a331
LD		 36#include <linux/spi/spi.h>
37
38#define SPI_COMMAND1 0x000
39#define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40#define SPI_PACKED (1 << 5)
41#define SPI_TX_EN (1 << 11)
42#define SPI_RX_EN (1 << 12)
43#define SPI_BOTH_EN_BYTE (1 << 13)
44#define SPI_BOTH_EN_BIT (1 << 14)
45#define SPI_LSBYTE_FE (1 << 15)
46#define SPI_LSBIT_FE (1 << 16)
47#define SPI_BIDIROE (1 << 17)
48#define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49#define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50#define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51#define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52#define SPI_IDLE_SDA_MASK (3 << 18)
979a9afe 53#define SPI_CS_SW_VAL (1 << 20)
f333a331
LD		 54#define SPI_CS_SW_HW (1 << 21)
55/* SPI_CS_POL_INACTIVE bits are default high */
48c3fc93
MN		 56 /* n from 0 to 3 */
57#define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
f333a331
LD		 58#define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
59
60#define SPI_CS_SEL_0 (0 << 26)
61#define SPI_CS_SEL_1 (1 << 26)
62#define SPI_CS_SEL_2 (2 << 26)
63#define SPI_CS_SEL_3 (3 << 26)
64#define SPI_CS_SEL_MASK (3 << 26)
65#define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66#define SPI_CONTROL_MODE_0 (0 << 28)
67#define SPI_CONTROL_MODE_1 (1 << 28)
68#define SPI_CONTROL_MODE_2 (2 << 28)
69#define SPI_CONTROL_MODE_3 (3 << 28)
70#define SPI_CONTROL_MODE_MASK (3 << 28)
71#define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72#define SPI_M_S (1 << 30)
73#define SPI_PIO (1 << 31)
74
75#define SPI_COMMAND2 0x004
76#define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77#define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
78
79#define SPI_CS_TIMING1 0x008
80#define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81#define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85#define SPI_CS_TIMING2 0x00C
86#define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87#define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88#define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89#define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90#define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91#define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92#define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93#define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94#define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97#define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
100
101#define SPI_TRANS_STATUS 0x010
102#define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103#define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104#define SPI_RDY (1 << 30)
105
106#define SPI_FIFO_STATUS 0x014
107#define SPI_RX_FIFO_EMPTY (1 << 0)
108#define SPI_RX_FIFO_FULL (1 << 1)
109#define SPI_TX_FIFO_EMPTY (1 << 2)
110#define SPI_TX_FIFO_FULL (1 << 3)
111#define SPI_RX_FIFO_UNF (1 << 4)
112#define SPI_RX_FIFO_OVF (1 << 5)
113#define SPI_TX_FIFO_UNF (1 << 6)
114#define SPI_TX_FIFO_OVF (1 << 7)
115#define SPI_ERR (1 << 8)
116#define SPI_TX_FIFO_FLUSH (1 << 14)
117#define SPI_RX_FIFO_FLUSH (1 << 15)
118#define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119#define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120#define SPI_FRAME_END (1 << 30)
121#define SPI_CS_INACTIVE (1 << 31)
122
123#define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125#define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127#define SPI_TX_DATA 0x018
128#define SPI_RX_DATA 0x01C
129
130#define SPI_DMA_CTL 0x020
131#define SPI_TX_TRIG_1 (0 << 15)
132#define SPI_TX_TRIG_4 (1 << 15)
133#define SPI_TX_TRIG_8 (2 << 15)
134#define SPI_TX_TRIG_16 (3 << 15)
135#define SPI_TX_TRIG_MASK (3 << 15)
136#define SPI_RX_TRIG_1 (0 << 19)
137#define SPI_RX_TRIG_4 (1 << 19)
138#define SPI_RX_TRIG_8 (2 << 19)
139#define SPI_RX_TRIG_16 (3 << 19)
140#define SPI_RX_TRIG_MASK (3 << 19)
141#define SPI_IE_TX (1 << 28)
142#define SPI_IE_RX (1 << 29)
143#define SPI_CONT (1 << 30)
144#define SPI_DMA (1 << 31)
145#define SPI_DMA_EN SPI_DMA
146
147#define SPI_DMA_BLK 0x024
148#define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
149
150#define SPI_TX_FIFO 0x108
151#define SPI_RX_FIFO 0x188
152#define MAX_CHIP_SELECT 4
153#define SPI_FIFO_DEPTH 64
154#define DATA_DIR_TX (1 << 0)
155#define DATA_DIR_RX (1 << 1)
156
157#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159#define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160#define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161#define MAX_HOLD_CYCLES 16
162#define SPI_DEFAULT_SPEED 25000000
163
f333a331
LD		 164struct tegra_spi_data {
165 struct device *dev;
166 struct spi_master *master;
167 spinlock_t lock;
168
169 struct clk *clk;
ff2251e3 170 struct reset_control *rst;
f333a331
LD		 171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
f333a331
LD		 174 u32 cur_speed;
175
176 struct spi_device *cur_spi;
f4fade12 177 struct spi_device *cs_control;
f333a331 178 unsigned cur_pos;
f333a331
LD		 179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
183
184 unsigned cur_rx_pos;
185 unsigned cur_tx_pos;
186
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
190
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
193
194 u32 tx_status;
195 u32 rx_status;
196 u32 status_reg;
197 bool is_packed;
f333a331
LD		 198
199 u32 command1_reg;
200 u32 dma_control_reg;
201 u32 def_command1_reg;
f333a331
LD		 202
203 struct completion xfer_completion;
204 struct spi_transfer *curr_xfer;
205 struct dma_chan *rx_dma_chan;
206 u32 *rx_dma_buf;
207 dma_addr_t rx_dma_phys;
208 struct dma_async_tx_descriptor *rx_dma_desc;
209
210 struct dma_chan *tx_dma_chan;
211 u32 *tx_dma_buf;
212 dma_addr_t tx_dma_phys;
213 struct dma_async_tx_descriptor *tx_dma_desc;
214};
215
216static int tegra_spi_runtime_suspend(struct device *dev);
217static int tegra_spi_runtime_resume(struct device *dev);
218
48c3fc93 219static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
f333a331
LD		 220 unsigned long reg)
221{
222 return readl(tspi->base + reg);
223}
224
225static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
48c3fc93 226 u32 val, unsigned long reg)
f333a331
LD		 227{
228 writel(val, tspi->base + reg);
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != SPI_TX_FIFO)
232 readl(tspi->base + SPI_COMMAND1);
233}
234
235static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
236{
48c3fc93 237 u32 val;
f333a331
LD		 238
239 /* Write 1 to clear status register */
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
242
243 /* Clear fifo status error if any */
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
245 if (val & SPI_ERR)
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
247 SPI_FIFO_STATUS);
248}
249
250static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device *spi, struct tegra_spi_data *tspi,
252 struct spi_transfer *t)
253{
254 unsigned remain_len = t->len - tspi->cur_pos;
255 unsigned max_word;
256 unsigned bits_per_word = t->bits_per_word;
257 unsigned max_len;
258 unsigned total_fifo_words;
259
e91d2352 260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
f333a331
LD		 261
262 if (bits_per_word == 8 || bits_per_word == 16) {
263 tspi->is_packed = 1;
264 tspi->words_per_32bit = 32/bits_per_word;
265 } else {
266 tspi->is_packed = 0;
267 tspi->words_per_32bit = 1;
268 }
269
270 if (tspi->is_packed) {
271 max_len = min(remain_len, tspi->max_buf_size);
272 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
273 total_fifo_words = (max_len + 3) / 4;
274 } else {
275 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
276 max_word = min(max_word, tspi->max_buf_size/4);
277 tspi->curr_dma_words = max_word;
278 total_fifo_words = max_word;
279 }
280 return total_fifo_words;
281}
282
283static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data *tspi, struct spi_transfer *t)
285{
286 unsigned nbytes;
287 unsigned tx_empty_count;
48c3fc93 288 u32 fifo_status;
f333a331
LD		 289 unsigned max_n_32bit;
290 unsigned i, count;
f333a331
LD		 291 unsigned int written_words;
292 unsigned fifo_words_left;
293 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
294
295 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
296 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
297
298 if (tspi->is_packed) {
299 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
300 written_words = min(fifo_words_left, tspi->curr_dma_words);
301 nbytes = written_words * tspi->bytes_per_word;
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) {
48c3fc93 304 u32 x = 0;
c19c8e75 305
f333a331 306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
48c3fc93 307 x |= (u32)(*tx_buf++) << (i * 8);
f333a331
LD		 308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
309 }
1a89ac5b
SK		 310
311 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
f333a331 312 } else {
1a89ac5b 313 unsigned int write_bytes;
f333a331
LD		 314 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
315 written_words = max_n_32bit;
316 nbytes = written_words * tspi->bytes_per_word;
1a89ac5b
SK		 317 if (nbytes > t->len - tspi->cur_pos)
318 nbytes = t->len - tspi->cur_pos;
319 write_bytes = nbytes;
f333a331 320 for (count = 0; count < max_n_32bit; count++) {
48c3fc93 321 u32 x = 0;
c19c8e75 322
f333a331
LD		 323 for (i = 0; nbytes && (i < tspi->bytes_per_word);
324 i++, nbytes--)
48c3fc93 325 x |= (u32)(*tx_buf++) << (i * 8);
f333a331
LD		 326 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
327 }
1a89ac5b
SK		 328
329 tspi->cur_tx_pos += write_bytes;
f333a331 330 }
1a89ac5b 331
f333a331
LD		 332 return written_words;
333}
334
335static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
336 struct tegra_spi_data *tspi, struct spi_transfer *t)
337{
338 unsigned rx_full_count;
48c3fc93 339 u32 fifo_status;
f333a331 340 unsigned i, count;
f333a331
LD		 341 unsigned int read_words = 0;
342 unsigned len;
343 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
344
345 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
346 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
347 if (tspi->is_packed) {
348 len = tspi->curr_dma_words * tspi->bytes_per_word;
349 for (count = 0; count < rx_full_count; count++) {
48c3fc93 350 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
c19c8e75 351
f333a331
LD		 352 for (i = 0; len && (i < 4); i++, len--)
353 *rx_buf++ = (x >> i*8) & 0xFF;
354 }
f333a331 355 read_words += tspi->curr_dma_words;
1a89ac5b 356 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
f333a331 357 } else {
48c3fc93 358 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
1a89ac5b
SK		 359 u8 bytes_per_word = tspi->bytes_per_word;
360 unsigned int read_bytes;
c19c8e75 361
1a89ac5b
SK		 362 len = rx_full_count * bytes_per_word;
363 if (len > t->len - tspi->cur_pos)
364 len = t->len - tspi->cur_pos;
365 read_bytes = len;
f333a331 366 for (count = 0; count < rx_full_count; count++) {
48c3fc93 367 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
c19c8e75 368
1a89ac5b 369 for (i = 0; len && (i < bytes_per_word); i++, len--)
f333a331
LD		 370 *rx_buf++ = (x >> (i*8)) & 0xFF;
371 }
f333a331 372 read_words += rx_full_count;
1a89ac5b 373 tspi->cur_rx_pos += read_bytes;
f333a331 374 }
1a89ac5b 375
f333a331
LD		 376 return read_words;
377}
378
379static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
380 struct tegra_spi_data *tspi, struct spi_transfer *t)
381{
f333a331
LD		 382 /* Make the dma buffer to read by cpu */
383 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
384 tspi->dma_buf_size, DMA_TO_DEVICE);
385
386 if (tspi->is_packed) {
48c3fc93 387 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
c19c8e75 388
f333a331 389 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
1a89ac5b 390 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
f333a331
LD		 391 } else {
392 unsigned int i;
393 unsigned int count;
394 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
395 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
1a89ac5b 396 unsigned int write_bytes;
f333a331 397
1a89ac5b
SK		 398 if (consume > t->len - tspi->cur_pos)
399 consume = t->len - tspi->cur_pos;
400 write_bytes = consume;
f333a331 401 for (count = 0; count < tspi->curr_dma_words; count++) {
48c3fc93 402 u32 x = 0;
c19c8e75 403
f333a331
LD		 404 for (i = 0; consume && (i < tspi->bytes_per_word);
405 i++, consume--)
48c3fc93 406 x |= (u32)(*tx_buf++) << (i * 8);
f333a331
LD		 407 tspi->tx_dma_buf[count] = x;
408 }
1a89ac5b
SK		 409
410 tspi->cur_tx_pos += write_bytes;
f333a331 411 }
f333a331
LD		 412
413 /* Make the dma buffer to read by dma */
414 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
415 tspi->dma_buf_size, DMA_TO_DEVICE);
416}
417
418static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
419 struct tegra_spi_data *tspi, struct spi_transfer *t)
420{
f333a331
LD		 421 /* Make the dma buffer to read by cpu */
422 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
424
425 if (tspi->is_packed) {
48c3fc93 426 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
c19c8e75 427
f333a331 428 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
1a89ac5b 429 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
f333a331
LD		 430 } else {
431 unsigned int i;
432 unsigned int count;
433 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
48c3fc93 434 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
1a89ac5b
SK		 435 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
436 unsigned int read_bytes;
f333a331 437
1a89ac5b
SK		 438 if (consume > t->len - tspi->cur_pos)
439 consume = t->len - tspi->cur_pos;
440 read_bytes = consume;
f333a331 441 for (count = 0; count < tspi->curr_dma_words; count++) {
48c3fc93 442 u32 x = tspi->rx_dma_buf[count] & rx_mask;
c19c8e75 443
1a89ac5b
SK		 444 for (i = 0; consume && (i < tspi->bytes_per_word);
445 i++, consume--)
f333a331
LD		 446 *rx_buf++ = (x >> (i*8)) & 0xFF;
447 }
1a89ac5b
SK		 448
449 tspi->cur_rx_pos += read_bytes;
f333a331 450 }
f333a331
LD		 451
452 /* Make the dma buffer to read by dma */
453 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
454 tspi->dma_buf_size, DMA_FROM_DEVICE);
455}
456
457static void tegra_spi_dma_complete(void *args)
458{
459 struct completion *dma_complete = args;
460
461 complete(dma_complete);
462}
463
464static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
465{
16735d02 466 reinit_completion(&tspi->tx_dma_complete);
f333a331
LD		 467 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
468 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
470 if (!tspi->tx_dma_desc) {
471 dev_err(tspi->dev, "Not able to get desc for Tx\n");
472 return -EIO;
473 }
474
475 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
476 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
477
478 dmaengine_submit(tspi->tx_dma_desc);
479 dma_async_issue_pending(tspi->tx_dma_chan);
480 return 0;
481}
482
483static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
484{
16735d02 485 reinit_completion(&tspi->rx_dma_complete);
f333a331
LD		 486 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
487 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 if (!tspi->rx_dma_desc) {
490 dev_err(tspi->dev, "Not able to get desc for Rx\n");
491 return -EIO;
492 }
493
494 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
495 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
496
497 dmaengine_submit(tspi->rx_dma_desc);
498 dma_async_issue_pending(tspi->rx_dma_chan);
499 return 0;
500}
501
c4fc9e5b 502static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
f333a331 503{
c4fc9e5b 504 unsigned long timeout = jiffies + HZ;
48c3fc93 505 u32 status;
f333a331 506
f333a331
LD		 507 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
508 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
c4fc9e5b
SK		 509 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
510 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
511 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
512 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
513 if (time_after(jiffies, timeout)) {
514 dev_err(tspi->dev,
515 "timeout waiting for fifo flush\n");
516 return -EIO;
517 }
518
519 udelay(1);
520 }
f333a331
LD		 521 }
522
c4fc9e5b
SK		 523 return 0;
524}
525
526static int tegra_spi_start_dma_based_transfer(
527 struct tegra_spi_data *tspi, struct spi_transfer *t)
528{
529 u32 val;
530 unsigned int len;
531 int ret = 0;
532
f333a331
LD		 533 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
534 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
535
536 if (tspi->is_packed)
537 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
538 4) * 4;
539 else
540 len = tspi->curr_dma_words * 4;
541
542 /* Set attention level based on length of transfer */
543 if (len & 0xF)
544 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
545 else if (((len) >> 4) & 0x1)
546 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
547 else
548 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
549
550 if (tspi->cur_direction & DATA_DIR_TX)
551 val |= SPI_IE_TX;
552
553 if (tspi->cur_direction & DATA_DIR_RX)
554 val |= SPI_IE_RX;
555
556 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
557 tspi->dma_control_reg = val;
558
559 if (tspi->cur_direction & DATA_DIR_TX) {
560 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
561 ret = tegra_spi_start_tx_dma(tspi, len);
562 if (ret < 0) {
563 dev_err(tspi->dev,
564 "Starting tx dma failed, err %d\n", ret);
565 return ret;
566 }
567 }
568
569 if (tspi->cur_direction & DATA_DIR_RX) {
570 /* Make the dma buffer to read by dma */
571 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
572 tspi->dma_buf_size, DMA_FROM_DEVICE);
573
574 ret = tegra_spi_start_rx_dma(tspi, len);
575 if (ret < 0) {
576 dev_err(tspi->dev,
577 "Starting rx dma failed, err %d\n", ret);
578 if (tspi->cur_direction & DATA_DIR_TX)
579 dmaengine_terminate_all(tspi->tx_dma_chan);
580 return ret;
581 }
582 }
583 tspi->is_curr_dma_xfer = true;
584 tspi->dma_control_reg = val;
585
586 val |= SPI_DMA_EN;
587 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
588 return ret;
589}
590
591static int tegra_spi_start_cpu_based_transfer(
592 struct tegra_spi_data *tspi, struct spi_transfer *t)
593{
48c3fc93 594 u32 val;
f333a331
LD		 595 unsigned cur_words;
596
597 if (tspi->cur_direction & DATA_DIR_TX)
598 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
599 else
600 cur_words = tspi->curr_dma_words;
601
602 val = SPI_DMA_BLK_SET(cur_words - 1);
603 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
604
605 val = 0;
606 if (tspi->cur_direction & DATA_DIR_TX)
607 val |= SPI_IE_TX;
608
609 if (tspi->cur_direction & DATA_DIR_RX)
610 val |= SPI_IE_RX;
611
612 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
613 tspi->dma_control_reg = val;
614
615 tspi->is_curr_dma_xfer = false;
616
617 val |= SPI_DMA_EN;
618 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
619 return 0;
620}
621
622static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
623 bool dma_to_memory)
624{
625 struct dma_chan *dma_chan;
626 u32 *dma_buf;
627 dma_addr_t dma_phys;
628 int ret;
629 struct dma_slave_config dma_sconfig;
f333a331 630
a915d150
SW		 631 dma_chan = dma_request_slave_channel_reason(tspi->dev,
632 dma_to_memory ? "rx" : "tx");
633 if (IS_ERR(dma_chan)) {
634 ret = PTR_ERR(dma_chan);
635 if (ret != -EPROBE_DEFER)
636 dev_err(tspi->dev,
637 "Dma channel is not available: %d\n", ret);
638 return ret;
f333a331
LD		 639 }
640
641 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
642 &dma_phys, GFP_KERNEL);
643 if (!dma_buf) {
644 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
645 dma_release_channel(dma_chan);
646 return -ENOMEM;
647 }
648
f333a331
LD		 649 if (dma_to_memory) {
650 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
651 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
652 dma_sconfig.src_maxburst = 0;
653 } else {
654 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
655 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
656 dma_sconfig.dst_maxburst = 0;
657 }
658
659 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
660 if (ret)
661 goto scrub;
662 if (dma_to_memory) {
663 tspi->rx_dma_chan = dma_chan;
664 tspi->rx_dma_buf = dma_buf;
665 tspi->rx_dma_phys = dma_phys;
666 } else {
667 tspi->tx_dma_chan = dma_chan;
668 tspi->tx_dma_buf = dma_buf;
669 tspi->tx_dma_phys = dma_phys;
670 }
671 return 0;
672
673scrub:
674 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
675 dma_release_channel(dma_chan);
676 return ret;
677}
678
679static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
680 bool dma_to_memory)
681{
682 u32 *dma_buf;
683 dma_addr_t dma_phys;
684 struct dma_chan *dma_chan;
685
686 if (dma_to_memory) {
687 dma_buf = tspi->rx_dma_buf;
688 dma_chan = tspi->rx_dma_chan;
689 dma_phys = tspi->rx_dma_phys;
690 tspi->rx_dma_chan = NULL;
691 tspi->rx_dma_buf = NULL;
692 } else {
693 dma_buf = tspi->tx_dma_buf;
694 dma_chan = tspi->tx_dma_chan;
695 dma_phys = tspi->tx_dma_phys;
696 tspi->tx_dma_buf = NULL;
697 tspi->tx_dma_chan = NULL;
698 }
699 if (!dma_chan)
700 return;
701
702 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
703 dma_release_channel(dma_chan);
704}
705
48c3fc93 706static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
f4fade12 707 struct spi_transfer *t, bool is_first_of_msg)
f333a331
LD		 708{
709 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
710 u32 speed = t->speed_hz;
711 u8 bits_per_word = t->bits_per_word;
48c3fc93 712 u32 command1;
f333a331
LD		 713 int req_mode;
714
715 if (speed != tspi->cur_speed) {
716 clk_set_rate(tspi->clk, speed);
717 tspi->cur_speed = speed;
718 }
719
720 tspi->cur_spi = spi;
721 tspi->cur_pos = 0;
722 tspi->cur_rx_pos = 0;
723 tspi->cur_tx_pos = 0;
724 tspi->curr_xfer = t;
f333a331
LD		 725
726 if (is_first_of_msg) {
727 tegra_spi_clear_status(tspi);
728
729 command1 = tspi->def_command1_reg;
730 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
731
732 command1 &= ~SPI_CONTROL_MODE_MASK;
733 req_mode = spi->mode & 0x3;
734 if (req_mode == SPI_MODE_0)
735 command1 |= SPI_CONTROL_MODE_0;
736 else if (req_mode == SPI_MODE_1)
737 command1 |= SPI_CONTROL_MODE_1;
738 else if (req_mode == SPI_MODE_2)
739 command1 |= SPI_CONTROL_MODE_2;
740 else if (req_mode == SPI_MODE_3)
741 command1 |= SPI_CONTROL_MODE_3;
742
f4fade12
RK		 743 if (tspi->cs_control) {
744 if (tspi->cs_control != spi)
745 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
746 tspi->cs_control = NULL;
747 } else
748 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
f333a331
LD		 749
750 command1 |= SPI_CS_SW_HW;
751 if (spi->mode & SPI_CS_HIGH)
979a9afe 752 command1 |= SPI_CS_SW_VAL;
f333a331 753 else
979a9afe 754 command1 &= ~SPI_CS_SW_VAL;
f333a331
LD		 755
756 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
757 } else {
758 command1 = tspi->command1_reg;
759 command1 &= ~SPI_BIT_LENGTH(~0);
760 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
761 }
762
f4fade12
RK		 763 return command1;
764}
765
766static int tegra_spi_start_transfer_one(struct spi_device *spi,
48c3fc93 767 struct spi_transfer *t, u32 command1)
f4fade12
RK		 768{
769 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
770 unsigned total_fifo_words;
771 int ret;
772
773 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
774
f333a331
LD		 775 if (tspi->is_packed)
776 command1 |= SPI_PACKED;
7b3d10cd
SK		 777 else
778 command1 &= ~SPI_PACKED;
f333a331
LD		 779
780 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
781 tspi->cur_direction = 0;
782 if (t->rx_buf) {
783 command1 |= SPI_RX_EN;
784 tspi->cur_direction |= DATA_DIR_RX;
785 }
786 if (t->tx_buf) {
787 command1 |= SPI_TX_EN;
788 tspi->cur_direction |= DATA_DIR_TX;
789 }
790 command1 |= SPI_CS_SEL(spi->chip_select);
791 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
792 tspi->command1_reg = command1;
793
48c3fc93
MN		 794 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
795 tspi->def_command1_reg, (unsigned)command1);
f333a331 796
c4fc9e5b
SK		 797 ret = tegra_spi_flush_fifos(tspi);
798 if (ret < 0)
799 return ret;
f333a331
LD		 800 if (total_fifo_words > SPI_FIFO_DEPTH)
801 ret = tegra_spi_start_dma_based_transfer(tspi, t);
802 else
803 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
804 return ret;
805}
806
807static int tegra_spi_setup(struct spi_device *spi)
808{
809 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
48c3fc93 810 u32 val;
f333a331
LD		 811 unsigned long flags;
812 int ret;
f333a331
LD		 813
814 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
815 spi->bits_per_word,
816 spi->mode & SPI_CPOL ? "" : "~",
817 spi->mode & SPI_CPHA ? "" : "~",
818 spi->max_speed_hz);
819
f333a331
LD		 820 ret = pm_runtime_get_sync(tspi->dev);
821 if (ret < 0) {
822 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
823 return ret;
824 }
825
826 spin_lock_irqsave(&tspi->lock, flags);
827 val = tspi->def_command1_reg;
828 if (spi->mode & SPI_CS_HIGH)
48c3fc93 829 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
f333a331 830 else
48c3fc93 831 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
f333a331
LD		 832 tspi->def_command1_reg = val;
833 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
834 spin_unlock_irqrestore(&tspi->lock, flags);
835
836 pm_runtime_put(tspi->dev);
837 return 0;
838}
839
f4fade12
RK		 840static void tegra_spi_transfer_delay(int delay)
841{
842 if (!delay)
843 return;
844
845 if (delay >= 1000)
846 mdelay(delay / 1000);
847
848 udelay(delay % 1000);
849}
850
f333a331
LD		 851static int tegra_spi_transfer_one_message(struct spi_master *master,
852 struct spi_message *msg)
853{
854 bool is_first_msg = true;
f333a331
LD		 855 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
856 struct spi_transfer *xfer;
857 struct spi_device *spi = msg->spi;
858 int ret;
f4fade12 859 bool skip = false;
f333a331
LD		 860
861 msg->status = 0;
862 msg->actual_length = 0;
863
f333a331 864 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
48c3fc93 865 u32 cmd1;
f4fade12 866
16735d02 867 reinit_completion(&tspi->xfer_completion);
f4fade12
RK		 868
869 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
870
871 if (!xfer->len) {
872 ret = 0;
873 skip = true;
874 goto complete_xfer;
875 }
876
877 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
f333a331
LD		 878 if (ret < 0) {
879 dev_err(tspi->dev,
880 "spi can not start transfer, err %d\n", ret);
f4fade12 881 goto complete_xfer;
f333a331 882 }
f4fade12 883
f333a331
LD		 884 is_first_msg = false;
885 ret = wait_for_completion_timeout(&tspi->xfer_completion,
886 SPI_DMA_TIMEOUT);
887 if (WARN_ON(ret == 0)) {
888 dev_err(tspi->dev,
bfca7618 889 "spi transfer timeout, err %d\n", ret);
32bd1a95
SK		 890 if (tspi->is_curr_dma_xfer &&
891 (tspi->cur_direction & DATA_DIR_TX))
892 dmaengine_terminate_all(tspi->tx_dma_chan);
893 if (tspi->is_curr_dma_xfer &&
894 (tspi->cur_direction & DATA_DIR_RX))
895 dmaengine_terminate_all(tspi->rx_dma_chan);
f333a331 896 ret = -EIO;
c4fc9e5b 897 tegra_spi_flush_fifos(tspi);
32bd1a95
SK		 898 reset_control_assert(tspi->rst);
899 udelay(2);
900 reset_control_deassert(tspi->rst);
f4fade12 901 goto complete_xfer;
f333a331
LD		 902 }
903
904 if (tspi->tx_status || tspi->rx_status) {
905 dev_err(tspi->dev, "Error in Transfer\n");
906 ret = -EIO;
f4fade12 907 goto complete_xfer;
f333a331
LD		 908 }
909 msg->actual_length += xfer->len;
f4fade12
RK		 910
911complete_xfer:
912 if (ret < 0 || skip) {
913 tegra_spi_writel(tspi, tspi->def_command1_reg,
914 SPI_COMMAND1);
915 tegra_spi_transfer_delay(xfer->delay_usecs);
916 goto exit;
971e9084
AL		 917 } else if (list_is_last(&xfer->transfer_list,
918 &msg->transfers)) {
f4fade12
RK		 919 if (xfer->cs_change)
920 tspi->cs_control = spi;
921 else {
922 tegra_spi_writel(tspi, tspi->def_command1_reg,
923 SPI_COMMAND1);
924 tegra_spi_transfer_delay(xfer->delay_usecs);
925 }
926 } else if (xfer->cs_change) {
f333a331
LD		 927 tegra_spi_writel(tspi, tspi->def_command1_reg,
928 SPI_COMMAND1);
f4fade12 929 tegra_spi_transfer_delay(xfer->delay_usecs);
f333a331 930 }
f4fade12 931
f333a331
LD		 932 }
933 ret = 0;
934exit:
f333a331
LD		 935 msg->status = ret;
936 spi_finalize_current_message(master);
937 return ret;
938}
939
940static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
941{
942 struct spi_transfer *t = tspi->curr_xfer;
943 unsigned long flags;
944
945 spin_lock_irqsave(&tspi->lock, flags);
946 if (tspi->tx_status || tspi->rx_status) {
947 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
948 tspi->status_reg);
949 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
950 tspi->command1_reg, tspi->dma_control_reg);
c4fc9e5b 951 tegra_spi_flush_fifos(tspi);
ff2251e3 952 reset_control_assert(tspi->rst);
f333a331 953 udelay(2);
ff2251e3 954 reset_control_deassert(tspi->rst);
f333a331
LD		 955 complete(&tspi->xfer_completion);
956 goto exit;
957 }
958
959 if (tspi->cur_direction & DATA_DIR_RX)
960 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
961
962 if (tspi->cur_direction & DATA_DIR_TX)
963 tspi->cur_pos = tspi->cur_tx_pos;
964 else
965 tspi->cur_pos = tspi->cur_rx_pos;
966
967 if (tspi->cur_pos == t->len) {
968 complete(&tspi->xfer_completion);
969 goto exit;
970 }
971
972 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
973 tegra_spi_start_cpu_based_transfer(tspi, t);
974exit:
975 spin_unlock_irqrestore(&tspi->lock, flags);
976 return IRQ_HANDLED;
977}
978
979static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
980{
981 struct spi_transfer *t = tspi->curr_xfer;
982 long wait_status;
983 int err = 0;
984 unsigned total_fifo_words;
985 unsigned long flags;
986
987 /* Abort dmas if any error */
988 if (tspi->cur_direction & DATA_DIR_TX) {
989 if (tspi->tx_status) {
990 dmaengine_terminate_all(tspi->tx_dma_chan);
991 err += 1;
992 } else {
993 wait_status = wait_for_completion_interruptible_timeout(
994 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
995 if (wait_status <= 0) {
996 dmaengine_terminate_all(tspi->tx_dma_chan);
997 dev_err(tspi->dev, "TxDma Xfer failed\n");
998 err += 1;
999 }
1000 }
1001 }
1002
1003 if (tspi->cur_direction & DATA_DIR_RX) {
1004 if (tspi->rx_status) {
1005 dmaengine_terminate_all(tspi->rx_dma_chan);
1006 err += 2;
1007 } else {
1008 wait_status = wait_for_completion_interruptible_timeout(
1009 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1010 if (wait_status <= 0) {
1011 dmaengine_terminate_all(tspi->rx_dma_chan);
1012 dev_err(tspi->dev, "RxDma Xfer failed\n");
1013 err += 2;
1014 }
1015 }
1016 }
1017
1018 spin_lock_irqsave(&tspi->lock, flags);
1019 if (err) {
1020 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1021 tspi->status_reg);
1022 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1023 tspi->command1_reg, tspi->dma_control_reg);
c4fc9e5b 1024 tegra_spi_flush_fifos(tspi);
ff2251e3 1025 reset_control_assert(tspi->rst);
f333a331 1026 udelay(2);
ff2251e3 1027 reset_control_deassert(tspi->rst);
f333a331
LD		 1028 complete(&tspi->xfer_completion);
1029 spin_unlock_irqrestore(&tspi->lock, flags);
1030 return IRQ_HANDLED;
1031 }
1032
1033 if (tspi->cur_direction & DATA_DIR_RX)
1034 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1035
1036 if (tspi->cur_direction & DATA_DIR_TX)
1037 tspi->cur_pos = tspi->cur_tx_pos;
1038 else
1039 tspi->cur_pos = tspi->cur_rx_pos;
1040
1041 if (tspi->cur_pos == t->len) {
1042 complete(&tspi->xfer_completion);
1043 goto exit;
1044 }
1045
1046 /* Continue transfer in current message */
1047 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1048 tspi, t);
1049 if (total_fifo_words > SPI_FIFO_DEPTH)
1050 err = tegra_spi_start_dma_based_transfer(tspi, t);
1051 else
1052 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1053
1054exit:
1055 spin_unlock_irqrestore(&tspi->lock, flags);
1056 return IRQ_HANDLED;
1057}
1058
1059static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1060{
1061 struct tegra_spi_data *tspi = context_data;
1062
1063 if (!tspi->is_curr_dma_xfer)
1064 return handle_cpu_based_xfer(tspi);
1065 return handle_dma_based_xfer(tspi);
1066}
1067
1068static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1069{
1070 struct tegra_spi_data *tspi = context_data;
1071
1072 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1073 if (tspi->cur_direction & DATA_DIR_TX)
1074 tspi->tx_status = tspi->status_reg &
1075 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1076
1077 if (tspi->cur_direction & DATA_DIR_RX)
1078 tspi->rx_status = tspi->status_reg &
1079 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1080 tegra_spi_clear_status(tspi);
1081
1082 return IRQ_WAKE_THREAD;
1083}
1084
0ac83f39 1085static const struct of_device_id tegra_spi_of_match[] = {
f333a331
LD		 1086 { .compatible = "nvidia,tegra114-spi", },
1087 {}
1088};
1089MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1090
1091static int tegra_spi_probe(struct platform_device *pdev)
1092{
1093 struct spi_master *master;
1094 struct tegra_spi_data *tspi;
1095 struct resource *r;
1096 int ret, spi_irq;
1097
1098 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1099 if (!master) {
1100 dev_err(&pdev->dev, "master allocation failed\n");
1101 return -ENOMEM;
1102 }
24b5a82c 1103 platform_set_drvdata(pdev, master);
f333a331
LD		 1104 tspi = spi_master_get_devdata(master);
1105
383840d9
AL		 1106 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1107 &master->max_speed_hz))
1108 master->max_speed_hz = 25000000; /* 25MHz */
f333a331
LD		 1109
1110 /* the spi->mode bits understood by this driver: */
1111 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1112 master->setup = tegra_spi_setup;
1113 master->transfer_one_message = tegra_spi_transfer_one_message;
1114 master->num_chipselect = MAX_CHIP_SELECT;
612aa5ce 1115 master->auto_runtime_pm = true;
f333a331
LD		 1116
1117 tspi->master = master;
1118 tspi->dev = &pdev->dev;
1119 spin_lock_init(&tspi->lock);
1120
1121 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f333a331
LD		 1122 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1123 if (IS_ERR(tspi->base)) {
1124 ret = PTR_ERR(tspi->base);
f333a331
LD		 1125 goto exit_free_master;
1126 }
5f7f54b5 1127 tspi->phys = r->start;
f333a331
LD		 1128
1129 spi_irq = platform_get_irq(pdev, 0);
1130 tspi->irq = spi_irq;
1131 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1132 tegra_spi_isr_thread, IRQF_ONESHOT,
1133 dev_name(&pdev->dev), tspi);
1134 if (ret < 0) {
1135 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1136 tspi->irq);
1137 goto exit_free_master;
1138 }
1139
1140 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1141 if (IS_ERR(tspi->clk)) {
1142 dev_err(&pdev->dev, "can not get clock\n");
1143 ret = PTR_ERR(tspi->clk);
1144 goto exit_free_irq;
1145 }
1146
d006edb4 1147 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
ff2251e3
SW		 1148 if (IS_ERR(tspi->rst)) {
1149 dev_err(&pdev->dev, "can not get reset\n");
1150 ret = PTR_ERR(tspi->rst);
1151 goto exit_free_irq;
1152 }
1153
f333a331
LD		 1154 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1155 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1156
a915d150
SW		 1157 ret = tegra_spi_init_dma_param(tspi, true);
1158 if (ret < 0)
1159 goto exit_free_irq;
1160 ret = tegra_spi_init_dma_param(tspi, false);
1161 if (ret < 0)
1162 goto exit_rx_dma_free;
1163 tspi->max_buf_size = tspi->dma_buf_size;
1164 init_completion(&tspi->tx_dma_complete);
1165 init_completion(&tspi->rx_dma_complete);
f333a331
LD		 1166
1167 init_completion(&tspi->xfer_completion);
1168
1169 pm_runtime_enable(&pdev->dev);
1170 if (!pm_runtime_enabled(&pdev->dev)) {
1171 ret = tegra_spi_runtime_resume(&pdev->dev);
1172 if (ret)
1173 goto exit_pm_disable;
1174 }
1175
1176 ret = pm_runtime_get_sync(&pdev->dev);
1177 if (ret < 0) {
1178 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1179 goto exit_pm_disable;
1180 }
1181 tspi->def_command1_reg = SPI_M_S;
1182 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1183 pm_runtime_put(&pdev->dev);
1184
1185 master->dev.of_node = pdev->dev.of_node;
5c809643 1186 ret = devm_spi_register_master(&pdev->dev, master);
f333a331
LD		 1187 if (ret < 0) {
1188 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1189 goto exit_pm_disable;
1190 }
1191 return ret;
1192
1193exit_pm_disable:
1194 pm_runtime_disable(&pdev->dev);
1195 if (!pm_runtime_status_suspended(&pdev->dev))
1196 tegra_spi_runtime_suspend(&pdev->dev);
1197 tegra_spi_deinit_dma_param(tspi, false);
1198exit_rx_dma_free:
1199 tegra_spi_deinit_dma_param(tspi, true);
1200exit_free_irq:
1201 free_irq(spi_irq, tspi);
1202exit_free_master:
1203 spi_master_put(master);
1204 return ret;
1205}
1206
1207static int tegra_spi_remove(struct platform_device *pdev)
1208{
24b5a82c 1209 struct spi_master *master = platform_get_drvdata(pdev);
f333a331
LD		 1210 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1211
1212 free_irq(tspi->irq, tspi);
f333a331
LD		 1213
1214 if (tspi->tx_dma_chan)
1215 tegra_spi_deinit_dma_param(tspi, false);
1216
1217 if (tspi->rx_dma_chan)
1218 tegra_spi_deinit_dma_param(tspi, true);
1219
1220 pm_runtime_disable(&pdev->dev);
1221 if (!pm_runtime_status_suspended(&pdev->dev))
1222 tegra_spi_runtime_suspend(&pdev->dev);
1223
1224 return 0;
1225}
1226
1227#ifdef CONFIG_PM_SLEEP
1228static int tegra_spi_suspend(struct device *dev)
1229{
1230 struct spi_master *master = dev_get_drvdata(dev);
1231
1232 return spi_master_suspend(master);
1233}
1234
1235static int tegra_spi_resume(struct device *dev)
1236{
1237 struct spi_master *master = dev_get_drvdata(dev);
1238 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1239 int ret;
1240
1241 ret = pm_runtime_get_sync(dev);
1242 if (ret < 0) {
1243 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1244 return ret;
1245 }
1246 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1247 pm_runtime_put(dev);
1248
1249 return spi_master_resume(master);
1250}
1251#endif
1252
1253static int tegra_spi_runtime_suspend(struct device *dev)
1254{
1255 struct spi_master *master = dev_get_drvdata(dev);
1256 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1257
1258 /* Flush all write which are in PPSB queue by reading back */
1259 tegra_spi_readl(tspi, SPI_COMMAND1);
1260
1261 clk_disable_unprepare(tspi->clk);
1262 return 0;
1263}
1264
1265static int tegra_spi_runtime_resume(struct device *dev)
1266{
1267 struct spi_master *master = dev_get_drvdata(dev);
1268 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1269 int ret;
1270
1271 ret = clk_prepare_enable(tspi->clk);
1272 if (ret < 0) {
1273 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1274 return ret;
1275 }
1276 return 0;
1277}
1278
1279static const struct dev_pm_ops tegra_spi_pm_ops = {
1280 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1281 tegra_spi_runtime_resume, NULL)
1282 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1283};
1284static struct platform_driver tegra_spi_driver = {
1285 .driver = {
1286 .name = "spi-tegra114",
f333a331
LD		 1287 .pm = &tegra_spi_pm_ops,
1288 .of_match_table = tegra_spi_of_match,
1289 },
1290 .probe = tegra_spi_probe,
1291 .remove = tegra_spi_remove,
1292};
1293module_platform_driver(tegra_spi_driver);
1294
1295MODULE_ALIAS("platform:spi-tegra114");
1296MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1297MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1298MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)