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spi: Add spi driver for Socionext SynQuacer platform
[linux-2.6-block.git] / drivers / spi / spi-synquacer.c
CommitLineData
b0823ee3
MK		 1// SPDX-License-Identifier: GPL-2.0
2//
3// Synquacer HSSPI controller driver
4//
5// Copyright (c) 2015-2018 Socionext Inc.
6// Copyright (c) 2018-2019 Linaro Ltd.
7//
8
9#include <linux/acpi.h>
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/scatterlist.h>
18#include <linux/slab.h>
19#include <linux/spi/spi.h>
20#include <linux/spinlock.h>
21#include <linux/clk.h>
22
23/* HSSPI register address definitions */
24#define SYNQUACER_HSSPI_REG_MCTRL 0x00
25#define SYNQUACER_HSSPI_REG_PCC0 0x04
26#define SYNQUACER_HSSPI_REG_PCC(n) (SYNQUACER_HSSPI_REG_PCC0 + (n) * 4)
27#define SYNQUACER_HSSPI_REG_TXF 0x14
28#define SYNQUACER_HSSPI_REG_TXE 0x18
29#define SYNQUACER_HSSPI_REG_TXC 0x1C
30#define SYNQUACER_HSSPI_REG_RXF 0x20
31#define SYNQUACER_HSSPI_REG_RXE 0x24
32#define SYNQUACER_HSSPI_REG_RXC 0x28
33#define SYNQUACER_HSSPI_REG_FAULTF 0x2C
34#define SYNQUACER_HSSPI_REG_FAULTC 0x30
35#define SYNQUACER_HSSPI_REG_DMCFG 0x34
36#define SYNQUACER_HSSPI_REG_DMSTART 0x38
37#define SYNQUACER_HSSPI_REG_DMBCC 0x3C
38#define SYNQUACER_HSSPI_REG_DMSTATUS 0x40
39#define SYNQUACER_HSSPI_REG_FIFOCFG 0x4C
40#define SYNQUACER_HSSPI_REG_TX_FIFO 0x50
41#define SYNQUACER_HSSPI_REG_RX_FIFO 0x90
42#define SYNQUACER_HSSPI_REG_MID 0xFC
43
44/* HSSPI register bit definitions */
45#define SYNQUACER_HSSPI_MCTRL_MEN BIT(0)
46#define SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN BIT(1)
47#define SYNQUACER_HSSPI_MCTRL_CDSS BIT(3)
48#define SYNQUACER_HSSPI_MCTRL_MES BIT(4)
49#define SYNQUACER_HSSPI_MCTRL_SYNCON BIT(5)
50
51#define SYNQUACER_HSSPI_PCC_CPHA BIT(0)
52#define SYNQUACER_HSSPI_PCC_CPOL BIT(1)
53#define SYNQUACER_HSSPI_PCC_ACES BIT(2)
54#define SYNQUACER_HSSPI_PCC_RTM BIT(3)
55#define SYNQUACER_HSSPI_PCC_SSPOL BIT(4)
56#define SYNQUACER_HSSPI_PCC_SDIR BIT(7)
57#define SYNQUACER_HSSPI_PCC_SENDIAN BIT(8)
58#define SYNQUACER_HSSPI_PCC_SAFESYNC BIT(16)
59#define SYNQUACER_HSSPI_PCC_SS2CD_SHIFT 5U
60#define SYNQUACER_HSSPI_PCC_CDRS_MASK 0x7f
61#define SYNQUACER_HSSPI_PCC_CDRS_SHIFT 9U
62
63#define SYNQUACER_HSSPI_TXF_FIFO_FULL BIT(0)
64#define SYNQUACER_HSSPI_TXF_FIFO_EMPTY BIT(1)
65#define SYNQUACER_HSSPI_TXF_SLAVE_RELEASED BIT(6)
66
67#define SYNQUACER_HSSPI_TXE_FIFO_FULL BIT(0)
68#define SYNQUACER_HSSPI_TXE_FIFO_EMPTY BIT(1)
69#define SYNQUACER_HSSPI_TXE_SLAVE_RELEASED BIT(6)
70
71#define SYNQUACER_HSSPI_RXF_FIFO_MORE_THAN_THRESHOLD BIT(5)
72#define SYNQUACER_HSSPI_RXF_SLAVE_RELEASED BIT(6)
73
74#define SYNQUACER_HSSPI_RXE_FIFO_MORE_THAN_THRESHOLD BIT(5)
75#define SYNQUACER_HSSPI_RXE_SLAVE_RELEASED BIT(6)
76
77#define SYNQUACER_HSSPI_DMCFG_SSDC BIT(1)
78#define SYNQUACER_HSSPI_DMCFG_MSTARTEN BIT(2)
79
80#define SYNQUACER_HSSPI_DMSTART_START BIT(0)
81#define SYNQUACER_HSSPI_DMSTOP_STOP BIT(8)
82#define SYNQUACER_HSSPI_DMPSEL_CS_MASK 0x3
83#define SYNQUACER_HSSPI_DMPSEL_CS_SHIFT 16U
84#define SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT 24U
85#define SYNQUACER_HSSPI_DMTRP_DATA_MASK 0x3
86#define SYNQUACER_HSSPI_DMTRP_DATA_SHIFT 26U
87#define SYNQUACER_HSSPI_DMTRP_DATA_TXRX 0
88#define SYNQUACER_HSSPI_DMTRP_DATA_RX 1
89#define SYNQUACER_HSSPI_DMTRP_DATA_TX 2
90
91#define SYNQUACER_HSSPI_DMSTATUS_RX_DATA_MASK 0x1f
92#define SYNQUACER_HSSPI_DMSTATUS_RX_DATA_SHIFT 8U
93#define SYNQUACER_HSSPI_DMSTATUS_TX_DATA_MASK 0x1f
94#define SYNQUACER_HSSPI_DMSTATUS_TX_DATA_SHIFT 16U
95
96#define SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_MASK 0xf
97#define SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_SHIFT 0U
98#define SYNQUACER_HSSPI_FIFOCFG_TX_THRESHOLD_MASK 0xf
99#define SYNQUACER_HSSPI_FIFOCFG_TX_THRESHOLD_SHIFT 4U
100#define SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_MASK 0x3
101#define SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_SHIFT 8U
102#define SYNQUACER_HSSPI_FIFOCFG_RX_FLUSH BIT(11)
103#define SYNQUACER_HSSPI_FIFOCFG_TX_FLUSH BIT(12)
104
105#define SYNQUACER_HSSPI_FIFO_DEPTH 16U
106#define SYNQUACER_HSSPI_FIFO_TX_THRESHOLD 4U
107#define SYNQUACER_HSSPI_FIFO_RX_THRESHOLD \
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
109
110#define SYNQUACER_HSSPI_TRANSFER_MODE_TX BIT(1)
111#define SYNQUACER_HSSPI_TRANSFER_MODE_RX BIT(2)
112#define SYNQUACER_HSSPI_TRANSFER_TMOUT_MSEC 2000U
113#define SYNQUACER_HSSPI_ENABLE_TMOUT_MSEC 1000U
114
115#define SYNQUACER_HSSPI_CLOCK_SRC_IHCLK 0
116#define SYNQUACER_HSSPI_CLOCK_SRC_IPCLK 1
117
118#define SYNQUACER_HSSPI_NUM_CHIP_SELECT 4U
119#define SYNQUACER_HSSPI_IRQ_NAME_MAX 32U
120
121struct synquacer_spi {
122 struct device *dev;
123 struct completion transfer_done;
124 unsigned int cs;
125 unsigned int bpw;
126 unsigned int mode;
127 unsigned int speed;
128 bool aces, rtm;
129 void *rx_buf;
130 const void *tx_buf;
131 struct clk *clk;
132 int clk_src_type;
133 void __iomem *regs;
134 u32 tx_words, rx_words;
135 unsigned int bus_width;
136 unsigned int transfer_mode;
137 char rx_irq_name[SYNQUACER_HSSPI_IRQ_NAME_MAX];
138 char tx_irq_name[SYNQUACER_HSSPI_IRQ_NAME_MAX];
139};
140
141static int read_fifo(struct synquacer_spi *sspi)
142{
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
144
145 len = (len >> SYNQUACER_HSSPI_DMSTATUS_RX_DATA_SHIFT) &
146 SYNQUACER_HSSPI_DMSTATUS_RX_DATA_MASK;
147 len = min(len, sspi->rx_words);
148
149 switch (sspi->bpw) {
150 case 8: {
151 u8 *buf = sspi->rx_buf;
152
153 readsb(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, buf, len);
154 sspi->rx_buf = buf + len;
155 break;
156 }
157 case 16: {
158 u16 *buf = sspi->rx_buf;
159
160 readsw(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, buf, len);
161 sspi->rx_buf = buf + len;
162 break;
163 }
164 case 24:
165 /* fallthrough, should use 32-bits access */
166 case 32: {
167 u32 *buf = sspi->rx_buf;
168
169 readsl(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, buf, len);
170 sspi->rx_buf = buf + len;
171 break;
172 }
173 default:
174 return -EINVAL;
175 }
176
177 sspi->rx_words -= len;
178 return 0;
179}
180
181static int write_fifo(struct synquacer_spi *sspi)
182{
183 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
184
185 len = (len >> SYNQUACER_HSSPI_DMSTATUS_TX_DATA_SHIFT) &
186 SYNQUACER_HSSPI_DMSTATUS_TX_DATA_MASK;
187 len = min(SYNQUACER_HSSPI_FIFO_DEPTH - len,
188 sspi->tx_words);
189
190 switch (sspi->bpw) {
191 case 8: {
192 const u8 *buf = sspi->tx_buf;
193
194 writesb(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO, buf, len);
195 sspi->tx_buf = buf + len;
196 break;
197 }
198 case 16: {
199 const u16 *buf = sspi->tx_buf;
200
201 writesw(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO, buf, len);
202 sspi->tx_buf = buf + len;
203 break;
204 }
205 case 24:
206 /* fallthrough, should use 32-bits access */
207 case 32: {
208 const u32 *buf = sspi->tx_buf;
209
210 writesl(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO, buf, len);
211 sspi->tx_buf = buf + len;
212 break;
213 }
214 default:
215 return -EINVAL;
216 }
217
218 sspi->tx_words -= len;
219 return 0;
220}
221
222static int synquacer_spi_config(struct spi_master *master,
223 struct spi_device *spi,
224 struct spi_transfer *xfer)
225{
226 struct synquacer_spi *sspi = spi_master_get_devdata(master);
227 unsigned int speed, mode, bpw, cs, bus_width, transfer_mode;
228 u32 rate, val, div;
229
230 /* Full Duplex only on 1-bit wide bus */
231 if (xfer->rx_buf && xfer->tx_buf &&
232 (xfer->rx_nbits != 1 || xfer->tx_nbits != 1)) {
233 dev_err(sspi->dev,
234 "RX and TX bus widths must be 1-bit for Full-Duplex!\n");
235 return -EINVAL;
236 }
237
238 if (xfer->tx_buf) {
239 bus_width = xfer->tx_nbits;
240 transfer_mode = SYNQUACER_HSSPI_TRANSFER_MODE_TX;
241 } else {
242 bus_width = xfer->rx_nbits;
243 transfer_mode = SYNQUACER_HSSPI_TRANSFER_MODE_RX;
244 }
245
246 mode = spi->mode;
247 cs = spi->chip_select;
248 speed = xfer->speed_hz;
249 bpw = xfer->bits_per_word;
250
251 /* return if nothing to change */
252 if (speed == sspi->speed &&
253 bus_width == sspi->bus_width && bpw == sspi->bpw &&
254 mode == sspi->mode && cs == sspi->cs &&
255 transfer_mode == sspi->transfer_mode) {
256 return 0;
257 }
258
259 sspi->transfer_mode = transfer_mode;
260 rate = master->max_speed_hz;
261
262 div = DIV_ROUND_UP(rate, speed);
263 if (div > 254) {
264 dev_err(sspi->dev, "Requested rate too low (%u)\n",
265 sspi->speed);
266 return -EINVAL;
267 }
268
269 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs));
270 val &= ~SYNQUACER_HSSPI_PCC_SAFESYNC;
271 if (bpw == 8 && (mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3)
272 val |= SYNQUACER_HSSPI_PCC_SAFESYNC;
273 if (bpw == 8 && (mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6)
274 val |= SYNQUACER_HSSPI_PCC_SAFESYNC;
275 if (bpw == 16 && (mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 3)
276 val |= SYNQUACER_HSSPI_PCC_SAFESYNC;
277
278 if (mode & SPI_CPHA)
279 val |= SYNQUACER_HSSPI_PCC_CPHA;
280 else
281 val &= ~SYNQUACER_HSSPI_PCC_CPHA;
282
283 if (mode & SPI_CPOL)
284 val |= SYNQUACER_HSSPI_PCC_CPOL;
285 else
286 val &= ~SYNQUACER_HSSPI_PCC_CPOL;
287
288 if (mode & SPI_CS_HIGH)
289 val |= SYNQUACER_HSSPI_PCC_SSPOL;
290 else
291 val &= ~SYNQUACER_HSSPI_PCC_SSPOL;
292
293 if (mode & SPI_LSB_FIRST)
294 val |= SYNQUACER_HSSPI_PCC_SDIR;
295 else
296 val &= ~SYNQUACER_HSSPI_PCC_SDIR;
297
298 if (sspi->aces)
299 val |= SYNQUACER_HSSPI_PCC_ACES;
300 else
301 val &= ~SYNQUACER_HSSPI_PCC_ACES;
302
303 if (sspi->rtm)
304 val |= SYNQUACER_HSSPI_PCC_RTM;
305 else
306 val &= ~SYNQUACER_HSSPI_PCC_RTM;
307
308 val |= (3 << SYNQUACER_HSSPI_PCC_SS2CD_SHIFT);
309 val |= SYNQUACER_HSSPI_PCC_SENDIAN;
310
311 val &= ~(SYNQUACER_HSSPI_PCC_CDRS_MASK <<
312 SYNQUACER_HSSPI_PCC_CDRS_SHIFT);
313 val |= ((div >> 1) << SYNQUACER_HSSPI_PCC_CDRS_SHIFT);
314
315 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs));
316
317 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
318 val &= ~(SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_MASK <<
319 SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_SHIFT);
320 val |= ((bpw / 8 - 1) << SYNQUACER_HSSPI_FIFOCFG_FIFO_WIDTH_SHIFT);
321 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
322
323 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
324 val &= ~(SYNQUACER_HSSPI_DMTRP_DATA_MASK <<
325 SYNQUACER_HSSPI_DMTRP_DATA_SHIFT);
326
327 if (xfer->rx_buf)
328 val |= (SYNQUACER_HSSPI_DMTRP_DATA_RX <<
329 SYNQUACER_HSSPI_DMTRP_DATA_SHIFT);
330 else
331 val |= (SYNQUACER_HSSPI_DMTRP_DATA_TX <<
332 SYNQUACER_HSSPI_DMTRP_DATA_SHIFT);
333
334 val &= ~(3 << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT);
335 val |= ((bus_width >> 1) << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT);
336 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
337
338 sspi->bpw = bpw;
339 sspi->mode = mode;
340 sspi->speed = speed;
341 sspi->cs = spi->chip_select;
342 sspi->bus_width = bus_width;
343
344 return 0;
345}
346
347static int synquacer_spi_transfer_one(struct spi_master *master,
348 struct spi_device *spi,
349 struct spi_transfer *xfer)
350{
351 struct synquacer_spi *sspi = spi_master_get_devdata(master);
352 int ret;
353 int status = 0;
354 u32 words;
355 u8 bpw;
356 u32 val;
357
358 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
359 val &= ~SYNQUACER_HSSPI_DMSTOP_STOP;
360 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
361
362 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
363 val |= SYNQUACER_HSSPI_FIFOCFG_RX_FLUSH;
364 val |= SYNQUACER_HSSPI_FIFOCFG_TX_FLUSH;
365 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
366
367 /*
368 * See if we can transfer 4-bytes as 1 word
369 * to maximize the FIFO buffer efficiency.
370 */
371 bpw = xfer->bits_per_word;
372 if (bpw == 8 && !(xfer->len % 4) && !(spi->mode & SPI_LSB_FIRST))
373 xfer->bits_per_word = 32;
374
375 ret = synquacer_spi_config(master, spi, xfer);
376
377 /* restore */
378 xfer->bits_per_word = bpw;
379
380 if (ret)
381 return ret;
382
383 reinit_completion(&sspi->transfer_done);
384
385 sspi->tx_buf = xfer->tx_buf;
386 sspi->rx_buf = xfer->rx_buf;
387
388 switch (sspi->bpw) {
389 case 8:
390 words = xfer->len;
391 break;
392 case 16:
393 words = xfer->len / 2;
394 break;
395 case 24:
396 /* fallthrough, should use 32-bits access */
397 case 32:
398 words = xfer->len / 4;
399 break;
400 default:
401 dev_err(sspi->dev, "unsupported bpw: %d\n", sspi->bpw);
402 return -EINVAL;
403 }
404
405 if (xfer->tx_buf)
406 sspi->tx_words = words;
407 else
408 sspi->tx_words = 0;
409
410 if (xfer->rx_buf)
411 sspi->rx_words = words;
412 else
413 sspi->rx_words = 0;
414
415 if (xfer->tx_buf) {
416 status = write_fifo(sspi);
417 if (status < 0) {
418 dev_err(sspi->dev, "failed write_fifo. status: 0x%x\n",
419 status);
420 return status;
421 }
422 }
423
424 if (xfer->rx_buf) {
425 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
426 val &= ~(SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_MASK <<
427 SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_SHIFT);
428 val |= ((sspi->rx_words > SYNQUACER_HSSPI_FIFO_DEPTH ?
429 SYNQUACER_HSSPI_FIFO_RX_THRESHOLD : sspi->rx_words) <<
430 SYNQUACER_HSSPI_FIFOCFG_RX_THRESHOLD_SHIFT);
431 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
432 }
433
434 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
435 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
436
437 /* Trigger */
438 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
439 val |= SYNQUACER_HSSPI_DMSTART_START;
440 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
441
442 if (xfer->tx_buf) {
443 val = SYNQUACER_HSSPI_TXE_FIFO_EMPTY;
444 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
445 status = wait_for_completion_timeout(&sspi->transfer_done,
446 msecs_to_jiffies(SYNQUACER_HSSPI_TRANSFER_TMOUT_MSEC));
447 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
448 }
449
450 if (xfer->rx_buf) {
451 u32 buf[SYNQUACER_HSSPI_FIFO_DEPTH];
452
453 val = SYNQUACER_HSSPI_RXE_FIFO_MORE_THAN_THRESHOLD |
454 SYNQUACER_HSSPI_RXE_SLAVE_RELEASED;
455 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
456 status = wait_for_completion_timeout(&sspi->transfer_done,
457 msecs_to_jiffies(SYNQUACER_HSSPI_TRANSFER_TMOUT_MSEC));
458 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
459
460 /* stop RX and clean RXFIFO */
461 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
462 val |= SYNQUACER_HSSPI_DMSTOP_STOP;
463 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
464 sspi->rx_buf = buf;
465 sspi->rx_words = SYNQUACER_HSSPI_FIFO_DEPTH;
466 read_fifo(sspi);
467 }
468
469 if (status < 0) {
470 dev_err(sspi->dev, "failed to transfer. status: 0x%x\n",
471 status);
472 return status;
473 }
474
475 return 0;
476}
477
478static void synquacer_spi_set_cs(struct spi_device *spi, bool enable)
479{
480 struct synquacer_spi *sspi = spi_master_get_devdata(spi->master);
481 u32 val;
482
483 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
484 val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK <<
485 SYNQUACER_HSSPI_DMPSEL_CS_SHIFT);
486 val |= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT;
487 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
488}
489
490static int synquacer_spi_wait_status_update(struct synquacer_spi *sspi,
491 bool enable)
492{
493 u32 val;
494 unsigned long timeout = jiffies +
495 msecs_to_jiffies(SYNQUACER_HSSPI_ENABLE_TMOUT_MSEC);
496
497 /* wait MES(Module Enable Status) is updated */
498 do {
499 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL) &
500 SYNQUACER_HSSPI_MCTRL_MES;
501 if (enable && val)
502 return 0;
503 if (!enable && !val)
504 return 0;
505 } while (time_before(jiffies, timeout));
506
507 dev_err(sspi->dev, "timeout occurs in updating Module Enable Status\n");
508 return -EBUSY;
509}
510
511static int synquacer_spi_enable(struct spi_master *master)
512{
513 u32 val;
514 int status;
515 struct synquacer_spi *sspi = spi_master_get_devdata(master);
516
517 /* Disable module */
518 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
519 status = synquacer_spi_wait_status_update(sspi, false);
520 if (status < 0)
521 return status;
522
523 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
524 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
525 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
526 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
527 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_FAULTC);
528
529 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMCFG);
530 val &= ~SYNQUACER_HSSPI_DMCFG_SSDC;
531 val &= ~SYNQUACER_HSSPI_DMCFG_MSTARTEN;
532 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMCFG);
533
534 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
535 if (sspi->clk_src_type == SYNQUACER_HSSPI_CLOCK_SRC_IPCLK)
536 val |= SYNQUACER_HSSPI_MCTRL_CDSS;
537 else
538 val &= ~SYNQUACER_HSSPI_MCTRL_CDSS;
539
540 val &= ~SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN;
541 val |= SYNQUACER_HSSPI_MCTRL_MEN;
542 val |= SYNQUACER_HSSPI_MCTRL_SYNCON;
543
544 /* Enable module */
545 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
546 status = synquacer_spi_wait_status_update(sspi, true);
547 if (status < 0)
548 return status;
549
550 return 0;
551}
552
553static irqreturn_t sq_spi_rx_handler(int irq, void *priv)
554{
555 uint32_t val;
556 struct synquacer_spi *sspi = priv;
557
558 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_RXF);
559 if ((val & SYNQUACER_HSSPI_RXF_SLAVE_RELEASED) ||
560 (val & SYNQUACER_HSSPI_RXF_FIFO_MORE_THAN_THRESHOLD)) {
561 read_fifo(sspi);
562
563 if (sspi->rx_words == 0) {
564 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
565 complete(&sspi->transfer_done);
566 }
567 return IRQ_HANDLED;
568 }
569
570 return IRQ_NONE;
571}
572
573static irqreturn_t sq_spi_tx_handler(int irq, void *priv)
574{
575 uint32_t val;
576 struct synquacer_spi *sspi = priv;
577
578 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_TXF);
579 if (val & SYNQUACER_HSSPI_TXF_FIFO_EMPTY) {
580 if (sspi->tx_words == 0) {
581 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
582 complete(&sspi->transfer_done);
583 } else {
584 write_fifo(sspi);
585 }
586 return IRQ_HANDLED;
587 }
588
589 return IRQ_NONE;
590}
591
592static int synquacer_spi_probe(struct platform_device *pdev)
593{
594 struct device_node *np = pdev->dev.of_node;
595 struct spi_master *master;
596 struct synquacer_spi *sspi;
597 int ret;
598 int rx_irq, tx_irq;
599
600 master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
601 if (!master)
602 return -ENOMEM;
603
604 platform_set_drvdata(pdev, master);
605
606 sspi = spi_master_get_devdata(master);
607 sspi->dev = &pdev->dev;
608
609 init_completion(&sspi->transfer_done);
610
611 sspi->regs = devm_platform_ioremap_resource(pdev, 0);
612 if (IS_ERR(sspi->regs)) {
613 ret = PTR_ERR(sspi->regs);
614 goto put_spi;
615 }
616
617 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IHCLK; /* Default */
618 device_property_read_u32(&pdev->dev, "socionext,ihclk-rate",
619 &master->max_speed_hz); /* for ACPI */
620
621 if (dev_of_node(&pdev->dev)) {
622 if (device_property_match_string(&pdev->dev,
623 "clock-names", "iHCLK") >= 0) {
624 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IHCLK;
625 sspi->clk = devm_clk_get(sspi->dev, "iHCLK");
626 } else if (device_property_match_string(&pdev->dev,
627 "clock-names", "iPCLK") >= 0) {
628 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IPCLK;
629 sspi->clk = devm_clk_get(sspi->dev, "iPCLK");
630 } else {
631 dev_err(&pdev->dev, "specified wrong clock source\n");
632 ret = -EINVAL;
633 goto put_spi;
634 }
635
636 if (IS_ERR(sspi->clk)) {
637 if (!(PTR_ERR(sspi->clk) == -EPROBE_DEFER))
638 dev_err(&pdev->dev, "clock not found\n");
639 ret = PTR_ERR(sspi->clk);
640 goto put_spi;
641 }
642
643 ret = clk_prepare_enable(sspi->clk);
644 if (ret) {
645 dev_err(&pdev->dev, "failed to enable clock (%d)\n",
646 ret);
647 goto put_spi;
648 }
649
650 master->max_speed_hz = clk_get_rate(sspi->clk);
651 }
652
653 if (!master->max_speed_hz) {
654 dev_err(&pdev->dev, "missing clock source\n");
655 return -EINVAL;
656 }
657 master->min_speed_hz = master->max_speed_hz / 254;
658
659 sspi->aces = device_property_read_bool(&pdev->dev,
660 "socionext,set-aces");
661 sspi->rtm = device_property_read_bool(&pdev->dev, "socionext,use-rtm");
662
663 master->num_chipselect = SYNQUACER_HSSPI_NUM_CHIP_SELECT;
664
665 rx_irq = platform_get_irq(pdev, 0);
666 if (rx_irq <= 0) {
667 dev_err(&pdev->dev, "get rx_irq failed (%d)\n", rx_irq);
668 ret = rx_irq;
669 goto put_spi;
670 }
671 snprintf(sspi->rx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-rx",
672 dev_name(&pdev->dev));
673 ret = devm_request_irq(&pdev->dev, rx_irq, sq_spi_rx_handler,
674 0, sspi->rx_irq_name, sspi);
675 if (ret) {
676 dev_err(&pdev->dev, "request rx_irq failed (%d)\n", ret);
677 goto put_spi;
678 }
679
680 tx_irq = platform_get_irq(pdev, 1);
681 if (tx_irq <= 0) {
682 dev_err(&pdev->dev, "get tx_irq failed (%d)\n", tx_irq);
683 ret = tx_irq;
684 goto put_spi;
685 }
686 snprintf(sspi->tx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-tx",
687 dev_name(&pdev->dev));
688 ret = devm_request_irq(&pdev->dev, tx_irq, sq_spi_tx_handler,
689 0, sspi->tx_irq_name, sspi);
690 if (ret) {
691 dev_err(&pdev->dev, "request tx_irq failed (%d)\n", ret);
692 goto put_spi;
693 }
694
695 master->dev.of_node = np;
696 master->dev.fwnode = pdev->dev.fwnode;
697 master->auto_runtime_pm = true;
698 master->bus_num = pdev->id;
699
700 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL |
701 SPI_TX_QUAD | SPI_RX_QUAD;
702 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |
703 SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
704
705 master->set_cs = synquacer_spi_set_cs;
706 master->transfer_one = synquacer_spi_transfer_one;
707
708 ret = synquacer_spi_enable(master);
709 if (ret)
710 goto fail_enable;
711
712 pm_runtime_set_active(sspi->dev);
713 pm_runtime_enable(sspi->dev);
714
715 ret = devm_spi_register_master(sspi->dev, master);
716 if (ret)
717 goto disable_pm;
718
719 return 0;
720
721disable_pm:
722 pm_runtime_disable(sspi->dev);
723fail_enable:
724 clk_disable_unprepare(sspi->clk);
725put_spi:
726 spi_master_put(master);
727
728 return ret;
729}
730
731static int synquacer_spi_remove(struct platform_device *pdev)
732{
733 struct spi_master *master = platform_get_drvdata(pdev);
734 struct synquacer_spi *sspi = spi_master_get_devdata(master);
735
736 pm_runtime_disable(sspi->dev);
737
738 clk_disable_unprepare(sspi->clk);
739
740 return 0;
741}
742
743static int __maybe_unused synquacer_spi_suspend(struct device *dev)
744{
745 struct spi_master *master = dev_get_drvdata(dev);
746 struct synquacer_spi *sspi = spi_master_get_devdata(master);
747 int ret;
748
749 ret = spi_master_suspend(master);
750 if (ret)
751 return ret;
752
753 if (!pm_runtime_suspended(dev))
754 clk_disable_unprepare(sspi->clk);
755
756 return ret;
757}
758
759static int __maybe_unused synquacer_spi_resume(struct device *dev)
760{
761 struct spi_master *master = dev_get_drvdata(dev);
762 struct synquacer_spi *sspi = spi_master_get_devdata(master);
763 int ret;
764
765 if (!pm_runtime_suspended(dev)) {
766 /* Ensure reconfigure during next xfer */
767 sspi->speed = 0;
768
769 ret = clk_prepare_enable(sspi->clk);
770 if (ret < 0) {
771 dev_err(dev, "failed to enable clk (%d)\n",
772 ret);
773 return ret;
774 }
775
776 ret = synquacer_spi_enable(master);
777 if (ret) {
778 dev_err(dev, "failed to enable spi (%d)\n", ret);
779 return ret;
780 }
781 }
782
783 ret = spi_master_resume(master);
784 if (ret < 0)
785 clk_disable_unprepare(sspi->clk);
786
787 return ret;
788}
789
790static SIMPLE_DEV_PM_OPS(synquacer_spi_pm_ops, synquacer_spi_suspend,
791 synquacer_spi_resume);
792
793static const struct of_device_id synquacer_spi_of_match[] = {
794 {.compatible = "socionext,synquacer-spi"},
795 {}
796};
797MODULE_DEVICE_TABLE(of, synquacer_spi_of_match);
798
799#ifdef CONFIG_ACPI
800static const struct acpi_device_id synquacer_hsspi_acpi_ids[] = {
801 { "SCX0004" },
802 { /* sentinel */ }
803};
804MODULE_DEVICE_TABLE(acpi, synquacer_hsspi_acpi_ids);
805#endif
806
807static struct platform_driver synquacer_spi_driver = {
808 .driver = {
809 .name = "synquacer-spi",
810 .pm = &synquacer_spi_pm_ops,
811 .of_match_table = synquacer_spi_of_match,
812 .acpi_match_table = ACPI_PTR(synquacer_hsspi_acpi_ids),
813 },
814 .probe = synquacer_spi_probe,
815 .remove = synquacer_spi_remove,
816};
817module_platform_driver(synquacer_spi_driver);
818
819MODULE_DESCRIPTION("Socionext Synquacer HS-SPI controller driver");
820MODULE_AUTHOR("Masahisa Kojima <masahisa.kojima@linaro.org>");
821MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
822MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)