Merge tag 'usb-ci-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter...
[linux-block.git] / drivers / spi / spi-sun6i.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
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2/*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
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8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/module.h>
10565dfd 16#include <linux/of_device.h>
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17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/reset.h>
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20
21#include <linux/spi/spi.h>
22
23#define SUN6I_FIFO_DEPTH 128
10565dfd 24#define SUN8I_FIFO_DEPTH 64
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25
26#define SUN6I_GBL_CTL_REG 0x04
27#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
28#define SUN6I_GBL_CTL_MASTER BIT(1)
29#define SUN6I_GBL_CTL_TP BIT(7)
30#define SUN6I_GBL_CTL_RST BIT(31)
31
32#define SUN6I_TFR_CTL_REG 0x08
33#define SUN6I_TFR_CTL_CPHA BIT(0)
34#define SUN6I_TFR_CTL_CPOL BIT(1)
35#define SUN6I_TFR_CTL_SPOL BIT(2)
d31ad46f
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36#define SUN6I_TFR_CTL_CS_MASK 0x30
37#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
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38#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
39#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
40#define SUN6I_TFR_CTL_DHB BIT(8)
41#define SUN6I_TFR_CTL_FBS BIT(12)
42#define SUN6I_TFR_CTL_XCH BIT(31)
43
44#define SUN6I_INT_CTL_REG 0x10
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45#define SUN6I_INT_CTL_RF_RDY BIT(0)
46#define SUN6I_INT_CTL_TF_ERQ BIT(4)
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47#define SUN6I_INT_CTL_RF_OVF BIT(8)
48#define SUN6I_INT_CTL_TC BIT(12)
49
50#define SUN6I_INT_STA_REG 0x14
51
52#define SUN6I_FIFO_CTL_REG 0x18
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53#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
54#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
3558fe90 55#define SUN6I_FIFO_CTL_RF_RST BIT(15)
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56#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
57#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
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58#define SUN6I_FIFO_CTL_TF_RST BIT(31)
59
60#define SUN6I_FIFO_STA_REG 0x1c
61#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
62#define SUN6I_FIFO_STA_RF_CNT_BITS 0
63#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
64#define SUN6I_FIFO_STA_TF_CNT_BITS 16
65
66#define SUN6I_CLK_CTL_REG 0x24
67#define SUN6I_CLK_CTL_CDR2_MASK 0xff
68#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
69#define SUN6I_CLK_CTL_CDR1_MASK 0xf
70#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
71#define SUN6I_CLK_CTL_DRS BIT(12)
72
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73#define SUN6I_MAX_XFER_SIZE 0xffffff
74
3558fe90 75#define SUN6I_BURST_CNT_REG 0x30
913f536c 76#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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77
78#define SUN6I_XMIT_CNT_REG 0x34
913f536c 79#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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80
81#define SUN6I_BURST_CTL_CNT_REG 0x38
913f536c 82#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
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83
84#define SUN6I_TXDATA_REG 0x200
85#define SUN6I_RXDATA_REG 0x300
86
87struct sun6i_spi {
88 struct spi_master *master;
89 void __iomem *base_addr;
90 struct clk *hclk;
91 struct clk *mclk;
92 struct reset_control *rstc;
93
94 struct completion done;
95
96 const u8 *tx_buf;
97 u8 *rx_buf;
98 int len;
10565dfd 99 unsigned long fifo_depth;
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100};
101
102static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
103{
104 return readl(sspi->base_addr + reg);
105}
106
107static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
108{
109 writel(value, sspi->base_addr + reg);
110}
111
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112static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
113{
114 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
115
116 reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
117
118 return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
119}
120
121static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
122{
123 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
124
125 reg |= mask;
126 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
127}
128
129static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
130{
131 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
132
133 reg &= ~mask;
134 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
135}
136
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137static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
138{
139 u32 reg, cnt;
140 u8 byte;
141
142 /* See how much data is available */
143 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
144 reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
145 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
146
147 if (len > cnt)
148 len = cnt;
149
150 while (len--) {
151 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
152 if (sspi->rx_buf)
153 *sspi->rx_buf++ = byte;
154 }
155}
156
157static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
158{
913f536c 159 u32 cnt;
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160 u8 byte;
161
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162 /* See how much data we can fit */
163 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
164
165 len = min3(len, (int)cnt, sspi->len);
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166
167 while (len--) {
168 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
169 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
170 sspi->len--;
171 }
172}
173
174static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
175{
176 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
177 u32 reg;
178
179 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
180 reg &= ~SUN6I_TFR_CTL_CS_MASK;
181 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
182
183 if (enable)
184 reg |= SUN6I_TFR_CTL_CS_LEVEL;
185 else
186 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
187
188 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
189}
190
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191static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
192{
3288d5cb 193 return SUN6I_MAX_XFER_SIZE - 1;
794912cf 194}
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195
196static int sun6i_spi_transfer_one(struct spi_master *master,
197 struct spi_device *spi,
198 struct spi_transfer *tfr)
199{
200 struct sun6i_spi *sspi = spi_master_get_devdata(master);
ed7815db 201 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
719bd654 202 unsigned int start, end, tx_time;
913f536c 203 unsigned int trig_level;
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204 unsigned int tx_len = 0;
205 int ret = 0;
206 u32 reg;
207
913f536c 208 if (tfr->len > SUN6I_MAX_XFER_SIZE)
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209 return -EINVAL;
210
211 reinit_completion(&sspi->done);
212 sspi->tx_buf = tfr->tx_buf;
213 sspi->rx_buf = tfr->rx_buf;
214 sspi->len = tfr->len;
215
216 /* Clear pending interrupts */
217 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
218
219 /* Reset FIFO */
220 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
221 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
222
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223 /*
224 * Setup FIFO interrupt trigger level
225 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
226 * value used in old generation of Allwinner SPI controller.
227 * (See spi-sun4i.c)
228 */
229 trig_level = sspi->fifo_depth / 4 * 3;
230 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
231 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
232 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
233
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234 /*
235 * Setup the transfer control register: Chip Select,
236 * polarities, etc.
237 */
238 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
239
240 if (spi->mode & SPI_CPOL)
241 reg |= SUN6I_TFR_CTL_CPOL;
242 else
243 reg &= ~SUN6I_TFR_CTL_CPOL;
244
245 if (spi->mode & SPI_CPHA)
246 reg |= SUN6I_TFR_CTL_CPHA;
247 else
248 reg &= ~SUN6I_TFR_CTL_CPHA;
249
250 if (spi->mode & SPI_LSB_FIRST)
251 reg |= SUN6I_TFR_CTL_FBS;
252 else
253 reg &= ~SUN6I_TFR_CTL_FBS;
254
255 /*
256 * If it's a TX only transfer, we don't want to fill the RX
257 * FIFO with bogus data
258 */
259 if (sspi->rx_buf)
260 reg &= ~SUN6I_TFR_CTL_DHB;
261 else
262 reg |= SUN6I_TFR_CTL_DHB;
263
264 /* We want to control the chip select manually */
265 reg |= SUN6I_TFR_CTL_CS_MANUAL;
266
267 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
268
269 /* Ensure that we have a parent clock fast enough */
270 mclk_rate = clk_get_rate(sspi->mclk);
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271 if (mclk_rate < (2 * tfr->speed_hz)) {
272 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
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273 mclk_rate = clk_get_rate(sspi->mclk);
274 }
275
276 /*
277 * Setup clock divider.
278 *
279 * We have two choices there. Either we can use the clock
280 * divide rate 1, which is calculated thanks to this formula:
281 * SPI_CLK = MOD_CLK / (2 ^ cdr)
282 * Or we can use CDR2, which is calculated with the formula:
283 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
284 * Wether we use the former or the latter is set through the
285 * DRS bit.
286 *
287 * First try CDR2, and if we can't reach the expected
288 * frequency, fall back to CDR1.
289 */
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290 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
291 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
292 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
293 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
3558fe90 294 } else {
ed7815db 295 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
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296 reg = SUN6I_CLK_CTL_CDR1(div);
297 }
298
299 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
300
301 /* Setup the transfer now... */
302 if (sspi->tx_buf)
303 tx_len = tfr->len;
304
305 /* Setup the counters */
306 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
307 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
308 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
309 SUN6I_BURST_CTL_CNT_STC(tx_len));
310
311 /* Fill the TX FIFO */
10565dfd 312 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
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313
314 /* Enable the interrupts */
315 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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316 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
317 SUN6I_INT_CTL_RF_RDY);
318 if (tx_len > sspi->fifo_depth)
319 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
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320
321 /* Start the transfer */
322 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
323 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
324
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MS
325 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
326 start = jiffies;
3558fe90 327 timeout = wait_for_completion_timeout(&sspi->done,
719bd654
MS
328 msecs_to_jiffies(tx_time));
329 end = jiffies;
3558fe90 330 if (!timeout) {
719bd654
MS
331 dev_warn(&master->dev,
332 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
333 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
334 jiffies_to_msecs(end - start), tx_time);
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335 ret = -ETIMEDOUT;
336 goto out;
337 }
338
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339out:
340 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
341
342 return ret;
343}
344
345static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
346{
347 struct sun6i_spi *sspi = dev_id;
348 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
349
350 /* Transfer complete */
351 if (status & SUN6I_INT_CTL_TC) {
352 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
913f536c 353 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
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354 complete(&sspi->done);
355 return IRQ_HANDLED;
356 }
357
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358 /* Receive FIFO 3/4 full */
359 if (status & SUN6I_INT_CTL_RF_RDY) {
360 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
361 /* Only clear the interrupt _after_ draining the FIFO */
362 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
363 return IRQ_HANDLED;
364 }
365
366 /* Transmit FIFO 3/4 empty */
367 if (status & SUN6I_INT_CTL_TF_ERQ) {
368 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
369
370 if (!sspi->len)
371 /* nothing left to transmit */
372 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
373
374 /* Only clear the interrupt _after_ re-seeding the FIFO */
375 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
376
377 return IRQ_HANDLED;
378 }
379
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380 return IRQ_NONE;
381}
382
383static int sun6i_spi_runtime_resume(struct device *dev)
384{
385 struct spi_master *master = dev_get_drvdata(dev);
386 struct sun6i_spi *sspi = spi_master_get_devdata(master);
387 int ret;
388
389 ret = clk_prepare_enable(sspi->hclk);
390 if (ret) {
391 dev_err(dev, "Couldn't enable AHB clock\n");
392 goto out;
393 }
394
395 ret = clk_prepare_enable(sspi->mclk);
396 if (ret) {
397 dev_err(dev, "Couldn't enable module clock\n");
398 goto err;
399 }
400
401 ret = reset_control_deassert(sspi->rstc);
402 if (ret) {
403 dev_err(dev, "Couldn't deassert the device from reset\n");
404 goto err2;
405 }
406
407 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
408 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
409
410 return 0;
411
412err2:
413 clk_disable_unprepare(sspi->mclk);
414err:
415 clk_disable_unprepare(sspi->hclk);
416out:
417 return ret;
418}
419
420static int sun6i_spi_runtime_suspend(struct device *dev)
421{
422 struct spi_master *master = dev_get_drvdata(dev);
423 struct sun6i_spi *sspi = spi_master_get_devdata(master);
424
425 reset_control_assert(sspi->rstc);
426 clk_disable_unprepare(sspi->mclk);
427 clk_disable_unprepare(sspi->hclk);
428
429 return 0;
430}
431
432static int sun6i_spi_probe(struct platform_device *pdev)
433{
434 struct spi_master *master;
435 struct sun6i_spi *sspi;
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436 int ret = 0, irq;
437
438 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
439 if (!master) {
440 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
441 return -ENOMEM;
442 }
443
444 platform_set_drvdata(pdev, master);
445 sspi = spi_master_get_devdata(master);
446
7c7c31f7 447 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
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448 if (IS_ERR(sspi->base_addr)) {
449 ret = PTR_ERR(sspi->base_addr);
450 goto err_free_master;
451 }
452
453 irq = platform_get_irq(pdev, 0);
454 if (irq < 0) {
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455 ret = -ENXIO;
456 goto err_free_master;
457 }
458
459 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
460 0, "sun6i-spi", sspi);
461 if (ret) {
462 dev_err(&pdev->dev, "Cannot request IRQ\n");
463 goto err_free_master;
464 }
465
466 sspi->master = master;
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467 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
468
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469 master->max_speed_hz = 100 * 1000 * 1000;
470 master->min_speed_hz = 3 * 1000;
74750e06 471 master->use_gpio_descriptors = true;
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472 master->set_cs = sun6i_spi_set_cs;
473 master->transfer_one = sun6i_spi_transfer_one;
474 master->num_chipselect = 4;
475 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
743a46b8 476 master->bits_per_word_mask = SPI_BPW_MASK(8);
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477 master->dev.of_node = pdev->dev.of_node;
478 master->auto_runtime_pm = true;
794912cf 479 master->max_transfer_size = sun6i_spi_max_transfer_size;
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480
481 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
482 if (IS_ERR(sspi->hclk)) {
483 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
484 ret = PTR_ERR(sspi->hclk);
485 goto err_free_master;
486 }
487
488 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
489 if (IS_ERR(sspi->mclk)) {
490 dev_err(&pdev->dev, "Unable to acquire module clock\n");
491 ret = PTR_ERR(sspi->mclk);
492 goto err_free_master;
493 }
494
495 init_completion(&sspi->done);
496
36bc7491 497 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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498 if (IS_ERR(sspi->rstc)) {
499 dev_err(&pdev->dev, "Couldn't get reset controller\n");
500 ret = PTR_ERR(sspi->rstc);
501 goto err_free_master;
502 }
503
504 /*
505 * This wake-up/shutdown pattern is to be able to have the
506 * device woken up, even if runtime_pm is disabled
507 */
508 ret = sun6i_spi_runtime_resume(&pdev->dev);
509 if (ret) {
510 dev_err(&pdev->dev, "Couldn't resume the device\n");
511 goto err_free_master;
512 }
513
514 pm_runtime_set_active(&pdev->dev);
515 pm_runtime_enable(&pdev->dev);
516 pm_runtime_idle(&pdev->dev);
517
518 ret = devm_spi_register_master(&pdev->dev, master);
519 if (ret) {
520 dev_err(&pdev->dev, "cannot register SPI master\n");
521 goto err_pm_disable;
522 }
523
524 return 0;
525
526err_pm_disable:
527 pm_runtime_disable(&pdev->dev);
528 sun6i_spi_runtime_suspend(&pdev->dev);
529err_free_master:
530 spi_master_put(master);
531 return ret;
532}
533
534static int sun6i_spi_remove(struct platform_device *pdev)
535{
2d9bbd02 536 pm_runtime_force_suspend(&pdev->dev);
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537
538 return 0;
539}
540
541static const struct of_device_id sun6i_spi_match[] = {
10565dfd
MK
542 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
543 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
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MR
544 {}
545};
546MODULE_DEVICE_TABLE(of, sun6i_spi_match);
547
548static const struct dev_pm_ops sun6i_spi_pm_ops = {
549 .runtime_resume = sun6i_spi_runtime_resume,
550 .runtime_suspend = sun6i_spi_runtime_suspend,
551};
552
553static struct platform_driver sun6i_spi_driver = {
554 .probe = sun6i_spi_probe,
555 .remove = sun6i_spi_remove,
556 .driver = {
557 .name = "sun6i-spi",
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558 .of_match_table = sun6i_spi_match,
559 .pm = &sun6i_spi_pm_ops,
560 },
561};
562module_platform_driver(sun6i_spi_driver);
563
564MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
565MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
566MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
567MODULE_LICENSE("GPL");