[linux-block.git] / drivers / spi / spi-sun6i.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2012 - 2014 Allwinner Tech
 * Pan Nan <pannan@allwinnertech.com>
 *
 * Copyright (C) 2014 Maxime Ripard
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>

#include <linux/spi/spi.h>

#define SUN6I_FIFO_DEPTH		128
#define SUN8I_FIFO_DEPTH		64

#define SUN6I_GBL_CTL_REG		0x04
#define SUN6I_GBL_CTL_BUS_ENABLE		BIT(0)
#define SUN6I_GBL_CTL_MASTER			BIT(1)
#define SUN6I_GBL_CTL_TP			BIT(7)
#define SUN6I_GBL_CTL_RST			BIT(31)

#define SUN6I_TFR_CTL_REG		0x08
#define SUN6I_TFR_CTL_CPHA			BIT(0)
#define SUN6I_TFR_CTL_CPOL			BIT(1)
#define SUN6I_TFR_CTL_SPOL			BIT(2)
#define SUN6I_TFR_CTL_CS_MASK			0x30
#define SUN6I_TFR_CTL_CS(cs)			(((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
#define SUN6I_TFR_CTL_CS_MANUAL			BIT(6)
#define SUN6I_TFR_CTL_CS_LEVEL			BIT(7)
#define SUN6I_TFR_CTL_DHB			BIT(8)
#define SUN6I_TFR_CTL_FBS			BIT(12)
#define SUN6I_TFR_CTL_XCH			BIT(31)

#define SUN6I_INT_CTL_REG		0x10
#define SUN6I_INT_CTL_RF_RDY			BIT(0)
#define SUN6I_INT_CTL_TF_ERQ			BIT(4)
#define SUN6I_INT_CTL_RF_OVF			BIT(8)
#define SUN6I_INT_CTL_TC			BIT(12)

#define SUN6I_INT_STA_REG		0x14

#define SUN6I_FIFO_CTL_REG		0x18
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK	0xff
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS	0
#define SUN6I_FIFO_CTL_RF_RST			BIT(15)
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK	0xff
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS	16
#define SUN6I_FIFO_CTL_TF_RST			BIT(31)

#define SUN6I_FIFO_STA_REG		0x1c
#define SUN6I_FIFO_STA_RF_CNT_MASK		0x7f
#define SUN6I_FIFO_STA_RF_CNT_BITS		0
#define SUN6I_FIFO_STA_TF_CNT_MASK		0x7f
#define SUN6I_FIFO_STA_TF_CNT_BITS		16

#define SUN6I_CLK_CTL_REG		0x24
#define SUN6I_CLK_CTL_CDR2_MASK			0xff
#define SUN6I_CLK_CTL_CDR2(div)			(((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
#define SUN6I_CLK_CTL_CDR1_MASK			0xf
#define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
#define SUN6I_CLK_CTL_DRS			BIT(12)

#define SUN6I_MAX_XFER_SIZE		0xffffff

#define SUN6I_BURST_CNT_REG		0x30
#define SUN6I_BURST_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_XMIT_CNT_REG		0x34
#define SUN6I_XMIT_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_BURST_CTL_CNT_REG		0x38
#define SUN6I_BURST_CTL_CNT_STC(cnt)		((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_TXDATA_REG		0x200
#define SUN6I_RXDATA_REG		0x300

struct sun6i_spi {
	struct spi_master	*master;
	void __iomem		*base_addr;
	struct clk		*hclk;
	struct clk		*mclk;
	struct reset_control	*rstc;

	struct completion	done;

	const u8		*tx_buf;
	u8			*rx_buf;
	int			len;
	unsigned long		fifo_depth;
};

static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
{
	return readl(sspi->base_addr + reg);
}

static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
{
	writel(value, sspi->base_addr + reg);
}

static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);

	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;

	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
}

static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

	reg |= mask;
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
}

static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

	reg &= ~mask;
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
}

static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
{
	u32 reg, cnt;
	u8 byte;

	/* See how much data is available */
	reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
	cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;

	if (len > cnt)
		len = cnt;

	while (len--) {
		byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
		if (sspi->rx_buf)
			*sspi->rx_buf++ = byte;
	}
}

static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
{
	u32 cnt;
	u8 byte;

	/* See how much data we can fit */
	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);

	len = min3(len, (int)cnt, sspi->len);

	while (len--) {
		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
		writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
		sspi->len--;
	}
}

static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
	u32 reg;

	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	reg &= ~SUN6I_TFR_CTL_CS_MASK;
	reg |= SUN6I_TFR_CTL_CS(spi->chip_select);

	if (enable)
		reg |= SUN6I_TFR_CTL_CS_LEVEL;
	else
		reg &= ~SUN6I_TFR_CTL_CS_LEVEL;

	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
}

static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
{
	return SUN6I_MAX_XFER_SIZE - 1;
}

static int sun6i_spi_transfer_one(struct spi_master *master,
				  struct spi_device *spi,
				  struct spi_transfer *tfr)
{
	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	unsigned int mclk_rate, div, timeout;
	unsigned int start, end, tx_time;
	unsigned int trig_level;
	unsigned int tx_len = 0;
	int ret = 0;
	u32 reg;

	if (tfr->len > SUN6I_MAX_XFER_SIZE)
		return -EINVAL;

	reinit_completion(&sspi->done);
	sspi->tx_buf = tfr->tx_buf;
	sspi->rx_buf = tfr->rx_buf;
	sspi->len = tfr->len;

	/* Clear pending interrupts */
	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);

	/* Reset FIFO */
	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);

	/*
	 * Setup FIFO interrupt trigger level
	 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
	 * value used in old generation of Allwinner SPI controller.
	 * (See spi-sun4i.c)
	 */
	trig_level = sspi->fifo_depth / 4 * 3;
	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
			(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
			(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));

	/*
	 * Setup the transfer control register: Chip Select,
	 * polarities, etc.
	 */
	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);

	if (spi->mode & SPI_CPOL)
		reg |= SUN6I_TFR_CTL_CPOL;
	else
		reg &= ~SUN6I_TFR_CTL_CPOL;

	if (spi->mode & SPI_CPHA)
		reg |= SUN6I_TFR_CTL_CPHA;
	else
		reg &= ~SUN6I_TFR_CTL_CPHA;

	if (spi->mode & SPI_LSB_FIRST)
		reg |= SUN6I_TFR_CTL_FBS;
	else
		reg &= ~SUN6I_TFR_CTL_FBS;

	/*
	 * If it's a TX only transfer, we don't want to fill the RX
	 * FIFO with bogus data
	 */
	if (sspi->rx_buf)
		reg &= ~SUN6I_TFR_CTL_DHB;
	else
		reg |= SUN6I_TFR_CTL_DHB;

	/* We want to control the chip select manually */
	reg |= SUN6I_TFR_CTL_CS_MANUAL;

	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);

	/* Ensure that we have a parent clock fast enough */
	mclk_rate = clk_get_rate(sspi->mclk);
	if (mclk_rate < (2 * tfr->speed_hz)) {
		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
		mclk_rate = clk_get_rate(sspi->mclk);
	}

	/*
	 * Setup clock divider.
	 *
	 * We have two choices there. Either we can use the clock
	 * divide rate 1, which is calculated thanks to this formula:
	 * SPI_CLK = MOD_CLK / (2 ^ cdr)
	 * Or we can use CDR2, which is calculated with the formula:
	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
	 * Wether we use the former or the latter is set through the
	 * DRS bit.
	 *
	 * First try CDR2, and if we can't reach the expected
	 * frequency, fall back to CDR1.
	 */
	div = mclk_rate / (2 * tfr->speed_hz);
	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
		if (div > 0)
			div--;

		reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
	} else {
		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
		reg = SUN6I_CLK_CTL_CDR1(div);
	}

	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);

	/* Setup the transfer now... */
	if (sspi->tx_buf)
		tx_len = tfr->len;

	/* Setup the counters */
	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
			SUN6I_BURST_CTL_CNT_STC(tx_len));

	/* Fill the TX FIFO */
	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);

	/* Enable the interrupts */
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
					 SUN6I_INT_CTL_RF_RDY);
	if (tx_len > sspi->fifo_depth)
		sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

	/* Start the transfer */
	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);

	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
	start = jiffies;
	timeout = wait_for_completion_timeout(&sspi->done,
					      msecs_to_jiffies(tx_time));
	end = jiffies;
	if (!timeout) {
		dev_warn(&master->dev,
			 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
			 jiffies_to_msecs(end - start), tx_time);
		ret = -ETIMEDOUT;
		goto out;
	}

out:
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);

	return ret;
}

static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
{
	struct sun6i_spi *sspi = dev_id;
	u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);

	/* Transfer complete */
	if (status & SUN6I_INT_CTL_TC) {
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
		sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
		complete(&sspi->done);
		return IRQ_HANDLED;
	}

	/* Receive FIFO 3/4 full */
	if (status & SUN6I_INT_CTL_RF_RDY) {
		sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
		/* Only clear the interrupt _after_ draining the FIFO */
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
		return IRQ_HANDLED;
	}

	/* Transmit FIFO 3/4 empty */
	if (status & SUN6I_INT_CTL_TF_ERQ) {
		sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);

		if (!sspi->len)
			/* nothing left to transmit */
			sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

		/* Only clear the interrupt _after_ re-seeding the FIFO */
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int sun6i_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(sspi->hclk);
	if (ret) {
		dev_err(dev, "Couldn't enable AHB clock\n");
		goto out;
	}

	ret = clk_prepare_enable(sspi->mclk);
	if (ret) {
		dev_err(dev, "Couldn't enable module clock\n");
		goto err;
	}

	ret = reset_control_deassert(sspi->rstc);
	if (ret) {
		dev_err(dev, "Couldn't deassert the device from reset\n");
		goto err2;
	}

	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
			SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);

	return 0;

err2:
	clk_disable_unprepare(sspi->mclk);
err:
	clk_disable_unprepare(sspi->hclk);
out:
	return ret;
}

static int sun6i_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct sun6i_spi *sspi = spi_master_get_devdata(master);

	reset_control_assert(sspi->rstc);
	clk_disable_unprepare(sspi->mclk);
	clk_disable_unprepare(sspi->hclk);

	return 0;
}

static int sun6i_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct sun6i_spi *sspi;
	struct resource	*res;
	int ret = 0, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
	if (!master) {
		dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);
	sspi = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sspi->base_addr)) {
		ret = PTR_ERR(sspi->base_addr);
		goto err_free_master;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "No spi IRQ specified\n");
		ret = -ENXIO;
		goto err_free_master;
	}

	ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
			       0, "sun6i-spi", sspi);
	if (ret) {
		dev_err(&pdev->dev, "Cannot request IRQ\n");
		goto err_free_master;
	}

	sspi->master = master;
	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);

	master->max_speed_hz = 100 * 1000 * 1000;
	master->min_speed_hz = 3 * 1000;
	master->set_cs = sun6i_spi_set_cs;
	master->transfer_one = sun6i_spi_transfer_one;
	master->num_chipselect = 4;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->dev.of_node = pdev->dev.of_node;
	master->auto_runtime_pm = true;
	master->max_transfer_size = sun6i_spi_max_transfer_size;

	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sspi->hclk)) {
		dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
		ret = PTR_ERR(sspi->hclk);
		goto err_free_master;
	}

	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
	if (IS_ERR(sspi->mclk)) {
		dev_err(&pdev->dev, "Unable to acquire module clock\n");
		ret = PTR_ERR(sspi->mclk);
		goto err_free_master;
	}

	init_completion(&sspi->done);

	sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (IS_ERR(sspi->rstc)) {
		dev_err(&pdev->dev, "Couldn't get reset controller\n");
		ret = PTR_ERR(sspi->rstc);
		goto err_free_master;
	}

	/*
	 * This wake-up/shutdown pattern is to be able to have the
	 * device woken up, even if runtime_pm is disabled
	 */
	ret = sun6i_spi_runtime_resume(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Couldn't resume the device\n");
		goto err_free_master;
	}

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_idle(&pdev->dev);

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "cannot register SPI master\n");
		goto err_pm_disable;
	}

	return 0;

err_pm_disable:
	pm_runtime_disable(&pdev->dev);
	sun6i_spi_runtime_suspend(&pdev->dev);
err_free_master:
	spi_master_put(master);
	return ret;
}

static int sun6i_spi_remove(struct platform_device *pdev)
{
	pm_runtime_force_suspend(&pdev->dev);

	return 0;
}

static const struct of_device_id sun6i_spi_match[] = {
	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
	{ .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
	{}
};
MODULE_DEVICE_TABLE(of, sun6i_spi_match);

static const struct dev_pm_ops sun6i_spi_pm_ops = {
	.runtime_resume		= sun6i_spi_runtime_resume,
	.runtime_suspend	= sun6i_spi_runtime_suspend,
};

static struct platform_driver sun6i_spi_driver = {
	.probe	= sun6i_spi_probe,
	.remove	= sun6i_spi_remove,
	.driver	= {
		.name		= "sun6i-spi",
		.of_match_table	= sun6i_spi_match,
		.pm		= &sun6i_spi_pm_ops,
	},
};
module_platform_driver(sun6i_spi_driver);

MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
3558fe90 MR	2	/*
	3	* Copyright (C) 2012 - 2014 Allwinner Tech
	4	* Pan Nan <pannan@allwinnertech.com>
	5	*
	6	* Copyright (C) 2014 Maxime Ripard
	7	* Maxime Ripard <maxime.ripard@free-electrons.com>
3558fe90 MR	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/delay.h>
	12	#include <linux/device.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/io.h>
	15	#include <linux/module.h>
10565dfd	16	#include <linux/of_device.h>
3558fe90 MR	17	#include <linux/platform_device.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/reset.h>
3558fe90 MR	20
	21	#include <linux/spi/spi.h>
	22
	23	#define SUN6I_FIFO_DEPTH 128
10565dfd	24	#define SUN8I_FIFO_DEPTH 64
3558fe90 MR	25
	26	#define SUN6I_GBL_CTL_REG 0x04
	27	#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
	28	#define SUN6I_GBL_CTL_MASTER BIT(1)
	29	#define SUN6I_GBL_CTL_TP BIT(7)
	30	#define SUN6I_GBL_CTL_RST BIT(31)
	31
	32	#define SUN6I_TFR_CTL_REG 0x08
	33	#define SUN6I_TFR_CTL_CPHA BIT(0)
	34	#define SUN6I_TFR_CTL_CPOL BIT(1)
	35	#define SUN6I_TFR_CTL_SPOL BIT(2)
d31ad46f AL	36	#define SUN6I_TFR_CTL_CS_MASK 0x30
d31ad46f AL	37	#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
3558fe90 MR	38	#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
	39	#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
	40	#define SUN6I_TFR_CTL_DHB BIT(8)
	41	#define SUN6I_TFR_CTL_FBS BIT(12)
	42	#define SUN6I_TFR_CTL_XCH BIT(31)
	43
	44	#define SUN6I_INT_CTL_REG 0x10
913f536c IZ	45	#define SUN6I_INT_CTL_RF_RDY BIT(0)
913f536c IZ	46	#define SUN6I_INT_CTL_TF_ERQ BIT(4)
3558fe90 MR	47	#define SUN6I_INT_CTL_RF_OVF BIT(8)
	48	#define SUN6I_INT_CTL_TC BIT(12)
	49
	50	#define SUN6I_INT_STA_REG 0x14
	51
	52	#define SUN6I_FIFO_CTL_REG 0x18
913f536c IZ	53	#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
913f536c IZ	54	#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
3558fe90	55	#define SUN6I_FIFO_CTL_RF_RST BIT(15)
913f536c IZ	56	#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
913f536c IZ	57	#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
3558fe90 MR	58	#define SUN6I_FIFO_CTL_TF_RST BIT(31)
	59
	60	#define SUN6I_FIFO_STA_REG 0x1c
	61	#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
	62	#define SUN6I_FIFO_STA_RF_CNT_BITS 0
	63	#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
	64	#define SUN6I_FIFO_STA_TF_CNT_BITS 16
	65
	66	#define SUN6I_CLK_CTL_REG 0x24
	67	#define SUN6I_CLK_CTL_CDR2_MASK 0xff
	68	#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
	69	#define SUN6I_CLK_CTL_CDR1_MASK 0xf
	70	#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
	71	#define SUN6I_CLK_CTL_DRS BIT(12)
	72
913f536c IZ	73	#define SUN6I_MAX_XFER_SIZE 0xffffff
913f536c IZ	74
3558fe90	75	#define SUN6I_BURST_CNT_REG 0x30
913f536c	76	#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	77
3558fe90 MR	78	#define SUN6I_XMIT_CNT_REG 0x34
913f536c	79	#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	80
3558fe90 MR	81	#define SUN6I_BURST_CTL_CNT_REG 0x38
913f536c	82	#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	83
	84	#define SUN6I_TXDATA_REG 0x200
	85	#define SUN6I_RXDATA_REG 0x300
	86
	87	struct sun6i_spi {
	88	struct spi_master *master;
	89	void __iomem *base_addr;
	90	struct clk *hclk;
	91	struct clk *mclk;
	92	struct reset_control *rstc;
	93
	94	struct completion done;
	95
	96	const u8 *tx_buf;
	97	u8 *rx_buf;
	98	int len;
10565dfd	99	unsigned long fifo_depth;
3558fe90 MR	100	};
	101
	102	static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
	103	{
	104	return readl(sspi->base_addr + reg);
	105	}
	106
	107	static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
	108	{
	109	writel(value, sspi->base_addr + reg);
	110	}
	111
913f536c IZ	112	static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
	113	{
	114	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	115
	116	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
	117
	118	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
	119	}
	120
	121	static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
	122	{
	123	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
	124
	125	reg \|= mask;
	126	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
	127	}
	128
	129	static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
	130	{
	131	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
	132
	133	reg &= ~mask;
	134	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
	135	}
	136
3558fe90 MR	137	static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
	138	{
	139	u32 reg, cnt;
	140	u8 byte;
	141
	142	/* See how much data is available */
	143	reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	144	reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
	145	cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
	146
	147	if (len > cnt)
	148	len = cnt;
	149
	150	while (len--) {
	151	byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
	152	if (sspi->rx_buf)
	153	*sspi->rx_buf++ = byte;
	154	}
	155	}
	156
	157	static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
	158	{
913f536c	159	u32 cnt;
3558fe90 MR	160	u8 byte;
3558fe90 MR	161
913f536c IZ	162	/* See how much data we can fit */
	163	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
	164
	165	len = min3(len, (int)cnt, sspi->len);
3558fe90 MR	166
	167	while (len--) {
	168	byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
	169	writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
	170	sspi->len--;
	171	}
	172	}
	173
	174	static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
	175	{
	176	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
	177	u32 reg;
	178
	179	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	180	reg &= ~SUN6I_TFR_CTL_CS_MASK;
	181	reg \|= SUN6I_TFR_CTL_CS(spi->chip_select);
	182
	183	if (enable)
	184	reg \|= SUN6I_TFR_CTL_CS_LEVEL;
	185	else
	186	reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
	187
	188	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
	189	}
	190
794912cf MS	191	static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
794912cf MS	192	{
3288d5cb	193	return SUN6I_MAX_XFER_SIZE - 1;
794912cf	194	}
3558fe90 MR	195
	196	static int sun6i_spi_transfer_one(struct spi_master *master,
	197	struct spi_device *spi,
	198	struct spi_transfer *tfr)
	199	{
	200	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	201	unsigned int mclk_rate, div, timeout;
719bd654	202	unsigned int start, end, tx_time;
913f536c	203	unsigned int trig_level;
3558fe90 MR	204	unsigned int tx_len = 0;
	205	int ret = 0;
	206	u32 reg;
	207
913f536c	208	if (tfr->len > SUN6I_MAX_XFER_SIZE)
3558fe90 MR	209	return -EINVAL;
	210
	211	reinit_completion(&sspi->done);
	212	sspi->tx_buf = tfr->tx_buf;
	213	sspi->rx_buf = tfr->rx_buf;
	214	sspi->len = tfr->len;
	215
	216	/* Clear pending interrupts */
	217	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
	218
	219	/* Reset FIFO */
	220	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
	221	SUN6I_FIFO_CTL_RF_RST \| SUN6I_FIFO_CTL_TF_RST);
	222
913f536c IZ	223	/*
	224	* Setup FIFO interrupt trigger level
	225	* Here we choose 3/4 of the full fifo depth, as it's the hardcoded
	226	* value used in old generation of Allwinner SPI controller.
	227	* (See spi-sun4i.c)
	228	*/
	229	trig_level = sspi->fifo_depth / 4 * 3;
	230	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
	231	(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) \|
	232	(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
	233
3558fe90 MR	234	/*
	235	* Setup the transfer control register: Chip Select,
	236	* polarities, etc.
	237	*/
	238	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	239
	240	if (spi->mode & SPI_CPOL)
	241	reg \|= SUN6I_TFR_CTL_CPOL;
	242	else
	243	reg &= ~SUN6I_TFR_CTL_CPOL;
	244
	245	if (spi->mode & SPI_CPHA)
	246	reg \|= SUN6I_TFR_CTL_CPHA;
	247	else
	248	reg &= ~SUN6I_TFR_CTL_CPHA;
	249
	250	if (spi->mode & SPI_LSB_FIRST)
	251	reg \|= SUN6I_TFR_CTL_FBS;
	252	else
	253	reg &= ~SUN6I_TFR_CTL_FBS;
	254
	255	/*
	256	* If it's a TX only transfer, we don't want to fill the RX
	257	* FIFO with bogus data
	258	*/
	259	if (sspi->rx_buf)
	260	reg &= ~SUN6I_TFR_CTL_DHB;
	261	else
	262	reg \|= SUN6I_TFR_CTL_DHB;
	263
	264	/* We want to control the chip select manually */
	265	reg \|= SUN6I_TFR_CTL_CS_MANUAL;
	266
	267	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
	268
	269	/* Ensure that we have a parent clock fast enough */
	270	mclk_rate = clk_get_rate(sspi->mclk);
47284e3e MW	271	if (mclk_rate < (2 * tfr->speed_hz)) {
47284e3e MW	272	clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
3558fe90 MR	273	mclk_rate = clk_get_rate(sspi->mclk);
	274	}
	275
	276	/*
	277	* Setup clock divider.
	278	*
	279	* We have two choices there. Either we can use the clock
	280	* divide rate 1, which is calculated thanks to this formula:
	281	* SPI_CLK = MOD_CLK / (2 ^ cdr)
	282	* Or we can use CDR2, which is calculated with the formula:
	283	* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
	284	* Wether we use the former or the latter is set through the
	285	* DRS bit.
	286	*
	287	* First try CDR2, and if we can't reach the expected
	288	* frequency, fall back to CDR1.
	289	*/
47284e3e	290	div = mclk_rate / (2 * tfr->speed_hz);
3558fe90 MR	291	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
	292	if (div > 0)
	293	div--;
	294
	295	reg = SUN6I_CLK_CTL_CDR2(div) \| SUN6I_CLK_CTL_DRS;
	296	} else {
47284e3e	297	div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
3558fe90 MR	298	reg = SUN6I_CLK_CTL_CDR1(div);
	299	}
	300
	301	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
	302
	303	/* Setup the transfer now... */
	304	if (sspi->tx_buf)
	305	tx_len = tfr->len;
	306
	307	/* Setup the counters */
	308	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
	309	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
	310	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
	311	SUN6I_BURST_CTL_CNT_STC(tx_len));
	312
	313	/* Fill the TX FIFO */
10565dfd	314	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
3558fe90 MR	315
	316	/* Enable the interrupts */
	317	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
913f536c IZ	318	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC \|
	319	SUN6I_INT_CTL_RF_RDY);
	320	if (tx_len > sspi->fifo_depth)
	321	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
3558fe90 MR	322
	323	/* Start the transfer */
	324	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	325	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg \| SUN6I_TFR_CTL_XCH);
	326
719bd654 MS	327	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
719bd654 MS	328	start = jiffies;
3558fe90	329	timeout = wait_for_completion_timeout(&sspi->done,
719bd654 MS	330	msecs_to_jiffies(tx_time));
719bd654 MS	331	end = jiffies;
3558fe90	332	if (!timeout) {
719bd654 MS	333	dev_warn(&master->dev,
	334	"%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
	335	dev_name(&spi->dev), tfr->len, tfr->speed_hz,
	336	jiffies_to_msecs(end - start), tx_time);
3558fe90 MR	337	ret = -ETIMEDOUT;
	338	goto out;
	339	}
	340
3558fe90 MR	341	out:
	342	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
	343
	344	return ret;
	345	}
	346
	347	static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
	348	{
	349	struct sun6i_spi *sspi = dev_id;
	350	u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
	351
	352	/* Transfer complete */
	353	if (status & SUN6I_INT_CTL_TC) {
	354	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
913f536c	355	sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
3558fe90 MR	356	complete(&sspi->done);
	357	return IRQ_HANDLED;
	358	}
	359
913f536c IZ	360	/* Receive FIFO 3/4 full */
	361	if (status & SUN6I_INT_CTL_RF_RDY) {
	362	sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
	363	/* Only clear the interrupt _after_ draining the FIFO */
	364	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
	365	return IRQ_HANDLED;
	366	}
	367
	368	/* Transmit FIFO 3/4 empty */
	369	if (status & SUN6I_INT_CTL_TF_ERQ) {
	370	sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
	371
	372	if (!sspi->len)
	373	/* nothing left to transmit */
	374	sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
	375
	376	/* Only clear the interrupt _after_ re-seeding the FIFO */
	377	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
	378
	379	return IRQ_HANDLED;
	380	}
	381
3558fe90 MR	382	return IRQ_NONE;
	383	}
	384
	385	static int sun6i_spi_runtime_resume(struct device *dev)
	386	{
	387	struct spi_master *master = dev_get_drvdata(dev);
	388	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	389	int ret;
	390
	391	ret = clk_prepare_enable(sspi->hclk);
	392	if (ret) {
	393	dev_err(dev, "Couldn't enable AHB clock\n");
	394	goto out;
	395	}
	396
	397	ret = clk_prepare_enable(sspi->mclk);
	398	if (ret) {
	399	dev_err(dev, "Couldn't enable module clock\n");
	400	goto err;
	401	}
	402
	403	ret = reset_control_deassert(sspi->rstc);
	404	if (ret) {
	405	dev_err(dev, "Couldn't deassert the device from reset\n");
	406	goto err2;
	407	}
	408
	409	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
	410	SUN6I_GBL_CTL_BUS_ENABLE \| SUN6I_GBL_CTL_MASTER \| SUN6I_GBL_CTL_TP);
	411
	412	return 0;
	413
	414	err2:
	415	clk_disable_unprepare(sspi->mclk);
	416	err:
	417	clk_disable_unprepare(sspi->hclk);
	418	out:
	419	return ret;
	420	}
	421
	422	static int sun6i_spi_runtime_suspend(struct device *dev)
	423	{
	424	struct spi_master *master = dev_get_drvdata(dev);
	425	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	426
	427	reset_control_assert(sspi->rstc);
	428	clk_disable_unprepare(sspi->mclk);
	429	clk_disable_unprepare(sspi->hclk);
	430
	431	return 0;
	432	}
	433
	434	static int sun6i_spi_probe(struct platform_device *pdev)
	435	{
	436	struct spi_master *master;
	437	struct sun6i_spi *sspi;
	438	struct resource *res;
	439	int ret = 0, irq;
	440
	441	master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
	442	if (!master) {
	443	dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
	444	return -ENOMEM;
	445	}
446
447	platform_set_drvdata(pdev, master);
448	sspi = spi_master_get_devdata(master);
449
450	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
451	sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
452	if (IS_ERR(sspi->base_addr)) {
453	ret = PTR_ERR(sspi->base_addr);
454	goto err_free_master;
455	}
456
457	irq = platform_get_irq(pdev, 0);
458	if (irq < 0) {
459	dev_err(&pdev->dev, "No spi IRQ specified\n");
460	ret = -ENXIO;
461	goto err_free_master;
462	}
463
464	ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
465	0, "sun6i-spi", sspi);
466	if (ret) {
467	dev_err(&pdev->dev, "Cannot request IRQ\n");
468	goto err_free_master;
469	}
470
471	sspi->master = master;
10565dfd MK	472	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
10565dfd MK	473
0b06d8cf MS	474	master->max_speed_hz = 100 * 1000 * 1000;
0b06d8cf MS	475	master->min_speed_hz = 3 * 1000;
3558fe90 MR	476	master->set_cs = sun6i_spi_set_cs;
	477	master->transfer_one = sun6i_spi_transfer_one;
	478	master->num_chipselect = 4;
	479	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
743a46b8	480	master->bits_per_word_mask = SPI_BPW_MASK(8);
3558fe90 MR	481	master->dev.of_node = pdev->dev.of_node;
3558fe90 MR	482	master->auto_runtime_pm = true;
794912cf	483	master->max_transfer_size = sun6i_spi_max_transfer_size;
3558fe90 MR	484
	485	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
	486	if (IS_ERR(sspi->hclk)) {
	487	dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
	488	ret = PTR_ERR(sspi->hclk);
	489	goto err_free_master;
	490	}
	491
	492	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
	493	if (IS_ERR(sspi->mclk)) {
	494	dev_err(&pdev->dev, "Unable to acquire module clock\n");
	495	ret = PTR_ERR(sspi->mclk);
	496	goto err_free_master;
	497	}
	498
	499	init_completion(&sspi->done);
	500
36bc7491	501	sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
3558fe90 MR	502	if (IS_ERR(sspi->rstc)) {
	503	dev_err(&pdev->dev, "Couldn't get reset controller\n");
	504	ret = PTR_ERR(sspi->rstc);
	505	goto err_free_master;
	506	}
	507
	508	/*
	509	* This wake-up/shutdown pattern is to be able to have the
	510	* device woken up, even if runtime_pm is disabled
	511	*/
	512	ret = sun6i_spi_runtime_resume(&pdev->dev);
	513	if (ret) {
	514	dev_err(&pdev->dev, "Couldn't resume the device\n");
	515	goto err_free_master;
	516	}
	517
	518	pm_runtime_set_active(&pdev->dev);
	519	pm_runtime_enable(&pdev->dev);
	520	pm_runtime_idle(&pdev->dev);
	521
	522	ret = devm_spi_register_master(&pdev->dev, master);
	523	if (ret) {
	524	dev_err(&pdev->dev, "cannot register SPI master\n");
	525	goto err_pm_disable;
	526	}
	527
	528	return 0;
	529
	530	err_pm_disable:
	531	pm_runtime_disable(&pdev->dev);
	532	sun6i_spi_runtime_suspend(&pdev->dev);
	533	err_free_master:
	534	spi_master_put(master);
	535	return ret;
	536	}
	537
	538	static int sun6i_spi_remove(struct platform_device *pdev)
	539	{
2d9bbd02	540	pm_runtime_force_suspend(&pdev->dev);
3558fe90 MR	541
	542	return 0;
	543	}
	544
	545	static const struct of_device_id sun6i_spi_match[] = {
10565dfd MK	546	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
10565dfd MK	547	{ .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
3558fe90 MR	548	{}
	549	};
	550	MODULE_DEVICE_TABLE(of, sun6i_spi_match);
	551
	552	static const struct dev_pm_ops sun6i_spi_pm_ops = {
	553	.runtime_resume = sun6i_spi_runtime_resume,
	554	.runtime_suspend = sun6i_spi_runtime_suspend,
	555	};
	556
	557	static struct platform_driver sun6i_spi_driver = {
	558	.probe = sun6i_spi_probe,
	559	.remove = sun6i_spi_remove,
	560	.driver = {
	561	.name = "sun6i-spi",
3558fe90 MR	562	.of_match_table = sun6i_spi_match,
	563	.pm = &sun6i_spi_pm_ops,
	564	},
	565	};
	566	module_platform_driver(sun6i_spi_driver);
	567
	568	MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
	569	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
	570	MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
	571	MODULE_LICENSE("GPL");