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3558fe90 MR |
1 | /* |
2 | * Copyright (C) 2012 - 2014 Allwinner Tech | |
3 | * Pan Nan <pannan@allwinnertech.com> | |
4 | * | |
5 | * Copyright (C) 2014 Maxime Ripard | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
10565dfd | 20 | #include <linux/of_device.h> |
3558fe90 MR |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/reset.h> | |
3558fe90 MR |
24 | |
25 | #include <linux/spi/spi.h> | |
26 | ||
27 | #define SUN6I_FIFO_DEPTH 128 | |
10565dfd | 28 | #define SUN8I_FIFO_DEPTH 64 |
3558fe90 MR |
29 | |
30 | #define SUN6I_GBL_CTL_REG 0x04 | |
31 | #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) | |
32 | #define SUN6I_GBL_CTL_MASTER BIT(1) | |
33 | #define SUN6I_GBL_CTL_TP BIT(7) | |
34 | #define SUN6I_GBL_CTL_RST BIT(31) | |
35 | ||
36 | #define SUN6I_TFR_CTL_REG 0x08 | |
37 | #define SUN6I_TFR_CTL_CPHA BIT(0) | |
38 | #define SUN6I_TFR_CTL_CPOL BIT(1) | |
39 | #define SUN6I_TFR_CTL_SPOL BIT(2) | |
d31ad46f AL |
40 | #define SUN6I_TFR_CTL_CS_MASK 0x30 |
41 | #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) | |
3558fe90 MR |
42 | #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) |
43 | #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) | |
44 | #define SUN6I_TFR_CTL_DHB BIT(8) | |
45 | #define SUN6I_TFR_CTL_FBS BIT(12) | |
46 | #define SUN6I_TFR_CTL_XCH BIT(31) | |
47 | ||
48 | #define SUN6I_INT_CTL_REG 0x10 | |
49 | #define SUN6I_INT_CTL_RF_OVF BIT(8) | |
50 | #define SUN6I_INT_CTL_TC BIT(12) | |
51 | ||
52 | #define SUN6I_INT_STA_REG 0x14 | |
53 | ||
54 | #define SUN6I_FIFO_CTL_REG 0x18 | |
55 | #define SUN6I_FIFO_CTL_RF_RST BIT(15) | |
56 | #define SUN6I_FIFO_CTL_TF_RST BIT(31) | |
57 | ||
58 | #define SUN6I_FIFO_STA_REG 0x1c | |
59 | #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f | |
60 | #define SUN6I_FIFO_STA_RF_CNT_BITS 0 | |
61 | #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f | |
62 | #define SUN6I_FIFO_STA_TF_CNT_BITS 16 | |
63 | ||
64 | #define SUN6I_CLK_CTL_REG 0x24 | |
65 | #define SUN6I_CLK_CTL_CDR2_MASK 0xff | |
66 | #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) | |
67 | #define SUN6I_CLK_CTL_CDR1_MASK 0xf | |
68 | #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) | |
69 | #define SUN6I_CLK_CTL_DRS BIT(12) | |
70 | ||
71 | #define SUN6I_BURST_CNT_REG 0x30 | |
72 | #define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) | |
73 | ||
74 | #define SUN6I_XMIT_CNT_REG 0x34 | |
75 | #define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) | |
76 | ||
77 | #define SUN6I_BURST_CTL_CNT_REG 0x38 | |
78 | #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) | |
79 | ||
80 | #define SUN6I_TXDATA_REG 0x200 | |
81 | #define SUN6I_RXDATA_REG 0x300 | |
82 | ||
83 | struct sun6i_spi { | |
84 | struct spi_master *master; | |
85 | void __iomem *base_addr; | |
86 | struct clk *hclk; | |
87 | struct clk *mclk; | |
88 | struct reset_control *rstc; | |
89 | ||
90 | struct completion done; | |
91 | ||
92 | const u8 *tx_buf; | |
93 | u8 *rx_buf; | |
94 | int len; | |
10565dfd | 95 | unsigned long fifo_depth; |
3558fe90 MR |
96 | }; |
97 | ||
98 | static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) | |
99 | { | |
100 | return readl(sspi->base_addr + reg); | |
101 | } | |
102 | ||
103 | static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) | |
104 | { | |
105 | writel(value, sspi->base_addr + reg); | |
106 | } | |
107 | ||
108 | static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) | |
109 | { | |
110 | u32 reg, cnt; | |
111 | u8 byte; | |
112 | ||
113 | /* See how much data is available */ | |
114 | reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); | |
115 | reg &= SUN6I_FIFO_STA_RF_CNT_MASK; | |
116 | cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; | |
117 | ||
118 | if (len > cnt) | |
119 | len = cnt; | |
120 | ||
121 | while (len--) { | |
122 | byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); | |
123 | if (sspi->rx_buf) | |
124 | *sspi->rx_buf++ = byte; | |
125 | } | |
126 | } | |
127 | ||
128 | static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) | |
129 | { | |
130 | u8 byte; | |
131 | ||
132 | if (len > sspi->len) | |
133 | len = sspi->len; | |
134 | ||
135 | while (len--) { | |
136 | byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; | |
137 | writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); | |
138 | sspi->len--; | |
139 | } | |
140 | } | |
141 | ||
142 | static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) | |
143 | { | |
144 | struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); | |
145 | u32 reg; | |
146 | ||
147 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
148 | reg &= ~SUN6I_TFR_CTL_CS_MASK; | |
149 | reg |= SUN6I_TFR_CTL_CS(spi->chip_select); | |
150 | ||
151 | if (enable) | |
152 | reg |= SUN6I_TFR_CTL_CS_LEVEL; | |
153 | else | |
154 | reg &= ~SUN6I_TFR_CTL_CS_LEVEL; | |
155 | ||
156 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
157 | } | |
158 | ||
794912cf MS |
159 | static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) |
160 | { | |
10565dfd MK |
161 | struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); |
162 | ||
163 | return sspi->fifo_depth - 1; | |
794912cf | 164 | } |
3558fe90 MR |
165 | |
166 | static int sun6i_spi_transfer_one(struct spi_master *master, | |
167 | struct spi_device *spi, | |
168 | struct spi_transfer *tfr) | |
169 | { | |
170 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
171 | unsigned int mclk_rate, div, timeout; | |
719bd654 | 172 | unsigned int start, end, tx_time; |
3558fe90 MR |
173 | unsigned int tx_len = 0; |
174 | int ret = 0; | |
175 | u32 reg; | |
176 | ||
177 | /* We don't support transfer larger than the FIFO */ | |
10565dfd | 178 | if (tfr->len > sspi->fifo_depth) |
3558fe90 MR |
179 | return -EINVAL; |
180 | ||
181 | reinit_completion(&sspi->done); | |
182 | sspi->tx_buf = tfr->tx_buf; | |
183 | sspi->rx_buf = tfr->rx_buf; | |
184 | sspi->len = tfr->len; | |
185 | ||
186 | /* Clear pending interrupts */ | |
187 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); | |
188 | ||
189 | /* Reset FIFO */ | |
190 | sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, | |
191 | SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); | |
192 | ||
193 | /* | |
194 | * Setup the transfer control register: Chip Select, | |
195 | * polarities, etc. | |
196 | */ | |
197 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
198 | ||
199 | if (spi->mode & SPI_CPOL) | |
200 | reg |= SUN6I_TFR_CTL_CPOL; | |
201 | else | |
202 | reg &= ~SUN6I_TFR_CTL_CPOL; | |
203 | ||
204 | if (spi->mode & SPI_CPHA) | |
205 | reg |= SUN6I_TFR_CTL_CPHA; | |
206 | else | |
207 | reg &= ~SUN6I_TFR_CTL_CPHA; | |
208 | ||
209 | if (spi->mode & SPI_LSB_FIRST) | |
210 | reg |= SUN6I_TFR_CTL_FBS; | |
211 | else | |
212 | reg &= ~SUN6I_TFR_CTL_FBS; | |
213 | ||
214 | /* | |
215 | * If it's a TX only transfer, we don't want to fill the RX | |
216 | * FIFO with bogus data | |
217 | */ | |
218 | if (sspi->rx_buf) | |
219 | reg &= ~SUN6I_TFR_CTL_DHB; | |
220 | else | |
221 | reg |= SUN6I_TFR_CTL_DHB; | |
222 | ||
223 | /* We want to control the chip select manually */ | |
224 | reg |= SUN6I_TFR_CTL_CS_MANUAL; | |
225 | ||
226 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
227 | ||
228 | /* Ensure that we have a parent clock fast enough */ | |
229 | mclk_rate = clk_get_rate(sspi->mclk); | |
47284e3e MW |
230 | if (mclk_rate < (2 * tfr->speed_hz)) { |
231 | clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); | |
3558fe90 MR |
232 | mclk_rate = clk_get_rate(sspi->mclk); |
233 | } | |
234 | ||
235 | /* | |
236 | * Setup clock divider. | |
237 | * | |
238 | * We have two choices there. Either we can use the clock | |
239 | * divide rate 1, which is calculated thanks to this formula: | |
240 | * SPI_CLK = MOD_CLK / (2 ^ cdr) | |
241 | * Or we can use CDR2, which is calculated with the formula: | |
242 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) | |
243 | * Wether we use the former or the latter is set through the | |
244 | * DRS bit. | |
245 | * | |
246 | * First try CDR2, and if we can't reach the expected | |
247 | * frequency, fall back to CDR1. | |
248 | */ | |
47284e3e | 249 | div = mclk_rate / (2 * tfr->speed_hz); |
3558fe90 MR |
250 | if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { |
251 | if (div > 0) | |
252 | div--; | |
253 | ||
254 | reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; | |
255 | } else { | |
47284e3e | 256 | div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); |
3558fe90 MR |
257 | reg = SUN6I_CLK_CTL_CDR1(div); |
258 | } | |
259 | ||
260 | sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); | |
261 | ||
262 | /* Setup the transfer now... */ | |
263 | if (sspi->tx_buf) | |
264 | tx_len = tfr->len; | |
265 | ||
266 | /* Setup the counters */ | |
267 | sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); | |
268 | sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len)); | |
269 | sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, | |
270 | SUN6I_BURST_CTL_CNT_STC(tx_len)); | |
271 | ||
272 | /* Fill the TX FIFO */ | |
10565dfd | 273 | sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); |
3558fe90 MR |
274 | |
275 | /* Enable the interrupts */ | |
276 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); | |
277 | ||
278 | /* Start the transfer */ | |
279 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
280 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); | |
281 | ||
719bd654 MS |
282 | tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); |
283 | start = jiffies; | |
3558fe90 | 284 | timeout = wait_for_completion_timeout(&sspi->done, |
719bd654 MS |
285 | msecs_to_jiffies(tx_time)); |
286 | end = jiffies; | |
3558fe90 | 287 | if (!timeout) { |
719bd654 MS |
288 | dev_warn(&master->dev, |
289 | "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", | |
290 | dev_name(&spi->dev), tfr->len, tfr->speed_hz, | |
291 | jiffies_to_msecs(end - start), tx_time); | |
3558fe90 MR |
292 | ret = -ETIMEDOUT; |
293 | goto out; | |
294 | } | |
295 | ||
10565dfd | 296 | sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); |
3558fe90 MR |
297 | |
298 | out: | |
299 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); | |
300 | ||
301 | return ret; | |
302 | } | |
303 | ||
304 | static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) | |
305 | { | |
306 | struct sun6i_spi *sspi = dev_id; | |
307 | u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); | |
308 | ||
309 | /* Transfer complete */ | |
310 | if (status & SUN6I_INT_CTL_TC) { | |
311 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); | |
312 | complete(&sspi->done); | |
313 | return IRQ_HANDLED; | |
314 | } | |
315 | ||
316 | return IRQ_NONE; | |
317 | } | |
318 | ||
319 | static int sun6i_spi_runtime_resume(struct device *dev) | |
320 | { | |
321 | struct spi_master *master = dev_get_drvdata(dev); | |
322 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
323 | int ret; | |
324 | ||
325 | ret = clk_prepare_enable(sspi->hclk); | |
326 | if (ret) { | |
327 | dev_err(dev, "Couldn't enable AHB clock\n"); | |
328 | goto out; | |
329 | } | |
330 | ||
331 | ret = clk_prepare_enable(sspi->mclk); | |
332 | if (ret) { | |
333 | dev_err(dev, "Couldn't enable module clock\n"); | |
334 | goto err; | |
335 | } | |
336 | ||
337 | ret = reset_control_deassert(sspi->rstc); | |
338 | if (ret) { | |
339 | dev_err(dev, "Couldn't deassert the device from reset\n"); | |
340 | goto err2; | |
341 | } | |
342 | ||
343 | sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, | |
344 | SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); | |
345 | ||
346 | return 0; | |
347 | ||
348 | err2: | |
349 | clk_disable_unprepare(sspi->mclk); | |
350 | err: | |
351 | clk_disable_unprepare(sspi->hclk); | |
352 | out: | |
353 | return ret; | |
354 | } | |
355 | ||
356 | static int sun6i_spi_runtime_suspend(struct device *dev) | |
357 | { | |
358 | struct spi_master *master = dev_get_drvdata(dev); | |
359 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
360 | ||
361 | reset_control_assert(sspi->rstc); | |
362 | clk_disable_unprepare(sspi->mclk); | |
363 | clk_disable_unprepare(sspi->hclk); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static int sun6i_spi_probe(struct platform_device *pdev) | |
369 | { | |
370 | struct spi_master *master; | |
371 | struct sun6i_spi *sspi; | |
372 | struct resource *res; | |
373 | int ret = 0, irq; | |
374 | ||
375 | master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); | |
376 | if (!master) { | |
377 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
378 | return -ENOMEM; | |
379 | } | |
380 | ||
381 | platform_set_drvdata(pdev, master); | |
382 | sspi = spi_master_get_devdata(master); | |
383 | ||
384 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
385 | sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); | |
386 | if (IS_ERR(sspi->base_addr)) { | |
387 | ret = PTR_ERR(sspi->base_addr); | |
388 | goto err_free_master; | |
389 | } | |
390 | ||
391 | irq = platform_get_irq(pdev, 0); | |
392 | if (irq < 0) { | |
393 | dev_err(&pdev->dev, "No spi IRQ specified\n"); | |
394 | ret = -ENXIO; | |
395 | goto err_free_master; | |
396 | } | |
397 | ||
398 | ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, | |
399 | 0, "sun6i-spi", sspi); | |
400 | if (ret) { | |
401 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
402 | goto err_free_master; | |
403 | } | |
404 | ||
405 | sspi->master = master; | |
10565dfd MK |
406 | sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); |
407 | ||
0b06d8cf MS |
408 | master->max_speed_hz = 100 * 1000 * 1000; |
409 | master->min_speed_hz = 3 * 1000; | |
3558fe90 MR |
410 | master->set_cs = sun6i_spi_set_cs; |
411 | master->transfer_one = sun6i_spi_transfer_one; | |
412 | master->num_chipselect = 4; | |
413 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | |
743a46b8 | 414 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
3558fe90 MR |
415 | master->dev.of_node = pdev->dev.of_node; |
416 | master->auto_runtime_pm = true; | |
794912cf | 417 | master->max_transfer_size = sun6i_spi_max_transfer_size; |
3558fe90 MR |
418 | |
419 | sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); | |
420 | if (IS_ERR(sspi->hclk)) { | |
421 | dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); | |
422 | ret = PTR_ERR(sspi->hclk); | |
423 | goto err_free_master; | |
424 | } | |
425 | ||
426 | sspi->mclk = devm_clk_get(&pdev->dev, "mod"); | |
427 | if (IS_ERR(sspi->mclk)) { | |
428 | dev_err(&pdev->dev, "Unable to acquire module clock\n"); | |
429 | ret = PTR_ERR(sspi->mclk); | |
430 | goto err_free_master; | |
431 | } | |
432 | ||
433 | init_completion(&sspi->done); | |
434 | ||
435 | sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); | |
436 | if (IS_ERR(sspi->rstc)) { | |
437 | dev_err(&pdev->dev, "Couldn't get reset controller\n"); | |
438 | ret = PTR_ERR(sspi->rstc); | |
439 | goto err_free_master; | |
440 | } | |
441 | ||
442 | /* | |
443 | * This wake-up/shutdown pattern is to be able to have the | |
444 | * device woken up, even if runtime_pm is disabled | |
445 | */ | |
446 | ret = sun6i_spi_runtime_resume(&pdev->dev); | |
447 | if (ret) { | |
448 | dev_err(&pdev->dev, "Couldn't resume the device\n"); | |
449 | goto err_free_master; | |
450 | } | |
451 | ||
452 | pm_runtime_set_active(&pdev->dev); | |
453 | pm_runtime_enable(&pdev->dev); | |
454 | pm_runtime_idle(&pdev->dev); | |
455 | ||
456 | ret = devm_spi_register_master(&pdev->dev, master); | |
457 | if (ret) { | |
458 | dev_err(&pdev->dev, "cannot register SPI master\n"); | |
459 | goto err_pm_disable; | |
460 | } | |
461 | ||
462 | return 0; | |
463 | ||
464 | err_pm_disable: | |
465 | pm_runtime_disable(&pdev->dev); | |
466 | sun6i_spi_runtime_suspend(&pdev->dev); | |
467 | err_free_master: | |
468 | spi_master_put(master); | |
469 | return ret; | |
470 | } | |
471 | ||
472 | static int sun6i_spi_remove(struct platform_device *pdev) | |
473 | { | |
474 | pm_runtime_disable(&pdev->dev); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static const struct of_device_id sun6i_spi_match[] = { | |
10565dfd MK |
480 | { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, |
481 | { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, | |
3558fe90 MR |
482 | {} |
483 | }; | |
484 | MODULE_DEVICE_TABLE(of, sun6i_spi_match); | |
485 | ||
486 | static const struct dev_pm_ops sun6i_spi_pm_ops = { | |
487 | .runtime_resume = sun6i_spi_runtime_resume, | |
488 | .runtime_suspend = sun6i_spi_runtime_suspend, | |
489 | }; | |
490 | ||
491 | static struct platform_driver sun6i_spi_driver = { | |
492 | .probe = sun6i_spi_probe, | |
493 | .remove = sun6i_spi_remove, | |
494 | .driver = { | |
495 | .name = "sun6i-spi", | |
3558fe90 MR |
496 | .of_match_table = sun6i_spi_match, |
497 | .pm = &sun6i_spi_pm_ops, | |
498 | }, | |
499 | }; | |
500 | module_platform_driver(sun6i_spi_driver); | |
501 | ||
502 | MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); | |
503 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
504 | MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); | |
505 | MODULE_LICENSE("GPL"); |