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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3558fe90 MR |
2 | /* |
3 | * Copyright (C) 2012 - 2014 Allwinner Tech | |
4 | * Pan Nan <pannan@allwinnertech.com> | |
5 | * | |
6 | * Copyright (C) 2014 Maxime Ripard | |
7 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
3558fe90 MR |
8 | */ |
9 | ||
9a3ef9df | 10 | #include <linux/bitfield.h> |
3558fe90 MR |
11 | #include <linux/clk.h> |
12 | #include <linux/delay.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
10565dfd | 17 | #include <linux/of_device.h> |
3558fe90 MR |
18 | #include <linux/platform_device.h> |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/reset.h> | |
345980a3 | 21 | #include <linux/dmaengine.h> |
3558fe90 MR |
22 | |
23 | #include <linux/spi/spi.h> | |
24 | ||
ae0f18be AK |
25 | #define SUN6I_AUTOSUSPEND_TIMEOUT 2000 |
26 | ||
3558fe90 | 27 | #define SUN6I_FIFO_DEPTH 128 |
10565dfd | 28 | #define SUN8I_FIFO_DEPTH 64 |
3558fe90 MR |
29 | |
30 | #define SUN6I_GBL_CTL_REG 0x04 | |
31 | #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) | |
32 | #define SUN6I_GBL_CTL_MASTER BIT(1) | |
33 | #define SUN6I_GBL_CTL_TP BIT(7) | |
34 | #define SUN6I_GBL_CTL_RST BIT(31) | |
35 | ||
36 | #define SUN6I_TFR_CTL_REG 0x08 | |
37 | #define SUN6I_TFR_CTL_CPHA BIT(0) | |
38 | #define SUN6I_TFR_CTL_CPOL BIT(1) | |
39 | #define SUN6I_TFR_CTL_SPOL BIT(2) | |
d31ad46f AL |
40 | #define SUN6I_TFR_CTL_CS_MASK 0x30 |
41 | #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) | |
3558fe90 MR |
42 | #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) |
43 | #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) | |
44 | #define SUN6I_TFR_CTL_DHB BIT(8) | |
45 | #define SUN6I_TFR_CTL_FBS BIT(12) | |
46 | #define SUN6I_TFR_CTL_XCH BIT(31) | |
47 | ||
48 | #define SUN6I_INT_CTL_REG 0x10 | |
913f536c IZ |
49 | #define SUN6I_INT_CTL_RF_RDY BIT(0) |
50 | #define SUN6I_INT_CTL_TF_ERQ BIT(4) | |
3558fe90 MR |
51 | #define SUN6I_INT_CTL_RF_OVF BIT(8) |
52 | #define SUN6I_INT_CTL_TC BIT(12) | |
53 | ||
54 | #define SUN6I_INT_STA_REG 0x14 | |
55 | ||
56 | #define SUN6I_FIFO_CTL_REG 0x18 | |
913f536c | 57 | #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff |
345980a3 | 58 | #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8) |
913f536c | 59 | #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 |
3558fe90 | 60 | #define SUN6I_FIFO_CTL_RF_RST BIT(15) |
913f536c IZ |
61 | #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff |
62 | #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 | |
345980a3 | 63 | #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24) |
3558fe90 MR |
64 | #define SUN6I_FIFO_CTL_TF_RST BIT(31) |
65 | ||
66 | #define SUN6I_FIFO_STA_REG 0x1c | |
5197da03 | 67 | #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) |
9a3ef9df | 68 | #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) |
3558fe90 MR |
69 | |
70 | #define SUN6I_CLK_CTL_REG 0x24 | |
71 | #define SUN6I_CLK_CTL_CDR2_MASK 0xff | |
72 | #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) | |
73 | #define SUN6I_CLK_CTL_CDR1_MASK 0xf | |
74 | #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) | |
75 | #define SUN6I_CLK_CTL_DRS BIT(12) | |
76 | ||
913f536c IZ |
77 | #define SUN6I_MAX_XFER_SIZE 0xffffff |
78 | ||
3558fe90 | 79 | #define SUN6I_BURST_CNT_REG 0x30 |
3558fe90 MR |
80 | |
81 | #define SUN6I_XMIT_CNT_REG 0x34 | |
3558fe90 MR |
82 | |
83 | #define SUN6I_BURST_CTL_CNT_REG 0x38 | |
3558fe90 MR |
84 | |
85 | #define SUN6I_TXDATA_REG 0x200 | |
86 | #define SUN6I_RXDATA_REG 0x300 | |
87 | ||
88 | struct sun6i_spi { | |
89 | struct spi_master *master; | |
90 | void __iomem *base_addr; | |
345980a3 AK |
91 | dma_addr_t dma_addr_rx; |
92 | dma_addr_t dma_addr_tx; | |
3558fe90 MR |
93 | struct clk *hclk; |
94 | struct clk *mclk; | |
95 | struct reset_control *rstc; | |
96 | ||
97 | struct completion done; | |
98 | ||
99 | const u8 *tx_buf; | |
100 | u8 *rx_buf; | |
101 | int len; | |
10565dfd | 102 | unsigned long fifo_depth; |
3558fe90 MR |
103 | }; |
104 | ||
105 | static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) | |
106 | { | |
107 | return readl(sspi->base_addr + reg); | |
108 | } | |
109 | ||
110 | static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) | |
111 | { | |
112 | writel(value, sspi->base_addr + reg); | |
113 | } | |
114 | ||
5197da03 MKB |
115 | static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) |
116 | { | |
117 | u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); | |
118 | ||
119 | return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); | |
120 | } | |
121 | ||
913f536c IZ |
122 | static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) |
123 | { | |
124 | u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); | |
125 | ||
9a3ef9df | 126 | return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); |
913f536c IZ |
127 | } |
128 | ||
913f536c IZ |
129 | static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) |
130 | { | |
131 | u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); | |
132 | ||
133 | reg &= ~mask; | |
134 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); | |
135 | } | |
136 | ||
92a52ee8 | 137 | static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi) |
3558fe90 | 138 | { |
92a52ee8 | 139 | u32 len; |
3558fe90 MR |
140 | u8 byte; |
141 | ||
142 | /* See how much data is available */ | |
92a52ee8 | 143 | len = sun6i_spi_get_rx_fifo_count(sspi); |
3558fe90 MR |
144 | |
145 | while (len--) { | |
146 | byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); | |
147 | if (sspi->rx_buf) | |
148 | *sspi->rx_buf++ = byte; | |
149 | } | |
150 | } | |
151 | ||
e4e8ca3f | 152 | static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) |
3558fe90 | 153 | { |
913f536c | 154 | u32 cnt; |
e4e8ca3f | 155 | int len; |
3558fe90 MR |
156 | u8 byte; |
157 | ||
913f536c IZ |
158 | /* See how much data we can fit */ |
159 | cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); | |
160 | ||
e4e8ca3f | 161 | len = min((int)cnt, sspi->len); |
3558fe90 MR |
162 | |
163 | while (len--) { | |
164 | byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; | |
165 | writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); | |
166 | sspi->len--; | |
167 | } | |
168 | } | |
169 | ||
170 | static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) | |
171 | { | |
172 | struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); | |
173 | u32 reg; | |
174 | ||
175 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
176 | reg &= ~SUN6I_TFR_CTL_CS_MASK; | |
177 | reg |= SUN6I_TFR_CTL_CS(spi->chip_select); | |
178 | ||
179 | if (enable) | |
180 | reg |= SUN6I_TFR_CTL_CS_LEVEL; | |
181 | else | |
182 | reg &= ~SUN6I_TFR_CTL_CS_LEVEL; | |
183 | ||
184 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
185 | } | |
186 | ||
794912cf MS |
187 | static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) |
188 | { | |
3288d5cb | 189 | return SUN6I_MAX_XFER_SIZE - 1; |
794912cf | 190 | } |
3558fe90 | 191 | |
345980a3 AK |
192 | static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi, |
193 | struct spi_transfer *tfr) | |
194 | { | |
195 | struct dma_async_tx_descriptor *rxdesc, *txdesc; | |
196 | struct spi_master *master = sspi->master; | |
197 | ||
198 | rxdesc = NULL; | |
199 | if (tfr->rx_buf) { | |
200 | struct dma_slave_config rxconf = { | |
201 | .direction = DMA_DEV_TO_MEM, | |
202 | .src_addr = sspi->dma_addr_rx, | |
203 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
204 | .src_maxburst = 8, | |
205 | }; | |
206 | ||
207 | dmaengine_slave_config(master->dma_rx, &rxconf); | |
208 | ||
209 | rxdesc = dmaengine_prep_slave_sg(master->dma_rx, | |
210 | tfr->rx_sg.sgl, | |
211 | tfr->rx_sg.nents, | |
212 | DMA_DEV_TO_MEM, | |
213 | DMA_PREP_INTERRUPT); | |
214 | if (!rxdesc) | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | txdesc = NULL; | |
219 | if (tfr->tx_buf) { | |
220 | struct dma_slave_config txconf = { | |
221 | .direction = DMA_MEM_TO_DEV, | |
222 | .dst_addr = sspi->dma_addr_tx, | |
223 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
224 | .dst_maxburst = 8, | |
225 | }; | |
226 | ||
227 | dmaengine_slave_config(master->dma_tx, &txconf); | |
228 | ||
229 | txdesc = dmaengine_prep_slave_sg(master->dma_tx, | |
230 | tfr->tx_sg.sgl, | |
231 | tfr->tx_sg.nents, | |
232 | DMA_MEM_TO_DEV, | |
233 | DMA_PREP_INTERRUPT); | |
234 | if (!txdesc) { | |
235 | if (rxdesc) | |
236 | dmaengine_terminate_sync(master->dma_rx); | |
237 | return -EINVAL; | |
238 | } | |
239 | } | |
240 | ||
241 | if (tfr->rx_buf) { | |
242 | dmaengine_submit(rxdesc); | |
243 | dma_async_issue_pending(master->dma_rx); | |
244 | } | |
245 | ||
246 | if (tfr->tx_buf) { | |
247 | dmaengine_submit(txdesc); | |
248 | dma_async_issue_pending(master->dma_tx); | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
3558fe90 MR |
254 | static int sun6i_spi_transfer_one(struct spi_master *master, |
255 | struct spi_device *spi, | |
256 | struct spi_transfer *tfr) | |
257 | { | |
258 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
ed7815db | 259 | unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; |
719bd654 | 260 | unsigned int start, end, tx_time; |
913f536c | 261 | unsigned int trig_level; |
7716fa80 | 262 | unsigned int tx_len = 0, rx_len = 0; |
345980a3 | 263 | bool use_dma; |
3558fe90 MR |
264 | int ret = 0; |
265 | u32 reg; | |
266 | ||
913f536c | 267 | if (tfr->len > SUN6I_MAX_XFER_SIZE) |
3558fe90 MR |
268 | return -EINVAL; |
269 | ||
270 | reinit_completion(&sspi->done); | |
271 | sspi->tx_buf = tfr->tx_buf; | |
272 | sspi->rx_buf = tfr->rx_buf; | |
273 | sspi->len = tfr->len; | |
345980a3 | 274 | use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; |
3558fe90 MR |
275 | |
276 | /* Clear pending interrupts */ | |
277 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); | |
278 | ||
279 | /* Reset FIFO */ | |
280 | sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, | |
281 | SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); | |
282 | ||
345980a3 AK |
283 | reg = 0; |
284 | ||
285 | if (!use_dma) { | |
286 | /* | |
287 | * Setup FIFO interrupt trigger level | |
288 | * Here we choose 3/4 of the full fifo depth, as it's | |
289 | * the hardcoded value used in old generation of Allwinner | |
290 | * SPI controller. (See spi-sun4i.c) | |
291 | */ | |
292 | trig_level = sspi->fifo_depth / 4 * 3; | |
293 | } else { | |
294 | /* | |
295 | * Setup FIFO DMA request trigger level | |
296 | * We choose 1/2 of the full fifo depth, that value will | |
297 | * be used as DMA burst length. | |
298 | */ | |
299 | trig_level = sspi->fifo_depth / 2; | |
300 | ||
301 | if (tfr->tx_buf) | |
302 | reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; | |
303 | if (tfr->rx_buf) | |
304 | reg |= SUN6I_FIFO_CTL_RF_DRQ_EN; | |
305 | } | |
306 | ||
307 | reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | | |
308 | (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS); | |
309 | ||
310 | sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); | |
913f536c | 311 | |
3558fe90 MR |
312 | /* |
313 | * Setup the transfer control register: Chip Select, | |
314 | * polarities, etc. | |
315 | */ | |
316 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
317 | ||
318 | if (spi->mode & SPI_CPOL) | |
319 | reg |= SUN6I_TFR_CTL_CPOL; | |
320 | else | |
321 | reg &= ~SUN6I_TFR_CTL_CPOL; | |
322 | ||
323 | if (spi->mode & SPI_CPHA) | |
324 | reg |= SUN6I_TFR_CTL_CPHA; | |
325 | else | |
326 | reg &= ~SUN6I_TFR_CTL_CPHA; | |
327 | ||
328 | if (spi->mode & SPI_LSB_FIRST) | |
329 | reg |= SUN6I_TFR_CTL_FBS; | |
330 | else | |
331 | reg &= ~SUN6I_TFR_CTL_FBS; | |
332 | ||
333 | /* | |
334 | * If it's a TX only transfer, we don't want to fill the RX | |
335 | * FIFO with bogus data | |
336 | */ | |
7716fa80 | 337 | if (sspi->rx_buf) { |
3558fe90 | 338 | reg &= ~SUN6I_TFR_CTL_DHB; |
7716fa80 MKB |
339 | rx_len = tfr->len; |
340 | } else { | |
3558fe90 | 341 | reg |= SUN6I_TFR_CTL_DHB; |
7716fa80 | 342 | } |
3558fe90 MR |
343 | |
344 | /* We want to control the chip select manually */ | |
345 | reg |= SUN6I_TFR_CTL_CS_MANUAL; | |
346 | ||
347 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
348 | ||
349 | /* Ensure that we have a parent clock fast enough */ | |
350 | mclk_rate = clk_get_rate(sspi->mclk); | |
47284e3e MW |
351 | if (mclk_rate < (2 * tfr->speed_hz)) { |
352 | clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); | |
3558fe90 MR |
353 | mclk_rate = clk_get_rate(sspi->mclk); |
354 | } | |
355 | ||
356 | /* | |
357 | * Setup clock divider. | |
358 | * | |
359 | * We have two choices there. Either we can use the clock | |
360 | * divide rate 1, which is calculated thanks to this formula: | |
361 | * SPI_CLK = MOD_CLK / (2 ^ cdr) | |
362 | * Or we can use CDR2, which is calculated with the formula: | |
363 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) | |
364 | * Wether we use the former or the latter is set through the | |
365 | * DRS bit. | |
366 | * | |
367 | * First try CDR2, and if we can't reach the expected | |
368 | * frequency, fall back to CDR1. | |
369 | */ | |
ed7815db MKB |
370 | div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); |
371 | div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); | |
372 | if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { | |
373 | reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; | |
0bc7b8a2 | 374 | tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); |
3558fe90 | 375 | } else { |
ed7815db | 376 | div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); |
3558fe90 | 377 | reg = SUN6I_CLK_CTL_CDR1(div); |
0bc7b8a2 | 378 | tfr->effective_speed_hz = mclk_rate / (1 << div); |
3558fe90 MR |
379 | } |
380 | ||
381 | sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); | |
382 | ||
383 | /* Setup the transfer now... */ | |
384 | if (sspi->tx_buf) | |
385 | tx_len = tfr->len; | |
386 | ||
387 | /* Setup the counters */ | |
2130be57 MKB |
388 | sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); |
389 | sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); | |
390 | sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); | |
3558fe90 | 391 | |
345980a3 AK |
392 | if (!use_dma) { |
393 | /* Fill the TX FIFO */ | |
394 | sun6i_spi_fill_fifo(sspi); | |
395 | } else { | |
396 | ret = sun6i_spi_prepare_dma(sspi, tfr); | |
397 | if (ret) { | |
398 | dev_warn(&master->dev, | |
399 | "%s: prepare DMA failed, ret=%d", | |
400 | dev_name(&spi->dev), ret); | |
401 | return ret; | |
402 | } | |
403 | } | |
3558fe90 MR |
404 | |
405 | /* Enable the interrupts */ | |
7716fa80 | 406 | reg = SUN6I_INT_CTL_TC; |
4e7390e9 | 407 | |
345980a3 AK |
408 | if (!use_dma) { |
409 | if (rx_len > sspi->fifo_depth) | |
410 | reg |= SUN6I_INT_CTL_RF_RDY; | |
411 | if (tx_len > sspi->fifo_depth) | |
412 | reg |= SUN6I_INT_CTL_TF_ERQ; | |
413 | } | |
4e7390e9 MKB |
414 | |
415 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); | |
3558fe90 MR |
416 | |
417 | /* Start the transfer */ | |
418 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
419 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); | |
420 | ||
719bd654 MS |
421 | tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); |
422 | start = jiffies; | |
3558fe90 | 423 | timeout = wait_for_completion_timeout(&sspi->done, |
719bd654 MS |
424 | msecs_to_jiffies(tx_time)); |
425 | end = jiffies; | |
3558fe90 | 426 | if (!timeout) { |
719bd654 MS |
427 | dev_warn(&master->dev, |
428 | "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", | |
429 | dev_name(&spi->dev), tfr->len, tfr->speed_hz, | |
430 | jiffies_to_msecs(end - start), tx_time); | |
3558fe90 | 431 | ret = -ETIMEDOUT; |
3558fe90 MR |
432 | } |
433 | ||
3558fe90 MR |
434 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); |
435 | ||
345980a3 AK |
436 | if (ret && use_dma) { |
437 | dmaengine_terminate_sync(master->dma_rx); | |
438 | dmaengine_terminate_sync(master->dma_tx); | |
439 | } | |
440 | ||
3558fe90 MR |
441 | return ret; |
442 | } | |
443 | ||
444 | static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) | |
445 | { | |
446 | struct sun6i_spi *sspi = dev_id; | |
447 | u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); | |
448 | ||
449 | /* Transfer complete */ | |
450 | if (status & SUN6I_INT_CTL_TC) { | |
451 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); | |
92a52ee8 | 452 | sun6i_spi_drain_fifo(sspi); |
3558fe90 MR |
453 | complete(&sspi->done); |
454 | return IRQ_HANDLED; | |
455 | } | |
456 | ||
913f536c IZ |
457 | /* Receive FIFO 3/4 full */ |
458 | if (status & SUN6I_INT_CTL_RF_RDY) { | |
92a52ee8 | 459 | sun6i_spi_drain_fifo(sspi); |
913f536c IZ |
460 | /* Only clear the interrupt _after_ draining the FIFO */ |
461 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); | |
462 | return IRQ_HANDLED; | |
463 | } | |
464 | ||
465 | /* Transmit FIFO 3/4 empty */ | |
466 | if (status & SUN6I_INT_CTL_TF_ERQ) { | |
e4e8ca3f | 467 | sun6i_spi_fill_fifo(sspi); |
913f536c IZ |
468 | |
469 | if (!sspi->len) | |
470 | /* nothing left to transmit */ | |
471 | sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); | |
472 | ||
473 | /* Only clear the interrupt _after_ re-seeding the FIFO */ | |
474 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); | |
475 | ||
476 | return IRQ_HANDLED; | |
477 | } | |
478 | ||
3558fe90 MR |
479 | return IRQ_NONE; |
480 | } | |
481 | ||
482 | static int sun6i_spi_runtime_resume(struct device *dev) | |
483 | { | |
484 | struct spi_master *master = dev_get_drvdata(dev); | |
485 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
486 | int ret; | |
487 | ||
488 | ret = clk_prepare_enable(sspi->hclk); | |
489 | if (ret) { | |
490 | dev_err(dev, "Couldn't enable AHB clock\n"); | |
491 | goto out; | |
492 | } | |
493 | ||
494 | ret = clk_prepare_enable(sspi->mclk); | |
495 | if (ret) { | |
496 | dev_err(dev, "Couldn't enable module clock\n"); | |
497 | goto err; | |
498 | } | |
499 | ||
500 | ret = reset_control_deassert(sspi->rstc); | |
501 | if (ret) { | |
502 | dev_err(dev, "Couldn't deassert the device from reset\n"); | |
503 | goto err2; | |
504 | } | |
505 | ||
506 | sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, | |
507 | SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); | |
508 | ||
509 | return 0; | |
510 | ||
511 | err2: | |
512 | clk_disable_unprepare(sspi->mclk); | |
513 | err: | |
514 | clk_disable_unprepare(sspi->hclk); | |
515 | out: | |
516 | return ret; | |
517 | } | |
518 | ||
519 | static int sun6i_spi_runtime_suspend(struct device *dev) | |
520 | { | |
521 | struct spi_master *master = dev_get_drvdata(dev); | |
522 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
523 | ||
524 | reset_control_assert(sspi->rstc); | |
525 | clk_disable_unprepare(sspi->mclk); | |
526 | clk_disable_unprepare(sspi->hclk); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
345980a3 AK |
531 | static bool sun6i_spi_can_dma(struct spi_master *master, |
532 | struct spi_device *spi, | |
533 | struct spi_transfer *xfer) | |
534 | { | |
535 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
536 | ||
537 | /* | |
538 | * If the number of spi words to transfer is less or equal than | |
539 | * the fifo length we can just fill the fifo and wait for a single | |
540 | * irq, so don't bother setting up dma | |
541 | */ | |
542 | return xfer->len > sspi->fifo_depth; | |
543 | } | |
544 | ||
3558fe90 MR |
545 | static int sun6i_spi_probe(struct platform_device *pdev) |
546 | { | |
547 | struct spi_master *master; | |
548 | struct sun6i_spi *sspi; | |
345980a3 | 549 | struct resource *mem; |
3558fe90 MR |
550 | int ret = 0, irq; |
551 | ||
552 | master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); | |
553 | if (!master) { | |
554 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
555 | return -ENOMEM; | |
556 | } | |
557 | ||
558 | platform_set_drvdata(pdev, master); | |
559 | sspi = spi_master_get_devdata(master); | |
560 | ||
345980a3 | 561 | sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); |
3558fe90 MR |
562 | if (IS_ERR(sspi->base_addr)) { |
563 | ret = PTR_ERR(sspi->base_addr); | |
564 | goto err_free_master; | |
565 | } | |
566 | ||
567 | irq = platform_get_irq(pdev, 0); | |
568 | if (irq < 0) { | |
3558fe90 MR |
569 | ret = -ENXIO; |
570 | goto err_free_master; | |
571 | } | |
572 | ||
573 | ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, | |
574 | 0, "sun6i-spi", sspi); | |
575 | if (ret) { | |
576 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
577 | goto err_free_master; | |
578 | } | |
579 | ||
580 | sspi->master = master; | |
10565dfd MK |
581 | sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); |
582 | ||
0b06d8cf MS |
583 | master->max_speed_hz = 100 * 1000 * 1000; |
584 | master->min_speed_hz = 3 * 1000; | |
74750e06 | 585 | master->use_gpio_descriptors = true; |
3558fe90 MR |
586 | master->set_cs = sun6i_spi_set_cs; |
587 | master->transfer_one = sun6i_spi_transfer_one; | |
588 | master->num_chipselect = 4; | |
589 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | |
743a46b8 | 590 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
3558fe90 MR |
591 | master->dev.of_node = pdev->dev.of_node; |
592 | master->auto_runtime_pm = true; | |
794912cf | 593 | master->max_transfer_size = sun6i_spi_max_transfer_size; |
3558fe90 MR |
594 | |
595 | sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); | |
596 | if (IS_ERR(sspi->hclk)) { | |
597 | dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); | |
598 | ret = PTR_ERR(sspi->hclk); | |
599 | goto err_free_master; | |
600 | } | |
601 | ||
602 | sspi->mclk = devm_clk_get(&pdev->dev, "mod"); | |
603 | if (IS_ERR(sspi->mclk)) { | |
604 | dev_err(&pdev->dev, "Unable to acquire module clock\n"); | |
605 | ret = PTR_ERR(sspi->mclk); | |
606 | goto err_free_master; | |
607 | } | |
608 | ||
609 | init_completion(&sspi->done); | |
610 | ||
36bc7491 | 611 | sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
3558fe90 MR |
612 | if (IS_ERR(sspi->rstc)) { |
613 | dev_err(&pdev->dev, "Couldn't get reset controller\n"); | |
614 | ret = PTR_ERR(sspi->rstc); | |
615 | goto err_free_master; | |
616 | } | |
617 | ||
345980a3 AK |
618 | master->dma_tx = dma_request_chan(&pdev->dev, "tx"); |
619 | if (IS_ERR(master->dma_tx)) { | |
620 | /* Check tx to see if we need defer probing driver */ | |
621 | if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { | |
622 | ret = -EPROBE_DEFER; | |
623 | goto err_free_master; | |
624 | } | |
625 | dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); | |
626 | master->dma_tx = NULL; | |
627 | } | |
628 | ||
629 | master->dma_rx = dma_request_chan(&pdev->dev, "rx"); | |
630 | if (IS_ERR(master->dma_rx)) { | |
631 | if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { | |
632 | ret = -EPROBE_DEFER; | |
633 | goto err_free_dma_tx; | |
634 | } | |
635 | dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); | |
636 | master->dma_rx = NULL; | |
637 | } | |
638 | ||
639 | if (master->dma_tx && master->dma_rx) { | |
640 | sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; | |
641 | sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; | |
642 | master->can_dma = sun6i_spi_can_dma; | |
643 | } | |
644 | ||
3558fe90 MR |
645 | /* |
646 | * This wake-up/shutdown pattern is to be able to have the | |
647 | * device woken up, even if runtime_pm is disabled | |
648 | */ | |
649 | ret = sun6i_spi_runtime_resume(&pdev->dev); | |
650 | if (ret) { | |
651 | dev_err(&pdev->dev, "Couldn't resume the device\n"); | |
345980a3 | 652 | goto err_free_dma_rx; |
3558fe90 MR |
653 | } |
654 | ||
ae0f18be AK |
655 | pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); |
656 | pm_runtime_use_autosuspend(&pdev->dev); | |
3558fe90 MR |
657 | pm_runtime_set_active(&pdev->dev); |
658 | pm_runtime_enable(&pdev->dev); | |
3558fe90 MR |
659 | |
660 | ret = devm_spi_register_master(&pdev->dev, master); | |
661 | if (ret) { | |
662 | dev_err(&pdev->dev, "cannot register SPI master\n"); | |
663 | goto err_pm_disable; | |
664 | } | |
665 | ||
666 | return 0; | |
667 | ||
668 | err_pm_disable: | |
669 | pm_runtime_disable(&pdev->dev); | |
670 | sun6i_spi_runtime_suspend(&pdev->dev); | |
345980a3 AK |
671 | err_free_dma_rx: |
672 | if (master->dma_rx) | |
673 | dma_release_channel(master->dma_rx); | |
674 | err_free_dma_tx: | |
675 | if (master->dma_tx) | |
676 | dma_release_channel(master->dma_tx); | |
3558fe90 MR |
677 | err_free_master: |
678 | spi_master_put(master); | |
679 | return ret; | |
680 | } | |
681 | ||
682 | static int sun6i_spi_remove(struct platform_device *pdev) | |
683 | { | |
345980a3 AK |
684 | struct spi_master *master = platform_get_drvdata(pdev); |
685 | ||
2d9bbd02 | 686 | pm_runtime_force_suspend(&pdev->dev); |
3558fe90 | 687 | |
345980a3 AK |
688 | if (master->dma_tx) |
689 | dma_release_channel(master->dma_tx); | |
690 | if (master->dma_rx) | |
691 | dma_release_channel(master->dma_rx); | |
3558fe90 MR |
692 | return 0; |
693 | } | |
694 | ||
695 | static const struct of_device_id sun6i_spi_match[] = { | |
10565dfd MK |
696 | { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, |
697 | { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, | |
3558fe90 MR |
698 | {} |
699 | }; | |
700 | MODULE_DEVICE_TABLE(of, sun6i_spi_match); | |
701 | ||
702 | static const struct dev_pm_ops sun6i_spi_pm_ops = { | |
703 | .runtime_resume = sun6i_spi_runtime_resume, | |
704 | .runtime_suspend = sun6i_spi_runtime_suspend, | |
705 | }; | |
706 | ||
707 | static struct platform_driver sun6i_spi_driver = { | |
708 | .probe = sun6i_spi_probe, | |
709 | .remove = sun6i_spi_remove, | |
710 | .driver = { | |
711 | .name = "sun6i-spi", | |
3558fe90 MR |
712 | .of_match_table = sun6i_spi_match, |
713 | .pm = &sun6i_spi_pm_ops, | |
714 | }, | |
715 | }; | |
716 | module_platform_driver(sun6i_spi_driver); | |
717 | ||
718 | MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); | |
719 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
720 | MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); | |
721 | MODULE_LICENSE("GPL"); |