Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3558fe90 MR |
2 | /* |
3 | * Copyright (C) 2012 - 2014 Allwinner Tech | |
4 | * Pan Nan <pannan@allwinnertech.com> | |
5 | * | |
6 | * Copyright (C) 2014 Maxime Ripard | |
7 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
3558fe90 MR |
8 | */ |
9 | ||
9a3ef9df | 10 | #include <linux/bitfield.h> |
3558fe90 MR |
11 | #include <linux/clk.h> |
12 | #include <linux/delay.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
749396cb | 17 | #include <linux/of.h> |
3558fe90 MR |
18 | #include <linux/platform_device.h> |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/reset.h> | |
345980a3 | 21 | #include <linux/dmaengine.h> |
3558fe90 MR |
22 | |
23 | #include <linux/spi/spi.h> | |
24 | ||
ae0f18be AK |
25 | #define SUN6I_AUTOSUSPEND_TIMEOUT 2000 |
26 | ||
3558fe90 | 27 | #define SUN6I_FIFO_DEPTH 128 |
10565dfd | 28 | #define SUN8I_FIFO_DEPTH 64 |
3558fe90 MR |
29 | |
30 | #define SUN6I_GBL_CTL_REG 0x04 | |
31 | #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) | |
32 | #define SUN6I_GBL_CTL_MASTER BIT(1) | |
33 | #define SUN6I_GBL_CTL_TP BIT(7) | |
34 | #define SUN6I_GBL_CTL_RST BIT(31) | |
35 | ||
36 | #define SUN6I_TFR_CTL_REG 0x08 | |
37 | #define SUN6I_TFR_CTL_CPHA BIT(0) | |
38 | #define SUN6I_TFR_CTL_CPOL BIT(1) | |
39 | #define SUN6I_TFR_CTL_SPOL BIT(2) | |
d31ad46f AL |
40 | #define SUN6I_TFR_CTL_CS_MASK 0x30 |
41 | #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) | |
3558fe90 MR |
42 | #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) |
43 | #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) | |
44 | #define SUN6I_TFR_CTL_DHB BIT(8) | |
8e886ac8 | 45 | #define SUN6I_TFR_CTL_SDC BIT(11) |
3558fe90 | 46 | #define SUN6I_TFR_CTL_FBS BIT(12) |
8e886ac8 | 47 | #define SUN6I_TFR_CTL_SDM BIT(13) |
3558fe90 MR |
48 | #define SUN6I_TFR_CTL_XCH BIT(31) |
49 | ||
50 | #define SUN6I_INT_CTL_REG 0x10 | |
913f536c IZ |
51 | #define SUN6I_INT_CTL_RF_RDY BIT(0) |
52 | #define SUN6I_INT_CTL_TF_ERQ BIT(4) | |
3558fe90 MR |
53 | #define SUN6I_INT_CTL_RF_OVF BIT(8) |
54 | #define SUN6I_INT_CTL_TC BIT(12) | |
55 | ||
56 | #define SUN6I_INT_STA_REG 0x14 | |
57 | ||
58 | #define SUN6I_FIFO_CTL_REG 0x18 | |
913f536c | 59 | #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff |
345980a3 | 60 | #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8) |
913f536c | 61 | #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 |
3558fe90 | 62 | #define SUN6I_FIFO_CTL_RF_RST BIT(15) |
913f536c IZ |
63 | #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff |
64 | #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 | |
345980a3 | 65 | #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24) |
3558fe90 MR |
66 | #define SUN6I_FIFO_CTL_TF_RST BIT(31) |
67 | ||
68 | #define SUN6I_FIFO_STA_REG 0x1c | |
5197da03 | 69 | #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) |
9a3ef9df | 70 | #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) |
3558fe90 MR |
71 | |
72 | #define SUN6I_CLK_CTL_REG 0x24 | |
73 | #define SUN6I_CLK_CTL_CDR2_MASK 0xff | |
74 | #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) | |
75 | #define SUN6I_CLK_CTL_CDR1_MASK 0xf | |
76 | #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) | |
77 | #define SUN6I_CLK_CTL_DRS BIT(12) | |
78 | ||
913f536c IZ |
79 | #define SUN6I_MAX_XFER_SIZE 0xffffff |
80 | ||
3558fe90 | 81 | #define SUN6I_BURST_CNT_REG 0x30 |
3558fe90 MR |
82 | |
83 | #define SUN6I_XMIT_CNT_REG 0x34 | |
3558fe90 MR |
84 | |
85 | #define SUN6I_BURST_CTL_CNT_REG 0x38 | |
0605d9fb MK |
86 | #define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0) |
87 | #define SUN6I_BURST_CTL_CNT_DRM BIT(28) | |
88 | #define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29) | |
3558fe90 MR |
89 | |
90 | #define SUN6I_TXDATA_REG 0x200 | |
91 | #define SUN6I_RXDATA_REG 0x300 | |
92 | ||
b00c0d89 IZ |
93 | struct sun6i_spi_cfg { |
94 | unsigned long fifo_depth; | |
8e886ac8 | 95 | bool has_clk_ctl; |
0605d9fb | 96 | u32 mode_bits; |
b00c0d89 IZ |
97 | }; |
98 | ||
3558fe90 MR |
99 | struct sun6i_spi { |
100 | struct spi_master *master; | |
101 | void __iomem *base_addr; | |
345980a3 AK |
102 | dma_addr_t dma_addr_rx; |
103 | dma_addr_t dma_addr_tx; | |
3558fe90 MR |
104 | struct clk *hclk; |
105 | struct clk *mclk; | |
106 | struct reset_control *rstc; | |
107 | ||
108 | struct completion done; | |
109 | ||
110 | const u8 *tx_buf; | |
111 | u8 *rx_buf; | |
112 | int len; | |
b00c0d89 | 113 | const struct sun6i_spi_cfg *cfg; |
3558fe90 MR |
114 | }; |
115 | ||
116 | static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) | |
117 | { | |
118 | return readl(sspi->base_addr + reg); | |
119 | } | |
120 | ||
121 | static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) | |
122 | { | |
123 | writel(value, sspi->base_addr + reg); | |
124 | } | |
125 | ||
5197da03 MKB |
126 | static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) |
127 | { | |
128 | u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); | |
129 | ||
130 | return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); | |
131 | } | |
132 | ||
913f536c IZ |
133 | static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) |
134 | { | |
135 | u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); | |
136 | ||
9a3ef9df | 137 | return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); |
913f536c IZ |
138 | } |
139 | ||
913f536c IZ |
140 | static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) |
141 | { | |
142 | u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); | |
143 | ||
144 | reg &= ~mask; | |
145 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); | |
146 | } | |
147 | ||
92a52ee8 | 148 | static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi) |
3558fe90 | 149 | { |
92a52ee8 | 150 | u32 len; |
3558fe90 MR |
151 | u8 byte; |
152 | ||
153 | /* See how much data is available */ | |
92a52ee8 | 154 | len = sun6i_spi_get_rx_fifo_count(sspi); |
3558fe90 MR |
155 | |
156 | while (len--) { | |
157 | byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); | |
158 | if (sspi->rx_buf) | |
159 | *sspi->rx_buf++ = byte; | |
160 | } | |
161 | } | |
162 | ||
e4e8ca3f | 163 | static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) |
3558fe90 | 164 | { |
913f536c | 165 | u32 cnt; |
e4e8ca3f | 166 | int len; |
3558fe90 MR |
167 | u8 byte; |
168 | ||
913f536c | 169 | /* See how much data we can fit */ |
b00c0d89 | 170 | cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); |
913f536c | 171 | |
e4e8ca3f | 172 | len = min((int)cnt, sspi->len); |
3558fe90 MR |
173 | |
174 | while (len--) { | |
175 | byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; | |
176 | writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); | |
177 | sspi->len--; | |
178 | } | |
179 | } | |
180 | ||
181 | static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) | |
182 | { | |
183 | struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); | |
184 | u32 reg; | |
185 | ||
186 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
187 | reg &= ~SUN6I_TFR_CTL_CS_MASK; | |
9e264f3f | 188 | reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0)); |
3558fe90 MR |
189 | |
190 | if (enable) | |
191 | reg |= SUN6I_TFR_CTL_CS_LEVEL; | |
192 | else | |
193 | reg &= ~SUN6I_TFR_CTL_CS_LEVEL; | |
194 | ||
195 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
196 | } | |
197 | ||
794912cf MS |
198 | static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) |
199 | { | |
3288d5cb | 200 | return SUN6I_MAX_XFER_SIZE - 1; |
794912cf | 201 | } |
3558fe90 | 202 | |
345980a3 AK |
203 | static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi, |
204 | struct spi_transfer *tfr) | |
205 | { | |
206 | struct dma_async_tx_descriptor *rxdesc, *txdesc; | |
207 | struct spi_master *master = sspi->master; | |
208 | ||
209 | rxdesc = NULL; | |
210 | if (tfr->rx_buf) { | |
211 | struct dma_slave_config rxconf = { | |
212 | .direction = DMA_DEV_TO_MEM, | |
213 | .src_addr = sspi->dma_addr_rx, | |
214 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
215 | .src_maxburst = 8, | |
216 | }; | |
217 | ||
218 | dmaengine_slave_config(master->dma_rx, &rxconf); | |
219 | ||
220 | rxdesc = dmaengine_prep_slave_sg(master->dma_rx, | |
221 | tfr->rx_sg.sgl, | |
222 | tfr->rx_sg.nents, | |
223 | DMA_DEV_TO_MEM, | |
224 | DMA_PREP_INTERRUPT); | |
225 | if (!rxdesc) | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | txdesc = NULL; | |
230 | if (tfr->tx_buf) { | |
231 | struct dma_slave_config txconf = { | |
232 | .direction = DMA_MEM_TO_DEV, | |
233 | .dst_addr = sspi->dma_addr_tx, | |
234 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
235 | .dst_maxburst = 8, | |
236 | }; | |
237 | ||
238 | dmaengine_slave_config(master->dma_tx, &txconf); | |
239 | ||
240 | txdesc = dmaengine_prep_slave_sg(master->dma_tx, | |
241 | tfr->tx_sg.sgl, | |
242 | tfr->tx_sg.nents, | |
243 | DMA_MEM_TO_DEV, | |
244 | DMA_PREP_INTERRUPT); | |
245 | if (!txdesc) { | |
246 | if (rxdesc) | |
247 | dmaengine_terminate_sync(master->dma_rx); | |
248 | return -EINVAL; | |
249 | } | |
250 | } | |
251 | ||
252 | if (tfr->rx_buf) { | |
253 | dmaengine_submit(rxdesc); | |
254 | dma_async_issue_pending(master->dma_rx); | |
255 | } | |
256 | ||
257 | if (tfr->tx_buf) { | |
258 | dmaengine_submit(txdesc); | |
259 | dma_async_issue_pending(master->dma_tx); | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
3558fe90 MR |
265 | static int sun6i_spi_transfer_one(struct spi_master *master, |
266 | struct spi_device *spi, | |
267 | struct spi_transfer *tfr) | |
268 | { | |
269 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
8e886ac8 | 270 | unsigned int div, div_cdr1, div_cdr2, timeout; |
719bd654 | 271 | unsigned int start, end, tx_time; |
913f536c | 272 | unsigned int trig_level; |
0605d9fb | 273 | unsigned int tx_len = 0, rx_len = 0, nbits = 0; |
345980a3 | 274 | bool use_dma; |
3558fe90 MR |
275 | int ret = 0; |
276 | u32 reg; | |
277 | ||
913f536c | 278 | if (tfr->len > SUN6I_MAX_XFER_SIZE) |
3558fe90 MR |
279 | return -EINVAL; |
280 | ||
281 | reinit_completion(&sspi->done); | |
282 | sspi->tx_buf = tfr->tx_buf; | |
283 | sspi->rx_buf = tfr->rx_buf; | |
284 | sspi->len = tfr->len; | |
345980a3 | 285 | use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; |
3558fe90 MR |
286 | |
287 | /* Clear pending interrupts */ | |
288 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); | |
289 | ||
290 | /* Reset FIFO */ | |
291 | sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, | |
292 | SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); | |
293 | ||
345980a3 AK |
294 | reg = 0; |
295 | ||
296 | if (!use_dma) { | |
297 | /* | |
298 | * Setup FIFO interrupt trigger level | |
299 | * Here we choose 3/4 of the full fifo depth, as it's | |
300 | * the hardcoded value used in old generation of Allwinner | |
301 | * SPI controller. (See spi-sun4i.c) | |
302 | */ | |
b00c0d89 | 303 | trig_level = sspi->cfg->fifo_depth / 4 * 3; |
345980a3 AK |
304 | } else { |
305 | /* | |
306 | * Setup FIFO DMA request trigger level | |
307 | * We choose 1/2 of the full fifo depth, that value will | |
308 | * be used as DMA burst length. | |
309 | */ | |
b00c0d89 | 310 | trig_level = sspi->cfg->fifo_depth / 2; |
345980a3 AK |
311 | |
312 | if (tfr->tx_buf) | |
313 | reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; | |
314 | if (tfr->rx_buf) | |
315 | reg |= SUN6I_FIFO_CTL_RF_DRQ_EN; | |
316 | } | |
317 | ||
318 | reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | | |
319 | (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS); | |
320 | ||
321 | sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); | |
913f536c | 322 | |
3558fe90 MR |
323 | /* |
324 | * Setup the transfer control register: Chip Select, | |
325 | * polarities, etc. | |
326 | */ | |
327 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
328 | ||
329 | if (spi->mode & SPI_CPOL) | |
330 | reg |= SUN6I_TFR_CTL_CPOL; | |
331 | else | |
332 | reg &= ~SUN6I_TFR_CTL_CPOL; | |
333 | ||
334 | if (spi->mode & SPI_CPHA) | |
335 | reg |= SUN6I_TFR_CTL_CPHA; | |
336 | else | |
337 | reg &= ~SUN6I_TFR_CTL_CPHA; | |
338 | ||
339 | if (spi->mode & SPI_LSB_FIRST) | |
340 | reg |= SUN6I_TFR_CTL_FBS; | |
341 | else | |
342 | reg &= ~SUN6I_TFR_CTL_FBS; | |
343 | ||
344 | /* | |
345 | * If it's a TX only transfer, we don't want to fill the RX | |
346 | * FIFO with bogus data | |
347 | */ | |
7716fa80 | 348 | if (sspi->rx_buf) { |
3558fe90 | 349 | reg &= ~SUN6I_TFR_CTL_DHB; |
7716fa80 MKB |
350 | rx_len = tfr->len; |
351 | } else { | |
3558fe90 | 352 | reg |= SUN6I_TFR_CTL_DHB; |
7716fa80 | 353 | } |
3558fe90 MR |
354 | |
355 | /* We want to control the chip select manually */ | |
356 | reg |= SUN6I_TFR_CTL_CS_MANUAL; | |
357 | ||
358 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
359 | ||
8e886ac8 MK |
360 | if (sspi->cfg->has_clk_ctl) { |
361 | unsigned int mclk_rate = clk_get_rate(sspi->mclk); | |
3558fe90 | 362 | |
8e886ac8 MK |
363 | /* Ensure that we have a parent clock fast enough */ |
364 | if (mclk_rate < (2 * tfr->speed_hz)) { | |
365 | clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); | |
366 | mclk_rate = clk_get_rate(sspi->mclk); | |
367 | } | |
368 | ||
369 | /* | |
370 | * Setup clock divider. | |
371 | * | |
372 | * We have two choices there. Either we can use the clock | |
373 | * divide rate 1, which is calculated thanks to this formula: | |
374 | * SPI_CLK = MOD_CLK / (2 ^ cdr) | |
375 | * Or we can use CDR2, which is calculated with the formula: | |
376 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) | |
377 | * Wether we use the former or the latter is set through the | |
378 | * DRS bit. | |
379 | * | |
380 | * First try CDR2, and if we can't reach the expected | |
381 | * frequency, fall back to CDR1. | |
382 | */ | |
383 | div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); | |
384 | div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); | |
385 | if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { | |
386 | reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; | |
387 | tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); | |
388 | } else { | |
389 | div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); | |
390 | reg = SUN6I_CLK_CTL_CDR1(div); | |
391 | tfr->effective_speed_hz = mclk_rate / (1 << div); | |
392 | } | |
393 | ||
394 | sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); | |
3558fe90 | 395 | } else { |
8e886ac8 MK |
396 | clk_set_rate(sspi->mclk, tfr->speed_hz); |
397 | tfr->effective_speed_hz = clk_get_rate(sspi->mclk); | |
398 | ||
399 | /* | |
400 | * Configure work mode. | |
401 | * | |
402 | * There are three work modes depending on the controller clock | |
403 | * frequency: | |
404 | * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0 | |
405 | * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0 | |
406 | * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1 | |
407 | */ | |
408 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
409 | reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC); | |
410 | ||
411 | if (tfr->effective_speed_hz <= 24000000) | |
412 | reg |= SUN6I_TFR_CTL_SDM; | |
413 | else if (tfr->effective_speed_hz >= 80000000) | |
414 | reg |= SUN6I_TFR_CTL_SDC; | |
415 | ||
416 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); | |
3558fe90 MR |
417 | } |
418 | ||
0d7993b2 MV |
419 | /* Finally enable the bus - doing so before might raise SCK to HIGH */ |
420 | reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); | |
421 | reg |= SUN6I_GBL_CTL_BUS_ENABLE; | |
422 | sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); | |
3558fe90 MR |
423 | |
424 | /* Setup the transfer now... */ | |
0605d9fb | 425 | if (sspi->tx_buf) { |
3558fe90 | 426 | tx_len = tfr->len; |
0605d9fb MK |
427 | nbits = tfr->tx_nbits; |
428 | } else if (tfr->rx_buf) { | |
429 | nbits = tfr->rx_nbits; | |
430 | } | |
431 | ||
432 | switch (nbits) { | |
433 | case SPI_NBITS_DUAL: | |
434 | reg = SUN6I_BURST_CTL_CNT_DRM; | |
435 | break; | |
436 | case SPI_NBITS_QUAD: | |
437 | reg = SUN6I_BURST_CTL_CNT_QUAD_EN; | |
438 | break; | |
439 | case SPI_NBITS_SINGLE: | |
440 | default: | |
441 | reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len); | |
442 | } | |
3558fe90 MR |
443 | |
444 | /* Setup the counters */ | |
0605d9fb | 445 | sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg); |
2130be57 MKB |
446 | sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); |
447 | sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); | |
3558fe90 | 448 | |
345980a3 AK |
449 | if (!use_dma) { |
450 | /* Fill the TX FIFO */ | |
451 | sun6i_spi_fill_fifo(sspi); | |
452 | } else { | |
453 | ret = sun6i_spi_prepare_dma(sspi, tfr); | |
454 | if (ret) { | |
455 | dev_warn(&master->dev, | |
456 | "%s: prepare DMA failed, ret=%d", | |
457 | dev_name(&spi->dev), ret); | |
458 | return ret; | |
459 | } | |
460 | } | |
3558fe90 MR |
461 | |
462 | /* Enable the interrupts */ | |
7716fa80 | 463 | reg = SUN6I_INT_CTL_TC; |
4e7390e9 | 464 | |
345980a3 | 465 | if (!use_dma) { |
b00c0d89 | 466 | if (rx_len > sspi->cfg->fifo_depth) |
345980a3 | 467 | reg |= SUN6I_INT_CTL_RF_RDY; |
b00c0d89 | 468 | if (tx_len > sspi->cfg->fifo_depth) |
345980a3 AK |
469 | reg |= SUN6I_INT_CTL_TF_ERQ; |
470 | } | |
4e7390e9 MKB |
471 | |
472 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); | |
3558fe90 MR |
473 | |
474 | /* Start the transfer */ | |
475 | reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); | |
476 | sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); | |
477 | ||
6eef8955 | 478 | tx_time = spi_controller_xfer_timeout(master, tfr); |
719bd654 | 479 | start = jiffies; |
3558fe90 | 480 | timeout = wait_for_completion_timeout(&sspi->done, |
719bd654 MS |
481 | msecs_to_jiffies(tx_time)); |
482 | end = jiffies; | |
3558fe90 | 483 | if (!timeout) { |
719bd654 MS |
484 | dev_warn(&master->dev, |
485 | "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", | |
486 | dev_name(&spi->dev), tfr->len, tfr->speed_hz, | |
487 | jiffies_to_msecs(end - start), tx_time); | |
3558fe90 | 488 | ret = -ETIMEDOUT; |
3558fe90 MR |
489 | } |
490 | ||
3558fe90 MR |
491 | sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); |
492 | ||
345980a3 AK |
493 | if (ret && use_dma) { |
494 | dmaengine_terminate_sync(master->dma_rx); | |
495 | dmaengine_terminate_sync(master->dma_tx); | |
496 | } | |
497 | ||
3558fe90 MR |
498 | return ret; |
499 | } | |
500 | ||
501 | static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) | |
502 | { | |
503 | struct sun6i_spi *sspi = dev_id; | |
504 | u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); | |
505 | ||
506 | /* Transfer complete */ | |
507 | if (status & SUN6I_INT_CTL_TC) { | |
508 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); | |
92a52ee8 | 509 | sun6i_spi_drain_fifo(sspi); |
3558fe90 MR |
510 | complete(&sspi->done); |
511 | return IRQ_HANDLED; | |
512 | } | |
513 | ||
913f536c IZ |
514 | /* Receive FIFO 3/4 full */ |
515 | if (status & SUN6I_INT_CTL_RF_RDY) { | |
92a52ee8 | 516 | sun6i_spi_drain_fifo(sspi); |
913f536c IZ |
517 | /* Only clear the interrupt _after_ draining the FIFO */ |
518 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); | |
519 | return IRQ_HANDLED; | |
520 | } | |
521 | ||
522 | /* Transmit FIFO 3/4 empty */ | |
523 | if (status & SUN6I_INT_CTL_TF_ERQ) { | |
e4e8ca3f | 524 | sun6i_spi_fill_fifo(sspi); |
913f536c IZ |
525 | |
526 | if (!sspi->len) | |
527 | /* nothing left to transmit */ | |
528 | sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); | |
529 | ||
530 | /* Only clear the interrupt _after_ re-seeding the FIFO */ | |
531 | sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); | |
532 | ||
533 | return IRQ_HANDLED; | |
534 | } | |
535 | ||
3558fe90 MR |
536 | return IRQ_NONE; |
537 | } | |
538 | ||
539 | static int sun6i_spi_runtime_resume(struct device *dev) | |
540 | { | |
541 | struct spi_master *master = dev_get_drvdata(dev); | |
542 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
543 | int ret; | |
544 | ||
545 | ret = clk_prepare_enable(sspi->hclk); | |
546 | if (ret) { | |
547 | dev_err(dev, "Couldn't enable AHB clock\n"); | |
548 | goto out; | |
549 | } | |
550 | ||
551 | ret = clk_prepare_enable(sspi->mclk); | |
552 | if (ret) { | |
553 | dev_err(dev, "Couldn't enable module clock\n"); | |
554 | goto err; | |
555 | } | |
556 | ||
557 | ret = reset_control_deassert(sspi->rstc); | |
558 | if (ret) { | |
559 | dev_err(dev, "Couldn't deassert the device from reset\n"); | |
560 | goto err2; | |
561 | } | |
562 | ||
563 | sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, | |
0d7993b2 | 564 | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); |
3558fe90 MR |
565 | |
566 | return 0; | |
567 | ||
568 | err2: | |
569 | clk_disable_unprepare(sspi->mclk); | |
570 | err: | |
571 | clk_disable_unprepare(sspi->hclk); | |
572 | out: | |
573 | return ret; | |
574 | } | |
575 | ||
576 | static int sun6i_spi_runtime_suspend(struct device *dev) | |
577 | { | |
578 | struct spi_master *master = dev_get_drvdata(dev); | |
579 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
580 | ||
581 | reset_control_assert(sspi->rstc); | |
582 | clk_disable_unprepare(sspi->mclk); | |
583 | clk_disable_unprepare(sspi->hclk); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
345980a3 AK |
588 | static bool sun6i_spi_can_dma(struct spi_master *master, |
589 | struct spi_device *spi, | |
590 | struct spi_transfer *xfer) | |
591 | { | |
592 | struct sun6i_spi *sspi = spi_master_get_devdata(master); | |
593 | ||
594 | /* | |
595 | * If the number of spi words to transfer is less or equal than | |
596 | * the fifo length we can just fill the fifo and wait for a single | |
597 | * irq, so don't bother setting up dma | |
598 | */ | |
b00c0d89 | 599 | return xfer->len > sspi->cfg->fifo_depth; |
345980a3 AK |
600 | } |
601 | ||
3558fe90 MR |
602 | static int sun6i_spi_probe(struct platform_device *pdev) |
603 | { | |
604 | struct spi_master *master; | |
605 | struct sun6i_spi *sspi; | |
345980a3 | 606 | struct resource *mem; |
3558fe90 MR |
607 | int ret = 0, irq; |
608 | ||
609 | master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); | |
610 | if (!master) { | |
611 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
612 | return -ENOMEM; | |
613 | } | |
614 | ||
615 | platform_set_drvdata(pdev, master); | |
616 | sspi = spi_master_get_devdata(master); | |
617 | ||
345980a3 | 618 | sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); |
3558fe90 MR |
619 | if (IS_ERR(sspi->base_addr)) { |
620 | ret = PTR_ERR(sspi->base_addr); | |
621 | goto err_free_master; | |
622 | } | |
623 | ||
624 | irq = platform_get_irq(pdev, 0); | |
625 | if (irq < 0) { | |
3558fe90 MR |
626 | ret = -ENXIO; |
627 | goto err_free_master; | |
628 | } | |
629 | ||
630 | ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, | |
631 | 0, "sun6i-spi", sspi); | |
632 | if (ret) { | |
633 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
634 | goto err_free_master; | |
635 | } | |
636 | ||
637 | sspi->master = master; | |
b00c0d89 | 638 | sspi->cfg = of_device_get_match_data(&pdev->dev); |
10565dfd | 639 | |
0b06d8cf MS |
640 | master->max_speed_hz = 100 * 1000 * 1000; |
641 | master->min_speed_hz = 3 * 1000; | |
74750e06 | 642 | master->use_gpio_descriptors = true; |
3558fe90 MR |
643 | master->set_cs = sun6i_spi_set_cs; |
644 | master->transfer_one = sun6i_spi_transfer_one; | |
645 | master->num_chipselect = 4; | |
0605d9fb MK |
646 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | |
647 | sspi->cfg->mode_bits; | |
743a46b8 | 648 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
3558fe90 MR |
649 | master->dev.of_node = pdev->dev.of_node; |
650 | master->auto_runtime_pm = true; | |
794912cf | 651 | master->max_transfer_size = sun6i_spi_max_transfer_size; |
3558fe90 MR |
652 | |
653 | sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); | |
654 | if (IS_ERR(sspi->hclk)) { | |
655 | dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); | |
656 | ret = PTR_ERR(sspi->hclk); | |
657 | goto err_free_master; | |
658 | } | |
659 | ||
660 | sspi->mclk = devm_clk_get(&pdev->dev, "mod"); | |
661 | if (IS_ERR(sspi->mclk)) { | |
662 | dev_err(&pdev->dev, "Unable to acquire module clock\n"); | |
663 | ret = PTR_ERR(sspi->mclk); | |
664 | goto err_free_master; | |
665 | } | |
666 | ||
667 | init_completion(&sspi->done); | |
668 | ||
36bc7491 | 669 | sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
3558fe90 MR |
670 | if (IS_ERR(sspi->rstc)) { |
671 | dev_err(&pdev->dev, "Couldn't get reset controller\n"); | |
672 | ret = PTR_ERR(sspi->rstc); | |
673 | goto err_free_master; | |
674 | } | |
675 | ||
345980a3 AK |
676 | master->dma_tx = dma_request_chan(&pdev->dev, "tx"); |
677 | if (IS_ERR(master->dma_tx)) { | |
678 | /* Check tx to see if we need defer probing driver */ | |
679 | if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { | |
680 | ret = -EPROBE_DEFER; | |
681 | goto err_free_master; | |
682 | } | |
683 | dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); | |
684 | master->dma_tx = NULL; | |
685 | } | |
686 | ||
687 | master->dma_rx = dma_request_chan(&pdev->dev, "rx"); | |
688 | if (IS_ERR(master->dma_rx)) { | |
689 | if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { | |
690 | ret = -EPROBE_DEFER; | |
691 | goto err_free_dma_tx; | |
692 | } | |
693 | dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); | |
694 | master->dma_rx = NULL; | |
695 | } | |
696 | ||
697 | if (master->dma_tx && master->dma_rx) { | |
698 | sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; | |
699 | sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; | |
700 | master->can_dma = sun6i_spi_can_dma; | |
701 | } | |
702 | ||
3558fe90 MR |
703 | /* |
704 | * This wake-up/shutdown pattern is to be able to have the | |
705 | * device woken up, even if runtime_pm is disabled | |
706 | */ | |
707 | ret = sun6i_spi_runtime_resume(&pdev->dev); | |
708 | if (ret) { | |
709 | dev_err(&pdev->dev, "Couldn't resume the device\n"); | |
345980a3 | 710 | goto err_free_dma_rx; |
3558fe90 MR |
711 | } |
712 | ||
ae0f18be AK |
713 | pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); |
714 | pm_runtime_use_autosuspend(&pdev->dev); | |
3558fe90 MR |
715 | pm_runtime_set_active(&pdev->dev); |
716 | pm_runtime_enable(&pdev->dev); | |
3558fe90 MR |
717 | |
718 | ret = devm_spi_register_master(&pdev->dev, master); | |
719 | if (ret) { | |
720 | dev_err(&pdev->dev, "cannot register SPI master\n"); | |
721 | goto err_pm_disable; | |
722 | } | |
723 | ||
724 | return 0; | |
725 | ||
726 | err_pm_disable: | |
727 | pm_runtime_disable(&pdev->dev); | |
728 | sun6i_spi_runtime_suspend(&pdev->dev); | |
345980a3 AK |
729 | err_free_dma_rx: |
730 | if (master->dma_rx) | |
731 | dma_release_channel(master->dma_rx); | |
732 | err_free_dma_tx: | |
733 | if (master->dma_tx) | |
734 | dma_release_channel(master->dma_tx); | |
3558fe90 MR |
735 | err_free_master: |
736 | spi_master_put(master); | |
737 | return ret; | |
738 | } | |
739 | ||
edf69ab9 | 740 | static void sun6i_spi_remove(struct platform_device *pdev) |
3558fe90 | 741 | { |
345980a3 AK |
742 | struct spi_master *master = platform_get_drvdata(pdev); |
743 | ||
2d9bbd02 | 744 | pm_runtime_force_suspend(&pdev->dev); |
3558fe90 | 745 | |
345980a3 AK |
746 | if (master->dma_tx) |
747 | dma_release_channel(master->dma_tx); | |
748 | if (master->dma_rx) | |
749 | dma_release_channel(master->dma_rx); | |
3558fe90 MR |
750 | } |
751 | ||
b00c0d89 IZ |
752 | static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { |
753 | .fifo_depth = SUN6I_FIFO_DEPTH, | |
8e886ac8 | 754 | .has_clk_ctl = true, |
b00c0d89 IZ |
755 | }; |
756 | ||
757 | static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { | |
758 | .fifo_depth = SUN8I_FIFO_DEPTH, | |
8e886ac8 | 759 | .has_clk_ctl = true, |
b00c0d89 IZ |
760 | }; |
761 | ||
046484cb MK |
762 | static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = { |
763 | .fifo_depth = SUN8I_FIFO_DEPTH, | |
25453d79 | 764 | .mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD, |
046484cb MK |
765 | }; |
766 | ||
3558fe90 | 767 | static const struct of_device_id sun6i_spi_match[] = { |
b00c0d89 IZ |
768 | { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg }, |
769 | { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg }, | |
046484cb MK |
770 | { |
771 | .compatible = "allwinner,sun50i-r329-spi", | |
772 | .data = &sun50i_r329_spi_cfg | |
773 | }, | |
3558fe90 MR |
774 | {} |
775 | }; | |
776 | MODULE_DEVICE_TABLE(of, sun6i_spi_match); | |
777 | ||
778 | static const struct dev_pm_ops sun6i_spi_pm_ops = { | |
779 | .runtime_resume = sun6i_spi_runtime_resume, | |
780 | .runtime_suspend = sun6i_spi_runtime_suspend, | |
781 | }; | |
782 | ||
783 | static struct platform_driver sun6i_spi_driver = { | |
784 | .probe = sun6i_spi_probe, | |
edf69ab9 | 785 | .remove_new = sun6i_spi_remove, |
3558fe90 MR |
786 | .driver = { |
787 | .name = "sun6i-spi", | |
3558fe90 MR |
788 | .of_match_table = sun6i_spi_match, |
789 | .pm = &sun6i_spi_pm_ops, | |
790 | }, | |
791 | }; | |
792 | module_platform_driver(sun6i_spi_driver); | |
793 | ||
794 | MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); | |
795 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
796 | MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); | |
797 | MODULE_LICENSE("GPL"); |