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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // STMicroelectronics STM32 SPI Controller driver (master mode only) | |
4 | // | |
5 | // Copyright (C) 2017, STMicroelectronics - All Rights Reserved | |
6 | // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics. | |
7 | ||
dcbe0d84 AD |
8 | #include <linux/debugfs.h> |
9 | #include <linux/clk.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/dmaengine.h> | |
12 | #include <linux/gpio.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/iopoll.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of_platform.h> | |
038ac869 | 17 | #include <linux/pm_runtime.h> |
dcbe0d84 AD |
18 | #include <linux/reset.h> |
19 | #include <linux/spi/spi.h> | |
20 | ||
21 | #define DRIVER_NAME "spi_stm32" | |
22 | ||
00505edf CG |
23 | /* STM32F4 SPI registers */ |
24 | #define STM32F4_SPI_CR1 0x00 | |
25 | #define STM32F4_SPI_CR2 0x04 | |
26 | #define STM32F4_SPI_SR 0x08 | |
27 | #define STM32F4_SPI_DR 0x0C | |
28 | #define STM32F4_SPI_I2SCFGR 0x1C | |
29 | ||
30 | /* STM32F4_SPI_CR1 bit fields */ | |
31 | #define STM32F4_SPI_CR1_CPHA BIT(0) | |
32 | #define STM32F4_SPI_CR1_CPOL BIT(1) | |
33 | #define STM32F4_SPI_CR1_MSTR BIT(2) | |
34 | #define STM32F4_SPI_CR1_BR_SHIFT 3 | |
35 | #define STM32F4_SPI_CR1_BR GENMASK(5, 3) | |
36 | #define STM32F4_SPI_CR1_SPE BIT(6) | |
37 | #define STM32F4_SPI_CR1_LSBFRST BIT(7) | |
38 | #define STM32F4_SPI_CR1_SSI BIT(8) | |
39 | #define STM32F4_SPI_CR1_SSM BIT(9) | |
40 | #define STM32F4_SPI_CR1_RXONLY BIT(10) | |
41 | #define STM32F4_SPI_CR1_DFF BIT(11) | |
42 | #define STM32F4_SPI_CR1_CRCNEXT BIT(12) | |
43 | #define STM32F4_SPI_CR1_CRCEN BIT(13) | |
44 | #define STM32F4_SPI_CR1_BIDIOE BIT(14) | |
45 | #define STM32F4_SPI_CR1_BIDIMODE BIT(15) | |
46 | #define STM32F4_SPI_CR1_BR_MIN 0 | |
47 | #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3) | |
48 | ||
49 | /* STM32F4_SPI_CR2 bit fields */ | |
50 | #define STM32F4_SPI_CR2_RXDMAEN BIT(0) | |
51 | #define STM32F4_SPI_CR2_TXDMAEN BIT(1) | |
52 | #define STM32F4_SPI_CR2_SSOE BIT(2) | |
53 | #define STM32F4_SPI_CR2_FRF BIT(4) | |
54 | #define STM32F4_SPI_CR2_ERRIE BIT(5) | |
55 | #define STM32F4_SPI_CR2_RXNEIE BIT(6) | |
56 | #define STM32F4_SPI_CR2_TXEIE BIT(7) | |
57 | ||
58 | /* STM32F4_SPI_SR bit fields */ | |
59 | #define STM32F4_SPI_SR_RXNE BIT(0) | |
60 | #define STM32F4_SPI_SR_TXE BIT(1) | |
61 | #define STM32F4_SPI_SR_CHSIDE BIT(2) | |
62 | #define STM32F4_SPI_SR_UDR BIT(3) | |
63 | #define STM32F4_SPI_SR_CRCERR BIT(4) | |
64 | #define STM32F4_SPI_SR_MODF BIT(5) | |
65 | #define STM32F4_SPI_SR_OVR BIT(6) | |
66 | #define STM32F4_SPI_SR_BSY BIT(7) | |
67 | #define STM32F4_SPI_SR_FRE BIT(8) | |
68 | ||
69 | /* STM32F4_SPI_I2SCFGR bit fields */ | |
70 | #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11) | |
71 | ||
72 | /* STM32F4 SPI Baud Rate min/max divisor */ | |
73 | #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN) | |
74 | #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX) | |
75 | ||
86026630 CG |
76 | /* STM32H7 SPI registers */ |
77 | #define STM32H7_SPI_CR1 0x00 | |
78 | #define STM32H7_SPI_CR2 0x04 | |
79 | #define STM32H7_SPI_CFG1 0x08 | |
80 | #define STM32H7_SPI_CFG2 0x0C | |
81 | #define STM32H7_SPI_IER 0x10 | |
82 | #define STM32H7_SPI_SR 0x14 | |
83 | #define STM32H7_SPI_IFCR 0x18 | |
84 | #define STM32H7_SPI_TXDR 0x20 | |
85 | #define STM32H7_SPI_RXDR 0x30 | |
86 | #define STM32H7_SPI_I2SCFGR 0x50 | |
87 | ||
88 | /* STM32H7_SPI_CR1 bit fields */ | |
89 | #define STM32H7_SPI_CR1_SPE BIT(0) | |
90 | #define STM32H7_SPI_CR1_MASRX BIT(8) | |
91 | #define STM32H7_SPI_CR1_CSTART BIT(9) | |
92 | #define STM32H7_SPI_CR1_CSUSP BIT(10) | |
93 | #define STM32H7_SPI_CR1_HDDIR BIT(11) | |
94 | #define STM32H7_SPI_CR1_SSI BIT(12) | |
95 | ||
96 | /* STM32H7_SPI_CR2 bit fields */ | |
97 | #define STM32H7_SPI_CR2_TSIZE_SHIFT 0 | |
98 | #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) | |
99 | ||
100 | /* STM32H7_SPI_CFG1 bit fields */ | |
101 | #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 | |
102 | #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) | |
103 | #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 | |
104 | #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) | |
105 | #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) | |
106 | #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) | |
107 | #define STM32H7_SPI_CFG1_MBR_SHIFT 28 | |
108 | #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) | |
109 | #define STM32H7_SPI_CFG1_MBR_MIN 0 | |
110 | #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) | |
111 | ||
112 | /* STM32H7_SPI_CFG2 bit fields */ | |
113 | #define STM32H7_SPI_CFG2_MIDI_SHIFT 4 | |
114 | #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) | |
115 | #define STM32H7_SPI_CFG2_COMM_SHIFT 17 | |
116 | #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) | |
117 | #define STM32H7_SPI_CFG2_SP_SHIFT 19 | |
118 | #define STM32H7_SPI_CFG2_SP GENMASK(21, 19) | |
119 | #define STM32H7_SPI_CFG2_MASTER BIT(22) | |
120 | #define STM32H7_SPI_CFG2_LSBFRST BIT(23) | |
121 | #define STM32H7_SPI_CFG2_CPHA BIT(24) | |
122 | #define STM32H7_SPI_CFG2_CPOL BIT(25) | |
123 | #define STM32H7_SPI_CFG2_SSM BIT(26) | |
124 | #define STM32H7_SPI_CFG2_AFCNTR BIT(31) | |
125 | ||
126 | /* STM32H7_SPI_IER bit fields */ | |
127 | #define STM32H7_SPI_IER_RXPIE BIT(0) | |
128 | #define STM32H7_SPI_IER_TXPIE BIT(1) | |
129 | #define STM32H7_SPI_IER_DXPIE BIT(2) | |
130 | #define STM32H7_SPI_IER_EOTIE BIT(3) | |
131 | #define STM32H7_SPI_IER_TXTFIE BIT(4) | |
132 | #define STM32H7_SPI_IER_OVRIE BIT(6) | |
133 | #define STM32H7_SPI_IER_MODFIE BIT(9) | |
134 | #define STM32H7_SPI_IER_ALL GENMASK(10, 0) | |
135 | ||
136 | /* STM32H7_SPI_SR bit fields */ | |
137 | #define STM32H7_SPI_SR_RXP BIT(0) | |
138 | #define STM32H7_SPI_SR_TXP BIT(1) | |
139 | #define STM32H7_SPI_SR_EOT BIT(3) | |
140 | #define STM32H7_SPI_SR_OVR BIT(6) | |
141 | #define STM32H7_SPI_SR_MODF BIT(9) | |
142 | #define STM32H7_SPI_SR_SUSP BIT(11) | |
143 | #define STM32H7_SPI_SR_RXPLVL_SHIFT 13 | |
144 | #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) | |
145 | #define STM32H7_SPI_SR_RXWNE BIT(15) | |
146 | ||
147 | /* STM32H7_SPI_IFCR bit fields */ | |
148 | #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) | |
149 | ||
150 | /* STM32H7_SPI_I2SCFGR bit fields */ | |
151 | #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) | |
152 | ||
153 | /* STM32H7 SPI Master Baud Rate min/max divisor */ | |
154 | #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) | |
155 | #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) | |
dcbe0d84 | 156 | |
9d5fce16 CG |
157 | /* STM32H7 SPI Communication mode */ |
158 | #define STM32H7_SPI_FULL_DUPLEX 0 | |
159 | #define STM32H7_SPI_SIMPLEX_TX 1 | |
160 | #define STM32H7_SPI_SIMPLEX_RX 2 | |
161 | #define STM32H7_SPI_HALF_DUPLEX 3 | |
162 | ||
163 | /* SPI Communication type */ | |
dcbe0d84 AD |
164 | #define SPI_FULL_DUPLEX 0 |
165 | #define SPI_SIMPLEX_TX 1 | |
166 | #define SPI_SIMPLEX_RX 2 | |
9d5fce16 CG |
167 | #define SPI_3WIRE_TX 3 |
168 | #define SPI_3WIRE_RX 4 | |
dcbe0d84 AD |
169 | |
170 | #define SPI_1HZ_NS 1000000000 | |
171 | ||
00505edf CG |
172 | /* |
173 | * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers | |
174 | * without fifo buffers. | |
175 | */ | |
176 | #define SPI_DMA_MIN_BYTES 16 | |
177 | ||
55166853 CG |
178 | /** |
179 | * stm32_spi_reg - stm32 SPI register & bitfield desc | |
180 | * @reg: register offset | |
181 | * @mask: bitfield mask | |
182 | * @shift: left shift | |
183 | */ | |
184 | struct stm32_spi_reg { | |
185 | int reg; | |
186 | int mask; | |
187 | int shift; | |
188 | }; | |
189 | ||
190 | /** | |
191 | * stm32_spi_regspec - stm32 registers definition, compatible dependent data | |
192 | * en: enable register and SPI enable bit | |
193 | * dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit | |
194 | * dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit | |
195 | * cpol: clock polarity register and polarity bit | |
196 | * cpha: clock phase register and phase bit | |
197 | * lsb_first: LSB transmitted first register and bit | |
198 | * br: baud rate register and bitfields | |
199 | * rx: SPI RX data register | |
200 | * tx: SPI TX data register | |
201 | */ | |
202 | struct stm32_spi_regspec { | |
203 | const struct stm32_spi_reg en; | |
204 | const struct stm32_spi_reg dma_rx_en; | |
205 | const struct stm32_spi_reg dma_tx_en; | |
206 | const struct stm32_spi_reg cpol; | |
207 | const struct stm32_spi_reg cpha; | |
208 | const struct stm32_spi_reg lsb_first; | |
209 | const struct stm32_spi_reg br; | |
210 | const struct stm32_spi_reg rx; | |
211 | const struct stm32_spi_reg tx; | |
212 | }; | |
213 | ||
214 | struct stm32_spi; | |
215 | ||
216 | /** | |
217 | * stm32_spi_cfg - stm32 compatible configuration data | |
218 | * @regs: registers descriptions | |
219 | * @get_fifo_size: routine to get fifo size | |
220 | * @get_bpw_mask: routine to get bits per word mask | |
221 | * @disable: routine to disable controller | |
222 | * @config: routine to configure controller as SPI Master | |
223 | * @set_bpw: routine to configure registers to for bits per word | |
224 | * @set_mode: routine to configure registers to desired mode | |
225 | * @set_data_idleness: optional routine to configure registers to desired idle | |
226 | * time between frames (if driver has this functionality) | |
227 | * set_number_of_data: optional routine to configure registers to desired | |
228 | * number of data (if driver has this functionality) | |
229 | * @can_dma: routine to determine if the transfer is eligible for DMA use | |
230 | * @transfer_one_dma_start: routine to start transfer a single spi_transfer | |
231 | * using DMA | |
232 | * @dma_rx cb: routine to call after DMA RX channel operation is complete | |
233 | * @dma_tx cb: routine to call after DMA TX channel operation is complete | |
234 | * @transfer_one_irq: routine to configure interrupts for driver | |
235 | * @irq_handler_event: Interrupt handler for SPI controller events | |
236 | * @irq_handler_thread: thread of interrupt handler for SPI controller | |
237 | * @baud_rate_div_min: minimum baud rate divisor | |
238 | * @baud_rate_div_max: maximum baud rate divisor | |
239 | * @has_fifo: boolean to know if fifo is used for driver | |
240 | * @has_startbit: boolean to know if start bit is used to start transfer | |
241 | */ | |
242 | struct stm32_spi_cfg { | |
243 | const struct stm32_spi_regspec *regs; | |
244 | int (*get_fifo_size)(struct stm32_spi *spi); | |
245 | int (*get_bpw_mask)(struct stm32_spi *spi); | |
246 | void (*disable)(struct stm32_spi *spi); | |
247 | int (*config)(struct stm32_spi *spi); | |
248 | void (*set_bpw)(struct stm32_spi *spi); | |
249 | int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type); | |
250 | void (*set_data_idleness)(struct stm32_spi *spi, u32 length); | |
251 | int (*set_number_of_data)(struct stm32_spi *spi, u32 length); | |
252 | void (*transfer_one_dma_start)(struct stm32_spi *spi); | |
253 | void (*dma_rx_cb)(void *data); | |
254 | void (*dma_tx_cb)(void *data); | |
255 | int (*transfer_one_irq)(struct stm32_spi *spi); | |
256 | irqreturn_t (*irq_handler_event)(int irq, void *dev_id); | |
257 | irqreturn_t (*irq_handler_thread)(int irq, void *dev_id); | |
258 | unsigned int baud_rate_div_min; | |
259 | unsigned int baud_rate_div_max; | |
260 | bool has_fifo; | |
261 | }; | |
262 | ||
dcbe0d84 AD |
263 | /** |
264 | * struct stm32_spi - private data of the SPI controller | |
265 | * @dev: driver model representation of the controller | |
266 | * @master: controller master interface | |
55166853 | 267 | * @cfg: compatible configuration data |
dcbe0d84 AD |
268 | * @base: virtual memory area |
269 | * @clk: hw kernel clock feeding the SPI clock generator | |
270 | * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator | |
271 | * @rst: SPI controller reset line | |
272 | * @lock: prevent I/O concurrent access | |
273 | * @irq: SPI controller interrupt line | |
274 | * @fifo_size: size of the embedded fifo in bytes | |
275 | * @cur_midi: master inter-data idleness in ns | |
276 | * @cur_speed: speed configured in Hz | |
277 | * @cur_bpw: number of bits in a single SPI data frame | |
278 | * @cur_fthlv: fifo threshold level (data frames in a single data packet) | |
279 | * @cur_comm: SPI communication mode | |
280 | * @cur_xferlen: current transfer length in bytes | |
281 | * @cur_usedma: boolean to know if dma is used in current transfer | |
282 | * @tx_buf: data to be written, or NULL | |
283 | * @rx_buf: data to be read, or NULL | |
284 | * @tx_len: number of data to be written in bytes | |
285 | * @rx_len: number of data to be read in bytes | |
286 | * @dma_tx: dma channel for TX transfer | |
287 | * @dma_rx: dma channel for RX transfer | |
288 | * @phys_addr: SPI registers physical base address | |
289 | */ | |
290 | struct stm32_spi { | |
291 | struct device *dev; | |
292 | struct spi_master *master; | |
55166853 | 293 | const struct stm32_spi_cfg *cfg; |
dcbe0d84 AD |
294 | void __iomem *base; |
295 | struct clk *clk; | |
296 | u32 clk_rate; | |
297 | struct reset_control *rst; | |
298 | spinlock_t lock; /* prevent I/O concurrent access */ | |
299 | int irq; | |
300 | unsigned int fifo_size; | |
301 | ||
302 | unsigned int cur_midi; | |
303 | unsigned int cur_speed; | |
304 | unsigned int cur_bpw; | |
305 | unsigned int cur_fthlv; | |
306 | unsigned int cur_comm; | |
307 | unsigned int cur_xferlen; | |
308 | bool cur_usedma; | |
309 | ||
310 | const void *tx_buf; | |
311 | void *rx_buf; | |
312 | int tx_len; | |
313 | int rx_len; | |
314 | struct dma_chan *dma_tx; | |
315 | struct dma_chan *dma_rx; | |
316 | dma_addr_t phys_addr; | |
317 | }; | |
318 | ||
00505edf CG |
319 | static const struct stm32_spi_regspec stm32f4_spi_regspec = { |
320 | .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE }, | |
321 | ||
322 | .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN }, | |
323 | .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN }, | |
324 | ||
325 | .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL }, | |
326 | .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA }, | |
327 | .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST }, | |
328 | .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT }, | |
329 | ||
330 | .rx = { STM32F4_SPI_DR }, | |
331 | .tx = { STM32F4_SPI_DR }, | |
332 | }; | |
333 | ||
55166853 CG |
334 | static const struct stm32_spi_regspec stm32h7_spi_regspec = { |
335 | /* SPI data transfer is enabled but spi_ker_ck is idle. | |
336 | * CFG1 and CFG2 registers are write protected when SPE is enabled. | |
337 | */ | |
338 | .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE }, | |
339 | ||
340 | .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN }, | |
341 | .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN }, | |
342 | ||
343 | .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL }, | |
344 | .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA }, | |
345 | .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST }, | |
346 | .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR, | |
347 | STM32H7_SPI_CFG1_MBR_SHIFT }, | |
348 | ||
349 | .rx = { STM32H7_SPI_RXDR }, | |
350 | .tx = { STM32H7_SPI_TXDR }, | |
351 | }; | |
352 | ||
dcbe0d84 AD |
353 | static inline void stm32_spi_set_bits(struct stm32_spi *spi, |
354 | u32 offset, u32 bits) | |
355 | { | |
356 | writel_relaxed(readl_relaxed(spi->base + offset) | bits, | |
357 | spi->base + offset); | |
358 | } | |
359 | ||
360 | static inline void stm32_spi_clr_bits(struct stm32_spi *spi, | |
361 | u32 offset, u32 bits) | |
362 | { | |
363 | writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, | |
364 | spi->base + offset); | |
365 | } | |
366 | ||
367 | /** | |
55166853 | 368 | * stm32h7_spi_get_fifo_size - Return fifo size |
dcbe0d84 AD |
369 | * @spi: pointer to the spi controller data structure |
370 | */ | |
55166853 | 371 | static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) |
dcbe0d84 AD |
372 | { |
373 | unsigned long flags; | |
374 | u32 count = 0; | |
375 | ||
376 | spin_lock_irqsave(&spi->lock, flags); | |
377 | ||
86026630 | 378 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 379 | |
86026630 CG |
380 | while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) |
381 | writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); | |
dcbe0d84 | 382 | |
86026630 | 383 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 AD |
384 | |
385 | spin_unlock_irqrestore(&spi->lock, flags); | |
386 | ||
387 | dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); | |
388 | ||
389 | return count; | |
390 | } | |
391 | ||
00505edf CG |
392 | /** |
393 | * stm32f4_spi_get_bpw_mask - Return bits per word mask | |
394 | * @spi: pointer to the spi controller data structure | |
395 | */ | |
396 | static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) | |
397 | { | |
398 | dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); | |
399 | return SPI_BPW_MASK(8) | SPI_BPW_MASK(16); | |
400 | } | |
401 | ||
dcbe0d84 | 402 | /** |
55166853 | 403 | * stm32h7_spi_get_bpw_mask - Return bits per word mask |
dcbe0d84 AD |
404 | * @spi: pointer to the spi controller data structure |
405 | */ | |
55166853 | 406 | static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) |
dcbe0d84 AD |
407 | { |
408 | unsigned long flags; | |
409 | u32 cfg1, max_bpw; | |
410 | ||
411 | spin_lock_irqsave(&spi->lock, flags); | |
412 | ||
413 | /* | |
414 | * The most significant bit at DSIZE bit field is reserved when the | |
415 | * maximum data size of periperal instances is limited to 16-bit | |
416 | */ | |
86026630 | 417 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); |
dcbe0d84 | 418 | |
86026630 CG |
419 | cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); |
420 | max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> | |
421 | STM32H7_SPI_CFG1_DSIZE_SHIFT; | |
dcbe0d84 AD |
422 | max_bpw += 1; |
423 | ||
424 | spin_unlock_irqrestore(&spi->lock, flags); | |
425 | ||
426 | dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); | |
427 | ||
428 | return SPI_BPW_RANGE_MASK(4, max_bpw); | |
429 | } | |
430 | ||
431 | /** | |
9d5fce16 | 432 | * stm32_spi_prepare_mbr - Determine baud rate divisor value |
dcbe0d84 AD |
433 | * @spi: pointer to the spi controller data structure |
434 | * @speed_hz: requested speed | |
9d5fce16 CG |
435 | * @min_div: minimum baud rate divisor |
436 | * @max_div: maximum baud rate divisor | |
dcbe0d84 | 437 | * |
9d5fce16 | 438 | * Return baud rate divisor value in case of success or -EINVAL |
dcbe0d84 | 439 | */ |
9d5fce16 CG |
440 | static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, |
441 | u32 min_div, u32 max_div) | |
dcbe0d84 AD |
442 | { |
443 | u32 div, mbrdiv; | |
444 | ||
445 | div = DIV_ROUND_UP(spi->clk_rate, speed_hz); | |
446 | ||
447 | /* | |
448 | * SPI framework set xfer->speed_hz to master->max_speed_hz if | |
449 | * xfer->speed_hz is greater than master->max_speed_hz, and it returns | |
450 | * an error when xfer->speed_hz is lower than master->min_speed_hz, so | |
451 | * no need to check it there. | |
452 | * However, we need to ensure the following calculations. | |
453 | */ | |
9d5fce16 | 454 | if ((div < min_div) || (div > max_div)) |
dcbe0d84 AD |
455 | return -EINVAL; |
456 | ||
457 | /* Determine the first power of 2 greater than or equal to div */ | |
128ebb89 AD |
458 | if (div & (div - 1)) |
459 | mbrdiv = fls(div); | |
460 | else | |
461 | mbrdiv = fls(div) - 1; | |
dcbe0d84 AD |
462 | |
463 | spi->cur_speed = spi->clk_rate / (1 << mbrdiv); | |
464 | ||
465 | return mbrdiv - 1; | |
466 | } | |
467 | ||
468 | /** | |
55166853 | 469 | * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level |
dcbe0d84 AD |
470 | * @spi: pointer to the spi controller data structure |
471 | */ | |
55166853 | 472 | static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi) |
dcbe0d84 AD |
473 | { |
474 | u32 fthlv, half_fifo; | |
475 | ||
476 | /* data packet should not exceed 1/2 of fifo space */ | |
477 | half_fifo = (spi->fifo_size / 2); | |
478 | ||
128ebb89 AD |
479 | if (spi->cur_bpw <= 8) |
480 | fthlv = half_fifo; | |
481 | else if (spi->cur_bpw <= 16) | |
482 | fthlv = half_fifo / 2; | |
483 | else | |
484 | fthlv = half_fifo / 4; | |
dcbe0d84 AD |
485 | |
486 | /* align packet size with data registers access */ | |
487 | if (spi->cur_bpw > 8) | |
488 | fthlv -= (fthlv % 2); /* multiple of 2 */ | |
489 | else | |
490 | fthlv -= (fthlv % 4); /* multiple of 4 */ | |
491 | ||
492 | return fthlv; | |
493 | } | |
494 | ||
00505edf CG |
495 | /** |
496 | * stm32f4_spi_write_tx - Write bytes to Transmit Data Register | |
497 | * @spi: pointer to the spi controller data structure | |
498 | * | |
499 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
500 | * tx_buf end. | |
501 | */ | |
502 | static void stm32f4_spi_write_tx(struct stm32_spi *spi) | |
503 | { | |
504 | if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
505 | STM32F4_SPI_SR_TXE)) { | |
506 | u32 offs = spi->cur_xferlen - spi->tx_len; | |
507 | ||
508 | if (spi->cur_bpw == 16) { | |
509 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
510 | ||
511 | writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); | |
512 | spi->tx_len -= sizeof(u16); | |
513 | } else { | |
514 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
515 | ||
516 | writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); | |
517 | spi->tx_len -= sizeof(u8); | |
518 | } | |
519 | } | |
520 | ||
521 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
522 | } | |
523 | ||
dcbe0d84 | 524 | /** |
55166853 | 525 | * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register |
dcbe0d84 AD |
526 | * @spi: pointer to the spi controller data structure |
527 | * | |
528 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
529 | * tx_buf end. | |
530 | */ | |
55166853 | 531 | static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) |
dcbe0d84 AD |
532 | { |
533 | while ((spi->tx_len > 0) && | |
86026630 CG |
534 | (readl_relaxed(spi->base + STM32H7_SPI_SR) & |
535 | STM32H7_SPI_SR_TXP)) { | |
dcbe0d84 AD |
536 | u32 offs = spi->cur_xferlen - spi->tx_len; |
537 | ||
538 | if (spi->tx_len >= sizeof(u32)) { | |
539 | const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); | |
540 | ||
86026630 | 541 | writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
542 | spi->tx_len -= sizeof(u32); |
543 | } else if (spi->tx_len >= sizeof(u16)) { | |
544 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
545 | ||
86026630 | 546 | writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
547 | spi->tx_len -= sizeof(u16); |
548 | } else { | |
549 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
550 | ||
86026630 | 551 | writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
552 | spi->tx_len -= sizeof(u8); |
553 | } | |
554 | } | |
555 | ||
556 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
557 | } | |
558 | ||
00505edf CG |
559 | /** |
560 | * stm32f4_spi_read_rx - Read bytes from Receive Data Register | |
561 | * @spi: pointer to the spi controller data structure | |
562 | * | |
563 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
564 | * rx_buf end. | |
565 | */ | |
566 | static void stm32f4_spi_read_rx(struct stm32_spi *spi) | |
567 | { | |
568 | if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
569 | STM32F4_SPI_SR_RXNE)) { | |
570 | u32 offs = spi->cur_xferlen - spi->rx_len; | |
571 | ||
572 | if (spi->cur_bpw == 16) { | |
573 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
574 | ||
575 | *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); | |
576 | spi->rx_len -= sizeof(u16); | |
577 | } else { | |
578 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
579 | ||
580 | *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); | |
581 | spi->rx_len -= sizeof(u8); | |
582 | } | |
583 | } | |
584 | ||
585 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); | |
586 | } | |
587 | ||
dcbe0d84 | 588 | /** |
55166853 | 589 | * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register |
dcbe0d84 AD |
590 | * @spi: pointer to the spi controller data structure |
591 | * | |
592 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
593 | * rx_buf end. | |
594 | */ | |
55166853 | 595 | static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) |
dcbe0d84 | 596 | { |
86026630 CG |
597 | u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
598 | u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> | |
599 | STM32H7_SPI_SR_RXPLVL_SHIFT; | |
dcbe0d84 AD |
600 | |
601 | while ((spi->rx_len > 0) && | |
86026630 CG |
602 | ((sr & STM32H7_SPI_SR_RXP) || |
603 | (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { | |
dcbe0d84 AD |
604 | u32 offs = spi->cur_xferlen - spi->rx_len; |
605 | ||
606 | if ((spi->rx_len >= sizeof(u32)) || | |
86026630 | 607 | (flush && (sr & STM32H7_SPI_SR_RXWNE))) { |
dcbe0d84 AD |
608 | u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); |
609 | ||
86026630 | 610 | *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
611 | spi->rx_len -= sizeof(u32); |
612 | } else if ((spi->rx_len >= sizeof(u16)) || | |
613 | (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { | |
614 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
615 | ||
86026630 | 616 | *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
617 | spi->rx_len -= sizeof(u16); |
618 | } else { | |
619 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
620 | ||
86026630 | 621 | *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
622 | spi->rx_len -= sizeof(u8); |
623 | } | |
624 | ||
86026630 CG |
625 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
626 | rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> | |
627 | STM32H7_SPI_SR_RXPLVL_SHIFT; | |
dcbe0d84 AD |
628 | } |
629 | ||
630 | dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, | |
631 | flush ? "(flush)" : "", spi->rx_len); | |
632 | } | |
633 | ||
634 | /** | |
635 | * stm32_spi_enable - Enable SPI controller | |
636 | * @spi: pointer to the spi controller data structure | |
dcbe0d84 AD |
637 | */ |
638 | static void stm32_spi_enable(struct stm32_spi *spi) | |
639 | { | |
640 | dev_dbg(spi->dev, "enable controller\n"); | |
641 | ||
55166853 CG |
642 | stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, |
643 | spi->cfg->regs->en.mask); | |
dcbe0d84 AD |
644 | } |
645 | ||
00505edf CG |
646 | /** |
647 | * stm32f4_spi_disable - Disable SPI controller | |
648 | * @spi: pointer to the spi controller data structure | |
649 | */ | |
650 | static void stm32f4_spi_disable(struct stm32_spi *spi) | |
651 | { | |
652 | unsigned long flags; | |
653 | u32 sr; | |
654 | ||
655 | dev_dbg(spi->dev, "disable controller\n"); | |
656 | ||
657 | spin_lock_irqsave(&spi->lock, flags); | |
658 | ||
659 | if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & | |
660 | STM32F4_SPI_CR1_SPE)) { | |
661 | spin_unlock_irqrestore(&spi->lock, flags); | |
662 | return; | |
663 | } | |
664 | ||
665 | /* Disable interrupts */ | |
666 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | | |
667 | STM32F4_SPI_CR2_RXNEIE | | |
668 | STM32F4_SPI_CR2_ERRIE); | |
669 | ||
670 | /* Wait until BSY = 0 */ | |
671 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, | |
672 | sr, !(sr & STM32F4_SPI_SR_BSY), | |
673 | 10, 100000) < 0) { | |
674 | dev_warn(spi->dev, "disabling condition timeout\n"); | |
675 | } | |
676 | ||
677 | if (spi->cur_usedma && spi->dma_tx) | |
678 | dmaengine_terminate_all(spi->dma_tx); | |
679 | if (spi->cur_usedma && spi->dma_rx) | |
680 | dmaengine_terminate_all(spi->dma_rx); | |
681 | ||
682 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); | |
683 | ||
684 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | | |
685 | STM32F4_SPI_CR2_RXDMAEN); | |
686 | ||
687 | /* Sequence to clear OVR flag */ | |
688 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
689 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
690 | ||
691 | spin_unlock_irqrestore(&spi->lock, flags); | |
692 | } | |
693 | ||
dcbe0d84 | 694 | /** |
55166853 | 695 | * stm32h7_spi_disable - Disable SPI controller |
dcbe0d84 AD |
696 | * @spi: pointer to the spi controller data structure |
697 | * | |
698 | * RX-Fifo is flushed when SPI controller is disabled. To prevent any data | |
55166853 | 699 | * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in |
dcbe0d84 | 700 | * RX-Fifo. |
55166853 CG |
701 | * Normally, if TSIZE has been configured, we should relax the hardware at the |
702 | * reception of the EOT interrupt. But in case of error, EOT will not be | |
703 | * raised. So the subsystem unprepare_message call allows us to properly | |
704 | * complete the transfer from an hardware point of view. | |
dcbe0d84 | 705 | */ |
55166853 | 706 | static void stm32h7_spi_disable(struct stm32_spi *spi) |
dcbe0d84 AD |
707 | { |
708 | unsigned long flags; | |
709 | u32 cr1, sr; | |
710 | ||
711 | dev_dbg(spi->dev, "disable controller\n"); | |
712 | ||
713 | spin_lock_irqsave(&spi->lock, flags); | |
714 | ||
86026630 | 715 | cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); |
dcbe0d84 | 716 | |
86026630 | 717 | if (!(cr1 & STM32H7_SPI_CR1_SPE)) { |
dcbe0d84 AD |
718 | spin_unlock_irqrestore(&spi->lock, flags); |
719 | return; | |
720 | } | |
721 | ||
722 | /* Wait on EOT or suspend the flow */ | |
86026630 CG |
723 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, |
724 | sr, !(sr & STM32H7_SPI_SR_EOT), | |
dcbe0d84 | 725 | 10, 100000) < 0) { |
86026630 CG |
726 | if (cr1 & STM32H7_SPI_CR1_CSTART) { |
727 | writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, | |
728 | spi->base + STM32H7_SPI_CR1); | |
dcbe0d84 | 729 | if (readl_relaxed_poll_timeout_atomic( |
86026630 CG |
730 | spi->base + STM32H7_SPI_SR, |
731 | sr, !(sr & STM32H7_SPI_SR_SUSP), | |
dcbe0d84 AD |
732 | 10, 100000) < 0) |
733 | dev_warn(spi->dev, | |
734 | "Suspend request timeout\n"); | |
735 | } | |
736 | } | |
737 | ||
738 | if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) | |
55166853 | 739 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 | 740 | |
2cbee7f8 | 741 | if (spi->cur_usedma && spi->dma_tx) |
dcbe0d84 | 742 | dmaengine_terminate_all(spi->dma_tx); |
2cbee7f8 | 743 | if (spi->cur_usedma && spi->dma_rx) |
dcbe0d84 AD |
744 | dmaengine_terminate_all(spi->dma_rx); |
745 | ||
86026630 | 746 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 747 | |
86026630 CG |
748 | stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | |
749 | STM32H7_SPI_CFG1_RXDMAEN); | |
dcbe0d84 AD |
750 | |
751 | /* Disable interrupts and clear status flags */ | |
86026630 CG |
752 | writel_relaxed(0, spi->base + STM32H7_SPI_IER); |
753 | writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); | |
dcbe0d84 AD |
754 | |
755 | spin_unlock_irqrestore(&spi->lock, flags); | |
756 | } | |
757 | ||
758 | /** | |
759 | * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use | |
760 | * | |
00505edf CG |
761 | * If driver has fifo and the current transfer size is greater than fifo size, |
762 | * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes. | |
dcbe0d84 AD |
763 | */ |
764 | static bool stm32_spi_can_dma(struct spi_master *master, | |
765 | struct spi_device *spi_dev, | |
766 | struct spi_transfer *transfer) | |
767 | { | |
00505edf | 768 | unsigned int dma_size; |
dcbe0d84 AD |
769 | struct stm32_spi *spi = spi_master_get_devdata(master); |
770 | ||
00505edf CG |
771 | if (spi->cfg->has_fifo) |
772 | dma_size = spi->fifo_size; | |
773 | else | |
774 | dma_size = SPI_DMA_MIN_BYTES; | |
775 | ||
dcbe0d84 | 776 | dev_dbg(spi->dev, "%s: %s\n", __func__, |
00505edf | 777 | (transfer->len > dma_size) ? "true" : "false"); |
dcbe0d84 | 778 | |
00505edf CG |
779 | return (transfer->len > dma_size); |
780 | } | |
781 | ||
782 | /** | |
783 | * stm32f4_spi_irq_event - Interrupt handler for SPI controller events | |
784 | * @irq: interrupt line | |
785 | * @dev_id: SPI controller master interface | |
786 | */ | |
787 | static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) | |
788 | { | |
789 | struct spi_master *master = dev_id; | |
790 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
791 | u32 sr, mask = 0; | |
792 | unsigned long flags; | |
793 | bool end = false; | |
794 | ||
795 | spin_lock_irqsave(&spi->lock, flags); | |
796 | ||
797 | sr = readl_relaxed(spi->base + STM32F4_SPI_SR); | |
798 | /* | |
799 | * BSY flag is not handled in interrupt but it is normal behavior when | |
800 | * this flag is set. | |
801 | */ | |
802 | sr &= ~STM32F4_SPI_SR_BSY; | |
803 | ||
804 | if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || | |
805 | spi->cur_comm == SPI_3WIRE_TX)) { | |
806 | /* OVR flag shouldn't be handled for TX only mode */ | |
807 | sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE; | |
808 | mask |= STM32F4_SPI_SR_TXE; | |
809 | } | |
810 | ||
811 | if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { | |
812 | /* TXE flag is set and is handled when RXNE flag occurs */ | |
813 | sr &= ~STM32F4_SPI_SR_TXE; | |
814 | mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; | |
815 | } | |
816 | ||
817 | if (!(sr & mask)) { | |
818 | dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); | |
819 | spin_unlock_irqrestore(&spi->lock, flags); | |
820 | return IRQ_NONE; | |
821 | } | |
822 | ||
823 | if (sr & STM32F4_SPI_SR_OVR) { | |
824 | dev_warn(spi->dev, "Overrun: received value discarded\n"); | |
825 | ||
826 | /* Sequence to clear OVR flag */ | |
827 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
828 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
829 | ||
830 | /* | |
831 | * If overrun is detected, it means that something went wrong, | |
832 | * so stop the current transfer. Transfer can wait for next | |
833 | * RXNE but DR is already read and end never happens. | |
834 | */ | |
835 | end = true; | |
836 | goto end_irq; | |
837 | } | |
838 | ||
839 | if (sr & STM32F4_SPI_SR_TXE) { | |
840 | if (spi->tx_buf) | |
841 | stm32f4_spi_write_tx(spi); | |
842 | if (spi->tx_len == 0) | |
843 | end = true; | |
844 | } | |
845 | ||
846 | if (sr & STM32F4_SPI_SR_RXNE) { | |
847 | stm32f4_spi_read_rx(spi); | |
848 | if (spi->rx_len == 0) | |
849 | end = true; | |
850 | else /* Load data for discontinuous mode */ | |
851 | stm32f4_spi_write_tx(spi); | |
852 | } | |
853 | ||
854 | end_irq: | |
855 | if (end) { | |
856 | /* Immediately disable interrupts to do not generate new one */ | |
857 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, | |
858 | STM32F4_SPI_CR2_TXEIE | | |
859 | STM32F4_SPI_CR2_RXNEIE | | |
860 | STM32F4_SPI_CR2_ERRIE); | |
861 | spin_unlock_irqrestore(&spi->lock, flags); | |
862 | return IRQ_WAKE_THREAD; | |
863 | } | |
864 | ||
865 | spin_unlock_irqrestore(&spi->lock, flags); | |
866 | return IRQ_HANDLED; | |
867 | } | |
868 | ||
869 | /** | |
870 | * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller | |
871 | * @irq: interrupt line | |
872 | * @dev_id: SPI controller master interface | |
873 | */ | |
874 | static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id) | |
875 | { | |
876 | struct spi_master *master = dev_id; | |
877 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
878 | ||
879 | spi_finalize_current_transfer(master); | |
880 | stm32f4_spi_disable(spi); | |
881 | ||
882 | return IRQ_HANDLED; | |
dcbe0d84 AD |
883 | } |
884 | ||
885 | /** | |
55166853 | 886 | * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller |
dcbe0d84 AD |
887 | * @irq: interrupt line |
888 | * @dev_id: SPI controller master interface | |
889 | */ | |
55166853 | 890 | static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) |
dcbe0d84 AD |
891 | { |
892 | struct spi_master *master = dev_id; | |
893 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
894 | u32 sr, ier, mask; | |
895 | unsigned long flags; | |
896 | bool end = false; | |
897 | ||
898 | spin_lock_irqsave(&spi->lock, flags); | |
899 | ||
86026630 CG |
900 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
901 | ier = readl_relaxed(spi->base + STM32H7_SPI_IER); | |
dcbe0d84 AD |
902 | |
903 | mask = ier; | |
904 | /* EOTIE is triggered on EOT, SUSP and TXC events. */ | |
86026630 | 905 | mask |= STM32H7_SPI_SR_SUSP; |
dcbe0d84 AD |
906 | /* |
907 | * When TXTF is set, DXPIE and TXPIE are cleared. So in case of | |
908 | * Full-Duplex, need to poll RXP event to know if there are remaining | |
909 | * data, before disabling SPI. | |
910 | */ | |
128ebb89 | 911 | if (spi->rx_buf && !spi->cur_usedma) |
86026630 | 912 | mask |= STM32H7_SPI_SR_RXP; |
dcbe0d84 AD |
913 | |
914 | if (!(sr & mask)) { | |
915 | dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", | |
916 | sr, ier); | |
917 | spin_unlock_irqrestore(&spi->lock, flags); | |
918 | return IRQ_NONE; | |
919 | } | |
920 | ||
86026630 | 921 | if (sr & STM32H7_SPI_SR_SUSP) { |
dcbe0d84 AD |
922 | dev_warn(spi->dev, "Communication suspended\n"); |
923 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) | |
55166853 | 924 | stm32h7_spi_read_rxfifo(spi, false); |
c67ad368 AD |
925 | /* |
926 | * If communication is suspended while using DMA, it means | |
927 | * that something went wrong, so stop the current transfer | |
928 | */ | |
929 | if (spi->cur_usedma) | |
930 | end = true; | |
dcbe0d84 AD |
931 | } |
932 | ||
86026630 | 933 | if (sr & STM32H7_SPI_SR_MODF) { |
dcbe0d84 AD |
934 | dev_warn(spi->dev, "Mode fault: transfer aborted\n"); |
935 | end = true; | |
936 | } | |
937 | ||
86026630 | 938 | if (sr & STM32H7_SPI_SR_OVR) { |
dcbe0d84 AD |
939 | dev_warn(spi->dev, "Overrun: received value discarded\n"); |
940 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) | |
55166853 | 941 | stm32h7_spi_read_rxfifo(spi, false); |
c67ad368 AD |
942 | /* |
943 | * If overrun is detected while using DMA, it means that | |
944 | * something went wrong, so stop the current transfer | |
945 | */ | |
946 | if (spi->cur_usedma) | |
947 | end = true; | |
dcbe0d84 AD |
948 | } |
949 | ||
86026630 | 950 | if (sr & STM32H7_SPI_SR_EOT) { |
dcbe0d84 | 951 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 952 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 AD |
953 | end = true; |
954 | } | |
955 | ||
86026630 | 956 | if (sr & STM32H7_SPI_SR_TXP) |
dcbe0d84 | 957 | if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) |
55166853 | 958 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 959 | |
86026630 | 960 | if (sr & STM32H7_SPI_SR_RXP) |
dcbe0d84 | 961 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 962 | stm32h7_spi_read_rxfifo(spi, false); |
dcbe0d84 | 963 | |
86026630 | 964 | writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); |
dcbe0d84 AD |
965 | |
966 | spin_unlock_irqrestore(&spi->lock, flags); | |
967 | ||
968 | if (end) { | |
969 | spi_finalize_current_transfer(master); | |
55166853 | 970 | stm32h7_spi_disable(spi); |
dcbe0d84 AD |
971 | } |
972 | ||
973 | return IRQ_HANDLED; | |
974 | } | |
975 | ||
976 | /** | |
977 | * stm32_spi_setup - setup device chip select | |
978 | */ | |
979 | static int stm32_spi_setup(struct spi_device *spi_dev) | |
980 | { | |
981 | int ret = 0; | |
982 | ||
983 | if (!gpio_is_valid(spi_dev->cs_gpio)) { | |
984 | dev_err(&spi_dev->dev, "%d is not a valid gpio\n", | |
985 | spi_dev->cs_gpio); | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
989 | dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__, | |
990 | spi_dev->cs_gpio, | |
991 | (spi_dev->mode & SPI_CS_HIGH) ? "low" : "high"); | |
992 | ||
993 | ret = gpio_direction_output(spi_dev->cs_gpio, | |
994 | !(spi_dev->mode & SPI_CS_HIGH)); | |
995 | ||
996 | return ret; | |
997 | } | |
998 | ||
999 | /** | |
1000 | * stm32_spi_prepare_msg - set up the controller to transfer a single message | |
1001 | */ | |
1002 | static int stm32_spi_prepare_msg(struct spi_master *master, | |
1003 | struct spi_message *msg) | |
1004 | { | |
1005 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1006 | struct spi_device *spi_dev = msg->spi; | |
1007 | struct device_node *np = spi_dev->dev.of_node; | |
1008 | unsigned long flags; | |
55166853 | 1009 | u32 clrb = 0, setb = 0; |
dcbe0d84 AD |
1010 | |
1011 | /* SPI slave device may need time between data frames */ | |
1012 | spi->cur_midi = 0; | |
042c1c60 | 1013 | if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) |
dcbe0d84 AD |
1014 | dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); |
1015 | ||
1016 | if (spi_dev->mode & SPI_CPOL) | |
55166853 | 1017 | setb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 | 1018 | else |
55166853 | 1019 | clrb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 AD |
1020 | |
1021 | if (spi_dev->mode & SPI_CPHA) | |
55166853 | 1022 | setb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 | 1023 | else |
55166853 | 1024 | clrb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 AD |
1025 | |
1026 | if (spi_dev->mode & SPI_LSB_FIRST) | |
55166853 | 1027 | setb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 | 1028 | else |
55166853 | 1029 | clrb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 AD |
1030 | |
1031 | dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", | |
1032 | spi_dev->mode & SPI_CPOL, | |
1033 | spi_dev->mode & SPI_CPHA, | |
1034 | spi_dev->mode & SPI_LSB_FIRST, | |
1035 | spi_dev->mode & SPI_CS_HIGH); | |
1036 | ||
1037 | spin_lock_irqsave(&spi->lock, flags); | |
1038 | ||
55166853 CG |
1039 | /* CPOL, CPHA and LSB FIRST bits have common register */ |
1040 | if (clrb || setb) | |
dcbe0d84 | 1041 | writel_relaxed( |
55166853 CG |
1042 | (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & |
1043 | ~clrb) | setb, | |
1044 | spi->base + spi->cfg->regs->cpol.reg); | |
dcbe0d84 AD |
1045 | |
1046 | spin_unlock_irqrestore(&spi->lock, flags); | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
00505edf CG |
1051 | /** |
1052 | * stm32f4_spi_dma_tx_cb - dma callback | |
1053 | * | |
1054 | * DMA callback is called when the transfer is complete for DMA TX channel. | |
1055 | */ | |
1056 | static void stm32f4_spi_dma_tx_cb(void *data) | |
1057 | { | |
1058 | struct stm32_spi *spi = data; | |
1059 | ||
1060 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1061 | spi_finalize_current_transfer(spi->master); | |
1062 | stm32f4_spi_disable(spi); | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * stm32f4_spi_dma_rx_cb - dma callback | |
1068 | * | |
1069 | * DMA callback is called when the transfer is complete for DMA RX channel. | |
1070 | */ | |
1071 | static void stm32f4_spi_dma_rx_cb(void *data) | |
1072 | { | |
1073 | struct stm32_spi *spi = data; | |
1074 | ||
1075 | spi_finalize_current_transfer(spi->master); | |
1076 | stm32f4_spi_disable(spi); | |
1077 | } | |
1078 | ||
dcbe0d84 | 1079 | /** |
55166853 | 1080 | * stm32h7_spi_dma_cb - dma callback |
dcbe0d84 AD |
1081 | * |
1082 | * DMA callback is called when the transfer is complete or when an error | |
1083 | * occurs. If the transfer is complete, EOT flag is raised. | |
1084 | */ | |
55166853 | 1085 | static void stm32h7_spi_dma_cb(void *data) |
dcbe0d84 AD |
1086 | { |
1087 | struct stm32_spi *spi = data; | |
1088 | unsigned long flags; | |
1089 | u32 sr; | |
1090 | ||
1091 | spin_lock_irqsave(&spi->lock, flags); | |
1092 | ||
86026630 | 1093 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
dcbe0d84 AD |
1094 | |
1095 | spin_unlock_irqrestore(&spi->lock, flags); | |
1096 | ||
86026630 | 1097 | if (!(sr & STM32H7_SPI_SR_EOT)) |
c67ad368 | 1098 | dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); |
dcbe0d84 | 1099 | |
c67ad368 | 1100 | /* Now wait for EOT, or SUSP or OVR in case of error */ |
dcbe0d84 AD |
1101 | } |
1102 | ||
1103 | /** | |
1104 | * stm32_spi_dma_config - configure dma slave channel depending on current | |
1105 | * transfer bits_per_word. | |
1106 | */ | |
1107 | static void stm32_spi_dma_config(struct stm32_spi *spi, | |
1108 | struct dma_slave_config *dma_conf, | |
1109 | enum dma_transfer_direction dir) | |
1110 | { | |
1111 | enum dma_slave_buswidth buswidth; | |
1112 | u32 maxburst; | |
1113 | ||
128ebb89 AD |
1114 | if (spi->cur_bpw <= 8) |
1115 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1116 | else if (spi->cur_bpw <= 16) | |
1117 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1118 | else | |
1119 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
dcbe0d84 | 1120 | |
00505edf CG |
1121 | if (spi->cfg->has_fifo) { |
1122 | /* Valid for DMA Half or Full Fifo threshold */ | |
1123 | if (spi->cur_fthlv == 2) | |
1124 | maxburst = 1; | |
1125 | else | |
1126 | maxburst = spi->cur_fthlv; | |
1127 | } else { | |
128ebb89 | 1128 | maxburst = 1; |
00505edf | 1129 | } |
dcbe0d84 AD |
1130 | |
1131 | memset(dma_conf, 0, sizeof(struct dma_slave_config)); | |
1132 | dma_conf->direction = dir; | |
1133 | if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ | |
55166853 | 1134 | dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; |
dcbe0d84 AD |
1135 | dma_conf->src_addr_width = buswidth; |
1136 | dma_conf->src_maxburst = maxburst; | |
1137 | ||
1138 | dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", | |
1139 | buswidth, maxburst); | |
1140 | } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ | |
55166853 | 1141 | dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; |
dcbe0d84 AD |
1142 | dma_conf->dst_addr_width = buswidth; |
1143 | dma_conf->dst_maxburst = maxburst; | |
1144 | ||
1145 | dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", | |
1146 | buswidth, maxburst); | |
1147 | } | |
1148 | } | |
1149 | ||
00505edf CG |
1150 | /** |
1151 | * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using | |
1152 | * interrupts | |
1153 | * | |
1154 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1155 | * in progress. | |
1156 | */ | |
1157 | static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) | |
1158 | { | |
1159 | unsigned long flags; | |
1160 | u32 cr2 = 0; | |
1161 | ||
1162 | /* Enable the interrupts relative to the current communication mode */ | |
1163 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1164 | cr2 |= STM32F4_SPI_CR2_TXEIE; | |
1165 | } else if (spi->cur_comm == SPI_FULL_DUPLEX) { | |
1166 | /* In transmit-only mode, the OVR flag is set in the SR register | |
1167 | * since the received data are never read. Therefore set OVR | |
1168 | * interrupt only when rx buffer is available. | |
1169 | */ | |
1170 | cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE; | |
1171 | } else { | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | spin_lock_irqsave(&spi->lock, flags); | |
1176 | ||
1177 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); | |
1178 | ||
1179 | stm32_spi_enable(spi); | |
1180 | ||
1181 | /* starting data transfer when buffer is loaded */ | |
1182 | if (spi->tx_buf) | |
1183 | stm32f4_spi_write_tx(spi); | |
1184 | ||
1185 | spin_unlock_irqrestore(&spi->lock, flags); | |
1186 | ||
1187 | return 1; | |
1188 | } | |
1189 | ||
dcbe0d84 | 1190 | /** |
55166853 CG |
1191 | * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using |
1192 | * interrupts | |
dcbe0d84 AD |
1193 | * |
1194 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1195 | * in progress. | |
1196 | */ | |
55166853 | 1197 | static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) |
dcbe0d84 AD |
1198 | { |
1199 | unsigned long flags; | |
1200 | u32 ier = 0; | |
1201 | ||
1202 | /* Enable the interrupts relative to the current communication mode */ | |
1203 | if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ | |
86026630 | 1204 | ier |= STM32H7_SPI_IER_DXPIE; |
dcbe0d84 | 1205 | else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ |
86026630 | 1206 | ier |= STM32H7_SPI_IER_TXPIE; |
dcbe0d84 | 1207 | else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ |
86026630 | 1208 | ier |= STM32H7_SPI_IER_RXPIE; |
dcbe0d84 AD |
1209 | |
1210 | /* Enable the interrupts relative to the end of transfer */ | |
86026630 CG |
1211 | ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | |
1212 | STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; | |
dcbe0d84 AD |
1213 | |
1214 | spin_lock_irqsave(&spi->lock, flags); | |
1215 | ||
1216 | stm32_spi_enable(spi); | |
1217 | ||
1218 | /* Be sure to have data in fifo before starting data transfer */ | |
1219 | if (spi->tx_buf) | |
55166853 | 1220 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 1221 | |
86026630 | 1222 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); |
dcbe0d84 | 1223 | |
86026630 | 1224 | writel_relaxed(ier, spi->base + STM32H7_SPI_IER); |
dcbe0d84 AD |
1225 | |
1226 | spin_unlock_irqrestore(&spi->lock, flags); | |
1227 | ||
1228 | return 1; | |
1229 | } | |
1230 | ||
00505edf CG |
1231 | /** |
1232 | * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start | |
1233 | * transfer using DMA | |
1234 | */ | |
1235 | static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) | |
1236 | { | |
1237 | /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ | |
1238 | if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || | |
1239 | spi->cur_comm == SPI_FULL_DUPLEX) { | |
1240 | /* | |
1241 | * In transmit-only mode, the OVR flag is set in the SR register | |
1242 | * since the received data are never read. Therefore set OVR | |
1243 | * interrupt only when rx buffer is available. | |
1244 | */ | |
1245 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); | |
1246 | } | |
1247 | ||
1248 | stm32_spi_enable(spi); | |
1249 | } | |
1250 | ||
f8bb12f2 | 1251 | /** |
55166853 CG |
1252 | * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start |
1253 | * transfer using DMA | |
f8bb12f2 | 1254 | */ |
55166853 | 1255 | static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) |
f8bb12f2 CG |
1256 | { |
1257 | /* Enable the interrupts relative to the end of transfer */ | |
1258 | stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | | |
1259 | STM32H7_SPI_IER_TXTFIE | | |
1260 | STM32H7_SPI_IER_OVRIE | | |
1261 | STM32H7_SPI_IER_MODFIE); | |
1262 | ||
1263 | stm32_spi_enable(spi); | |
1264 | ||
1265 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); | |
1266 | } | |
1267 | ||
dcbe0d84 AD |
1268 | /** |
1269 | * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA | |
1270 | * | |
1271 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1272 | * in progress. | |
1273 | */ | |
1274 | static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, | |
1275 | struct spi_transfer *xfer) | |
1276 | { | |
1277 | struct dma_slave_config tx_dma_conf, rx_dma_conf; | |
1278 | struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; | |
1279 | unsigned long flags; | |
dcbe0d84 AD |
1280 | |
1281 | spin_lock_irqsave(&spi->lock, flags); | |
1282 | ||
1283 | rx_dma_desc = NULL; | |
2cbee7f8 | 1284 | if (spi->rx_buf && spi->dma_rx) { |
dcbe0d84 AD |
1285 | stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); |
1286 | dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); | |
1287 | ||
1288 | /* Enable Rx DMA request */ | |
55166853 CG |
1289 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1290 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1291 | |
1292 | rx_dma_desc = dmaengine_prep_slave_sg( | |
1293 | spi->dma_rx, xfer->rx_sg.sgl, | |
1294 | xfer->rx_sg.nents, | |
1295 | rx_dma_conf.direction, | |
1296 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1297 | } |
1298 | ||
1299 | tx_dma_desc = NULL; | |
2cbee7f8 | 1300 | if (spi->tx_buf && spi->dma_tx) { |
dcbe0d84 AD |
1301 | stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); |
1302 | dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); | |
1303 | ||
1304 | tx_dma_desc = dmaengine_prep_slave_sg( | |
1305 | spi->dma_tx, xfer->tx_sg.sgl, | |
1306 | xfer->tx_sg.nents, | |
1307 | tx_dma_conf.direction, | |
1308 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1309 | } |
1310 | ||
2cbee7f8 CG |
1311 | if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || |
1312 | (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) | |
1313 | goto dma_desc_error; | |
1314 | ||
1315 | if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) | |
dcbe0d84 AD |
1316 | goto dma_desc_error; |
1317 | ||
1318 | if (rx_dma_desc) { | |
55166853 | 1319 | rx_dma_desc->callback = spi->cfg->dma_rx_cb; |
7b821a64 AD |
1320 | rx_dma_desc->callback_param = spi; |
1321 | ||
dcbe0d84 AD |
1322 | if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { |
1323 | dev_err(spi->dev, "Rx DMA submit failed\n"); | |
1324 | goto dma_desc_error; | |
1325 | } | |
1326 | /* Enable Rx DMA channel */ | |
1327 | dma_async_issue_pending(spi->dma_rx); | |
1328 | } | |
1329 | ||
1330 | if (tx_dma_desc) { | |
9d5fce16 CG |
1331 | if (spi->cur_comm == SPI_SIMPLEX_TX || |
1332 | spi->cur_comm == SPI_3WIRE_TX) { | |
55166853 | 1333 | tx_dma_desc->callback = spi->cfg->dma_tx_cb; |
7b821a64 AD |
1334 | tx_dma_desc->callback_param = spi; |
1335 | } | |
1336 | ||
dcbe0d84 AD |
1337 | if (dma_submit_error(dmaengine_submit(tx_dma_desc))) { |
1338 | dev_err(spi->dev, "Tx DMA submit failed\n"); | |
1339 | goto dma_submit_error; | |
1340 | } | |
1341 | /* Enable Tx DMA channel */ | |
1342 | dma_async_issue_pending(spi->dma_tx); | |
1343 | ||
1344 | /* Enable Tx DMA request */ | |
55166853 CG |
1345 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, |
1346 | spi->cfg->regs->dma_tx_en.mask); | |
dcbe0d84 AD |
1347 | } |
1348 | ||
55166853 | 1349 | spi->cfg->transfer_one_dma_start(spi); |
dcbe0d84 AD |
1350 | |
1351 | spin_unlock_irqrestore(&spi->lock, flags); | |
1352 | ||
1353 | return 1; | |
1354 | ||
1355 | dma_submit_error: | |
2cbee7f8 | 1356 | if (spi->dma_rx) |
dcbe0d84 AD |
1357 | dmaengine_terminate_all(spi->dma_rx); |
1358 | ||
1359 | dma_desc_error: | |
55166853 CG |
1360 | stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1361 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1362 | |
1363 | spin_unlock_irqrestore(&spi->lock, flags); | |
1364 | ||
1365 | dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); | |
1366 | ||
2cbee7f8 | 1367 | spi->cur_usedma = false; |
55166853 | 1368 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1369 | } |
1370 | ||
00505edf CG |
1371 | /** |
1372 | * stm32f4_spi_set_bpw - Configure bits per word | |
1373 | * @spi: pointer to the spi controller data structure | |
1374 | */ | |
1375 | static void stm32f4_spi_set_bpw(struct stm32_spi *spi) | |
1376 | { | |
1377 | if (spi->cur_bpw == 16) | |
1378 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1379 | else | |
1380 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1381 | } | |
1382 | ||
dcbe0d84 | 1383 | /** |
55166853 | 1384 | * stm32h7_spi_set_bpw - configure bits per word |
9d5fce16 | 1385 | * @spi: pointer to the spi controller data structure |
dcbe0d84 | 1386 | */ |
55166853 | 1387 | static void stm32h7_spi_set_bpw(struct stm32_spi *spi) |
dcbe0d84 | 1388 | { |
9d5fce16 CG |
1389 | u32 bpw, fthlv; |
1390 | u32 cfg1_clrb = 0, cfg1_setb = 0; | |
dcbe0d84 | 1391 | |
9d5fce16 | 1392 | bpw = spi->cur_bpw - 1; |
dcbe0d84 | 1393 | |
9d5fce16 CG |
1394 | cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; |
1395 | cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & | |
1396 | STM32H7_SPI_CFG1_DSIZE; | |
dcbe0d84 | 1397 | |
55166853 | 1398 | spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi); |
9d5fce16 | 1399 | fthlv = spi->cur_fthlv - 1; |
dcbe0d84 | 1400 | |
9d5fce16 CG |
1401 | cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; |
1402 | cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & | |
1403 | STM32H7_SPI_CFG1_FTHLV; | |
dcbe0d84 | 1404 | |
9d5fce16 CG |
1405 | writel_relaxed( |
1406 | (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & | |
1407 | ~cfg1_clrb) | cfg1_setb, | |
1408 | spi->base + STM32H7_SPI_CFG1); | |
1409 | } | |
dcbe0d84 | 1410 | |
9d5fce16 CG |
1411 | /** |
1412 | * stm32_spi_set_mbr - Configure baud rate divisor in master mode | |
1413 | * @spi: pointer to the spi controller data structure | |
1414 | * @mbrdiv: baud rate divisor value | |
1415 | */ | |
1416 | static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) | |
1417 | { | |
55166853 | 1418 | u32 clrb = 0, setb = 0; |
dcbe0d84 | 1419 | |
55166853 CG |
1420 | clrb |= spi->cfg->regs->br.mask; |
1421 | setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & | |
1422 | spi->cfg->regs->br.mask; | |
dcbe0d84 | 1423 | |
55166853 CG |
1424 | writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & |
1425 | ~clrb) | setb, | |
1426 | spi->base + spi->cfg->regs->br.reg); | |
9d5fce16 | 1427 | } |
dcbe0d84 | 1428 | |
9d5fce16 CG |
1429 | /** |
1430 | * stm32_spi_communication_type - return transfer communication type | |
1431 | * @spi_dev: pointer to the spi device | |
1432 | * transfer: pointer to spi transfer | |
1433 | */ | |
1434 | static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev, | |
1435 | struct spi_transfer *transfer) | |
1436 | { | |
1437 | unsigned int type = SPI_FULL_DUPLEX; | |
dcbe0d84 | 1438 | |
dcbe0d84 AD |
1439 | if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ |
1440 | /* | |
1441 | * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL | |
9d5fce16 | 1442 | * is forbidden and unvalidated by SPI subsystem so depending |
dcbe0d84 AD |
1443 | * on the valid buffer, we can determine the direction of the |
1444 | * transfer. | |
1445 | */ | |
dcbe0d84 | 1446 | if (!transfer->tx_buf) |
9d5fce16 CG |
1447 | type = SPI_3WIRE_RX; |
1448 | else | |
1449 | type = SPI_3WIRE_TX; | |
dcbe0d84 AD |
1450 | } else { |
1451 | if (!transfer->tx_buf) | |
9d5fce16 | 1452 | type = SPI_SIMPLEX_RX; |
dcbe0d84 | 1453 | else if (!transfer->rx_buf) |
9d5fce16 | 1454 | type = SPI_SIMPLEX_TX; |
dcbe0d84 | 1455 | } |
dcbe0d84 | 1456 | |
9d5fce16 CG |
1457 | return type; |
1458 | } | |
1459 | ||
00505edf CG |
1460 | /** |
1461 | * stm32f4_spi_set_mode - configure communication mode | |
1462 | * @spi: pointer to the spi controller data structure | |
1463 | * @comm_type: type of communication to configure | |
1464 | */ | |
1465 | static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) | |
1466 | { | |
1467 | if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) { | |
1468 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, | |
1469 | STM32F4_SPI_CR1_BIDIMODE | | |
1470 | STM32F4_SPI_CR1_BIDIOE); | |
1471 | } else if (comm_type == SPI_FULL_DUPLEX) { | |
1472 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, | |
1473 | STM32F4_SPI_CR1_BIDIMODE | | |
1474 | STM32F4_SPI_CR1_BIDIOE); | |
1475 | } else { | |
1476 | return -EINVAL; | |
1477 | } | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
9d5fce16 | 1482 | /** |
55166853 | 1483 | * stm32h7_spi_set_mode - configure communication mode |
9d5fce16 CG |
1484 | * @spi: pointer to the spi controller data structure |
1485 | * @comm_type: type of communication to configure | |
1486 | */ | |
55166853 | 1487 | static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) |
9d5fce16 CG |
1488 | { |
1489 | u32 mode; | |
1490 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1491 | ||
1492 | if (comm_type == SPI_3WIRE_RX) { | |
1493 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1494 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1495 | } else if (comm_type == SPI_3WIRE_TX) { | |
1496 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1497 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1498 | } else if (comm_type == SPI_SIMPLEX_RX) { | |
1499 | mode = STM32H7_SPI_SIMPLEX_RX; | |
1500 | } else if (comm_type == SPI_SIMPLEX_TX) { | |
1501 | mode = STM32H7_SPI_SIMPLEX_TX; | |
1502 | } else { | |
1503 | mode = STM32H7_SPI_FULL_DUPLEX; | |
dcbe0d84 AD |
1504 | } |
1505 | ||
9d5fce16 CG |
1506 | cfg2_clrb |= STM32H7_SPI_CFG2_COMM; |
1507 | cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & | |
1508 | STM32H7_SPI_CFG2_COMM; | |
1509 | ||
1510 | writel_relaxed( | |
1511 | (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & | |
1512 | ~cfg2_clrb) | cfg2_setb, | |
1513 | spi->base + STM32H7_SPI_CFG2); | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
1518 | /** | |
55166853 CG |
1519 | * stm32h7_spi_data_idleness - configure minimum time delay inserted between two |
1520 | * consecutive data frames in master mode | |
9d5fce16 CG |
1521 | * @spi: pointer to the spi controller data structure |
1522 | * @len: transfer len | |
1523 | */ | |
55166853 | 1524 | static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) |
9d5fce16 CG |
1525 | { |
1526 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1527 | ||
86026630 | 1528 | cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; |
9d5fce16 | 1529 | if ((len > 1) && (spi->cur_midi > 0)) { |
dcbe0d84 AD |
1530 | u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); |
1531 | u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), | |
86026630 CG |
1532 | (u32)STM32H7_SPI_CFG2_MIDI >> |
1533 | STM32H7_SPI_CFG2_MIDI_SHIFT); | |
dcbe0d84 AD |
1534 | |
1535 | dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", | |
1536 | sck_period_ns, midi, midi * sck_period_ns); | |
86026630 CG |
1537 | cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & |
1538 | STM32H7_SPI_CFG2_MIDI; | |
dcbe0d84 AD |
1539 | } |
1540 | ||
9d5fce16 CG |
1541 | writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & |
1542 | ~cfg2_clrb) | cfg2_setb, | |
1543 | spi->base + STM32H7_SPI_CFG2); | |
1544 | } | |
1545 | ||
1546 | /** | |
55166853 | 1547 | * stm32h7_spi_number_of_data - configure number of data at current transfer |
9d5fce16 CG |
1548 | * @spi: pointer to the spi controller data structure |
1549 | * @len: transfer length | |
1550 | */ | |
55166853 | 1551 | static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) |
9d5fce16 CG |
1552 | { |
1553 | u32 cr2_clrb = 0, cr2_setb = 0; | |
1554 | ||
1555 | if (nb_words <= (STM32H7_SPI_CR2_TSIZE >> | |
1556 | STM32H7_SPI_CR2_TSIZE_SHIFT)) { | |
1557 | cr2_clrb |= STM32H7_SPI_CR2_TSIZE; | |
1558 | cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT; | |
1559 | writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & | |
1560 | ~cr2_clrb) | cr2_setb, | |
1561 | spi->base + STM32H7_SPI_CR2); | |
1562 | } else { | |
1563 | return -EMSGSIZE; | |
1564 | } | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | /** | |
1570 | * stm32_spi_transfer_one_setup - common setup to transfer a single | |
1571 | * spi_transfer either using DMA or | |
1572 | * interrupts. | |
1573 | */ | |
1574 | static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, | |
1575 | struct spi_device *spi_dev, | |
1576 | struct spi_transfer *transfer) | |
1577 | { | |
1578 | unsigned long flags; | |
1579 | unsigned int comm_type; | |
1580 | int nb_words, ret = 0; | |
1581 | ||
1582 | spin_lock_irqsave(&spi->lock, flags); | |
1583 | ||
1584 | if (spi->cur_bpw != transfer->bits_per_word) { | |
1585 | spi->cur_bpw = transfer->bits_per_word; | |
55166853 | 1586 | spi->cfg->set_bpw(spi); |
9d5fce16 CG |
1587 | } |
1588 | ||
1589 | if (spi->cur_speed != transfer->speed_hz) { | |
1590 | int mbr; | |
1591 | ||
1592 | /* Update spi->cur_speed with real clock speed */ | |
1593 | mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, | |
55166853 CG |
1594 | spi->cfg->baud_rate_div_min, |
1595 | spi->cfg->baud_rate_div_max); | |
9d5fce16 CG |
1596 | if (mbr < 0) { |
1597 | ret = mbr; | |
1598 | goto out; | |
1599 | } | |
1600 | ||
1601 | transfer->speed_hz = spi->cur_speed; | |
1602 | stm32_spi_set_mbr(spi, mbr); | |
1603 | } | |
1604 | ||
1605 | comm_type = stm32_spi_communication_type(spi_dev, transfer); | |
1606 | if (spi->cur_comm != comm_type) { | |
55166853 | 1607 | ret = spi->cfg->set_mode(spi, comm_type); |
9d5fce16 CG |
1608 | |
1609 | if (ret < 0) | |
1610 | goto out; | |
1611 | ||
1612 | spi->cur_comm = comm_type; | |
1613 | } | |
1614 | ||
55166853 CG |
1615 | if (spi->cfg->set_data_idleness) |
1616 | spi->cfg->set_data_idleness(spi, transfer->len); | |
dcbe0d84 | 1617 | |
128ebb89 AD |
1618 | if (spi->cur_bpw <= 8) |
1619 | nb_words = transfer->len; | |
1620 | else if (spi->cur_bpw <= 16) | |
1621 | nb_words = DIV_ROUND_UP(transfer->len * 8, 16); | |
1622 | else | |
1623 | nb_words = DIV_ROUND_UP(transfer->len * 8, 32); | |
dcbe0d84 | 1624 | |
55166853 CG |
1625 | if (spi->cfg->set_number_of_data) { |
1626 | ret = spi->cfg->set_number_of_data(spi, nb_words); | |
1627 | if (ret < 0) | |
1628 | goto out; | |
1629 | } | |
dcbe0d84 AD |
1630 | |
1631 | spi->cur_xferlen = transfer->len; | |
1632 | ||
1633 | dev_dbg(spi->dev, "transfer communication mode set to %d\n", | |
1634 | spi->cur_comm); | |
1635 | dev_dbg(spi->dev, | |
1636 | "data frame of %d-bit, data packet of %d data frames\n", | |
1637 | spi->cur_bpw, spi->cur_fthlv); | |
1638 | dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); | |
1639 | dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", | |
1640 | spi->cur_xferlen, nb_words); | |
1641 | dev_dbg(spi->dev, "dma %s\n", | |
1642 | (spi->cur_usedma) ? "enabled" : "disabled"); | |
1643 | ||
1644 | out: | |
1645 | spin_unlock_irqrestore(&spi->lock, flags); | |
1646 | ||
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | /** | |
1651 | * stm32_spi_transfer_one - transfer a single spi_transfer | |
1652 | * | |
1653 | * It must return 0 if the transfer is finished or 1 if the transfer is still | |
1654 | * in progress. | |
1655 | */ | |
1656 | static int stm32_spi_transfer_one(struct spi_master *master, | |
1657 | struct spi_device *spi_dev, | |
1658 | struct spi_transfer *transfer) | |
1659 | { | |
1660 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1661 | int ret; | |
1662 | ||
1663 | spi->tx_buf = transfer->tx_buf; | |
1664 | spi->rx_buf = transfer->rx_buf; | |
1665 | spi->tx_len = spi->tx_buf ? transfer->len : 0; | |
1666 | spi->rx_len = spi->rx_buf ? transfer->len : 0; | |
1667 | ||
c67ad368 | 1668 | spi->cur_usedma = (master->can_dma && |
2cbee7f8 | 1669 | master->can_dma(master, spi_dev, transfer)); |
dcbe0d84 AD |
1670 | |
1671 | ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); | |
1672 | if (ret) { | |
1673 | dev_err(spi->dev, "SPI transfer setup failed\n"); | |
1674 | return ret; | |
1675 | } | |
1676 | ||
1677 | if (spi->cur_usedma) | |
1678 | return stm32_spi_transfer_one_dma(spi, transfer); | |
1679 | else | |
55166853 | 1680 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1681 | } |
1682 | ||
1683 | /** | |
1684 | * stm32_spi_unprepare_msg - relax the hardware | |
dcbe0d84 AD |
1685 | */ |
1686 | static int stm32_spi_unprepare_msg(struct spi_master *master, | |
1687 | struct spi_message *msg) | |
1688 | { | |
1689 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1690 | ||
55166853 | 1691 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1692 | |
1693 | return 0; | |
1694 | } | |
1695 | ||
00505edf CG |
1696 | /** |
1697 | * stm32f4_spi_config - Configure SPI controller as SPI master | |
1698 | */ | |
1699 | static int stm32f4_spi_config(struct stm32_spi *spi) | |
1700 | { | |
1701 | unsigned long flags; | |
1702 | ||
1703 | spin_lock_irqsave(&spi->lock, flags); | |
1704 | ||
1705 | /* Ensure I2SMOD bit is kept cleared */ | |
1706 | stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, | |
1707 | STM32F4_SPI_I2SCFGR_I2SMOD); | |
1708 | ||
1709 | /* | |
1710 | * - SS input value high | |
1711 | * - transmitter half duplex direction | |
1712 | * - Set the master mode (default Motorola mode) | |
1713 | * - Consider 1 master/n slaves configuration and | |
1714 | * SS input value is determined by the SSI bit | |
1715 | */ | |
1716 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | | |
1717 | STM32F4_SPI_CR1_BIDIOE | | |
1718 | STM32F4_SPI_CR1_MSTR | | |
1719 | STM32F4_SPI_CR1_SSM); | |
1720 | ||
1721 | spin_unlock_irqrestore(&spi->lock, flags); | |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
dcbe0d84 | 1726 | /** |
55166853 | 1727 | * stm32h7_spi_config - Configure SPI controller as SPI master |
dcbe0d84 | 1728 | */ |
55166853 | 1729 | static int stm32h7_spi_config(struct stm32_spi *spi) |
dcbe0d84 AD |
1730 | { |
1731 | unsigned long flags; | |
1732 | ||
1733 | spin_lock_irqsave(&spi->lock, flags); | |
1734 | ||
1735 | /* Ensure I2SMOD bit is kept cleared */ | |
86026630 CG |
1736 | stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, |
1737 | STM32H7_SPI_I2SCFGR_I2SMOD); | |
dcbe0d84 AD |
1738 | |
1739 | /* | |
1740 | * - SS input value high | |
1741 | * - transmitter half duplex direction | |
1742 | * - automatic communication suspend when RX-Fifo is full | |
1743 | */ | |
86026630 CG |
1744 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | |
1745 | STM32H7_SPI_CR1_HDDIR | | |
1746 | STM32H7_SPI_CR1_MASRX); | |
dcbe0d84 AD |
1747 | |
1748 | /* | |
1749 | * - Set the master mode (default Motorola mode) | |
1750 | * - Consider 1 master/n slaves configuration and | |
1751 | * SS input value is determined by the SSI bit | |
1752 | * - keep control of all associated GPIOs | |
1753 | */ | |
86026630 CG |
1754 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | |
1755 | STM32H7_SPI_CFG2_SSM | | |
1756 | STM32H7_SPI_CFG2_AFCNTR); | |
dcbe0d84 AD |
1757 | |
1758 | spin_unlock_irqrestore(&spi->lock, flags); | |
1759 | ||
1760 | return 0; | |
1761 | } | |
1762 | ||
00505edf CG |
1763 | static const struct stm32_spi_cfg stm32f4_spi_cfg = { |
1764 | .regs = &stm32f4_spi_regspec, | |
1765 | .get_bpw_mask = stm32f4_spi_get_bpw_mask, | |
1766 | .disable = stm32f4_spi_disable, | |
1767 | .config = stm32f4_spi_config, | |
1768 | .set_bpw = stm32f4_spi_set_bpw, | |
1769 | .set_mode = stm32f4_spi_set_mode, | |
1770 | .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start, | |
1771 | .dma_tx_cb = stm32f4_spi_dma_tx_cb, | |
1772 | .dma_rx_cb = stm32f4_spi_dma_rx_cb, | |
1773 | .transfer_one_irq = stm32f4_spi_transfer_one_irq, | |
1774 | .irq_handler_event = stm32f4_spi_irq_event, | |
1775 | .irq_handler_thread = stm32f4_spi_irq_thread, | |
1776 | .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN, | |
1777 | .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX, | |
1778 | .has_fifo = false, | |
1779 | }; | |
1780 | ||
55166853 CG |
1781 | static const struct stm32_spi_cfg stm32h7_spi_cfg = { |
1782 | .regs = &stm32h7_spi_regspec, | |
1783 | .get_fifo_size = stm32h7_spi_get_fifo_size, | |
1784 | .get_bpw_mask = stm32h7_spi_get_bpw_mask, | |
1785 | .disable = stm32h7_spi_disable, | |
1786 | .config = stm32h7_spi_config, | |
1787 | .set_bpw = stm32h7_spi_set_bpw, | |
1788 | .set_mode = stm32h7_spi_set_mode, | |
1789 | .set_data_idleness = stm32h7_spi_data_idleness, | |
1790 | .set_number_of_data = stm32h7_spi_number_of_data, | |
1791 | .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start, | |
1792 | .dma_rx_cb = stm32h7_spi_dma_cb, | |
1793 | .dma_tx_cb = stm32h7_spi_dma_cb, | |
1794 | .transfer_one_irq = stm32h7_spi_transfer_one_irq, | |
1795 | .irq_handler_thread = stm32h7_spi_irq_thread, | |
1796 | .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN, | |
1797 | .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX, | |
1798 | .has_fifo = true, | |
1799 | }; | |
1800 | ||
dcbe0d84 | 1801 | static const struct of_device_id stm32_spi_of_match[] = { |
55166853 | 1802 | { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg }, |
00505edf | 1803 | { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg }, |
dcbe0d84 AD |
1804 | {}, |
1805 | }; | |
1806 | MODULE_DEVICE_TABLE(of, stm32_spi_of_match); | |
1807 | ||
1808 | static int stm32_spi_probe(struct platform_device *pdev) | |
1809 | { | |
1810 | struct spi_master *master; | |
1811 | struct stm32_spi *spi; | |
1812 | struct resource *res; | |
1813 | int i, ret; | |
1814 | ||
1815 | master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); | |
1816 | if (!master) { | |
1817 | dev_err(&pdev->dev, "spi master allocation failed\n"); | |
1818 | return -ENOMEM; | |
1819 | } | |
1820 | platform_set_drvdata(pdev, master); | |
1821 | ||
1822 | spi = spi_master_get_devdata(master); | |
1823 | spi->dev = &pdev->dev; | |
1824 | spi->master = master; | |
1825 | spin_lock_init(&spi->lock); | |
1826 | ||
55166853 CG |
1827 | spi->cfg = (const struct stm32_spi_cfg *) |
1828 | of_match_device(pdev->dev.driver->of_match_table, | |
1829 | &pdev->dev)->data; | |
1830 | ||
dcbe0d84 AD |
1831 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1832 | spi->base = devm_ioremap_resource(&pdev->dev, res); | |
1833 | if (IS_ERR(spi->base)) { | |
1834 | ret = PTR_ERR(spi->base); | |
1835 | goto err_master_put; | |
1836 | } | |
55166853 | 1837 | |
dcbe0d84 AD |
1838 | spi->phys_addr = (dma_addr_t)res->start; |
1839 | ||
1840 | spi->irq = platform_get_irq(pdev, 0); | |
1841 | if (spi->irq <= 0) { | |
8d1467a6 FD |
1842 | ret = spi->irq; |
1843 | if (ret != -EPROBE_DEFER) | |
1844 | dev_err(&pdev->dev, "failed to get irq: %d\n", ret); | |
dcbe0d84 AD |
1845 | goto err_master_put; |
1846 | } | |
55166853 CG |
1847 | ret = devm_request_threaded_irq(&pdev->dev, spi->irq, |
1848 | spi->cfg->irq_handler_event, | |
1849 | spi->cfg->irq_handler_thread, | |
1850 | IRQF_ONESHOT, pdev->name, master); | |
dcbe0d84 AD |
1851 | if (ret) { |
1852 | dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, | |
1853 | ret); | |
1854 | goto err_master_put; | |
1855 | } | |
1856 | ||
d4c9134a | 1857 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
dcbe0d84 AD |
1858 | if (IS_ERR(spi->clk)) { |
1859 | ret = PTR_ERR(spi->clk); | |
1860 | dev_err(&pdev->dev, "clk get failed: %d\n", ret); | |
1861 | goto err_master_put; | |
1862 | } | |
1863 | ||
1864 | ret = clk_prepare_enable(spi->clk); | |
1865 | if (ret) { | |
1866 | dev_err(&pdev->dev, "clk enable failed: %d\n", ret); | |
1867 | goto err_master_put; | |
1868 | } | |
1869 | spi->clk_rate = clk_get_rate(spi->clk); | |
1870 | if (!spi->clk_rate) { | |
1871 | dev_err(&pdev->dev, "clk rate = 0\n"); | |
1872 | ret = -EINVAL; | |
3dbb3eef | 1873 | goto err_clk_disable; |
dcbe0d84 AD |
1874 | } |
1875 | ||
d5e9a4a4 | 1876 | spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
dcbe0d84 AD |
1877 | if (!IS_ERR(spi->rst)) { |
1878 | reset_control_assert(spi->rst); | |
1879 | udelay(2); | |
1880 | reset_control_deassert(spi->rst); | |
1881 | } | |
1882 | ||
55166853 CG |
1883 | if (spi->cfg->has_fifo) |
1884 | spi->fifo_size = spi->cfg->get_fifo_size(spi); | |
dcbe0d84 | 1885 | |
55166853 | 1886 | ret = spi->cfg->config(spi); |
dcbe0d84 AD |
1887 | if (ret) { |
1888 | dev_err(&pdev->dev, "controller configuration failed: %d\n", | |
1889 | ret); | |
1890 | goto err_clk_disable; | |
1891 | } | |
1892 | ||
1893 | master->dev.of_node = pdev->dev.of_node; | |
1894 | master->auto_runtime_pm = true; | |
1895 | master->bus_num = pdev->id; | |
d6cea11b | 1896 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | |
6962b055 | 1897 | SPI_3WIRE; |
55166853 CG |
1898 | master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); |
1899 | master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; | |
1900 | master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; | |
dcbe0d84 AD |
1901 | master->setup = stm32_spi_setup; |
1902 | master->prepare_message = stm32_spi_prepare_msg; | |
1903 | master->transfer_one = stm32_spi_transfer_one; | |
1904 | master->unprepare_message = stm32_spi_unprepare_msg; | |
1905 | ||
1906 | spi->dma_tx = dma_request_slave_channel(spi->dev, "tx"); | |
1907 | if (!spi->dma_tx) | |
1908 | dev_warn(&pdev->dev, "failed to request tx dma channel\n"); | |
1909 | else | |
1910 | master->dma_tx = spi->dma_tx; | |
1911 | ||
1912 | spi->dma_rx = dma_request_slave_channel(spi->dev, "rx"); | |
1913 | if (!spi->dma_rx) | |
1914 | dev_warn(&pdev->dev, "failed to request rx dma channel\n"); | |
1915 | else | |
1916 | master->dma_rx = spi->dma_rx; | |
1917 | ||
1918 | if (spi->dma_tx || spi->dma_rx) | |
1919 | master->can_dma = stm32_spi_can_dma; | |
1920 | ||
038ac869 AD |
1921 | pm_runtime_set_active(&pdev->dev); |
1922 | pm_runtime_enable(&pdev->dev); | |
1923 | ||
dcbe0d84 AD |
1924 | ret = devm_spi_register_master(&pdev->dev, master); |
1925 | if (ret) { | |
1926 | dev_err(&pdev->dev, "spi master registration failed: %d\n", | |
1927 | ret); | |
1928 | goto err_dma_release; | |
1929 | } | |
1930 | ||
1931 | if (!master->cs_gpios) { | |
1932 | dev_err(&pdev->dev, "no CS gpios available\n"); | |
1933 | ret = -EINVAL; | |
1934 | goto err_dma_release; | |
1935 | } | |
1936 | ||
1937 | for (i = 0; i < master->num_chipselect; i++) { | |
1938 | if (!gpio_is_valid(master->cs_gpios[i])) { | |
1939 | dev_err(&pdev->dev, "%i is not a valid gpio\n", | |
1940 | master->cs_gpios[i]); | |
1941 | ret = -EINVAL; | |
1942 | goto err_dma_release; | |
1943 | } | |
1944 | ||
1945 | ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], | |
1946 | DRIVER_NAME); | |
1947 | if (ret) { | |
1948 | dev_err(&pdev->dev, "can't get CS gpio %i\n", | |
1949 | master->cs_gpios[i]); | |
1950 | goto err_dma_release; | |
1951 | } | |
1952 | } | |
1953 | ||
1954 | dev_info(&pdev->dev, "driver initialized\n"); | |
1955 | ||
1956 | return 0; | |
1957 | ||
1958 | err_dma_release: | |
1959 | if (spi->dma_tx) | |
1960 | dma_release_channel(spi->dma_tx); | |
1961 | if (spi->dma_rx) | |
1962 | dma_release_channel(spi->dma_rx); | |
038ac869 AD |
1963 | |
1964 | pm_runtime_disable(&pdev->dev); | |
dcbe0d84 AD |
1965 | err_clk_disable: |
1966 | clk_disable_unprepare(spi->clk); | |
1967 | err_master_put: | |
1968 | spi_master_put(master); | |
1969 | ||
1970 | return ret; | |
1971 | } | |
1972 | ||
1973 | static int stm32_spi_remove(struct platform_device *pdev) | |
1974 | { | |
1975 | struct spi_master *master = platform_get_drvdata(pdev); | |
1976 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1977 | ||
55166853 | 1978 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1979 | |
1980 | if (master->dma_tx) | |
1981 | dma_release_channel(master->dma_tx); | |
1982 | if (master->dma_rx) | |
1983 | dma_release_channel(master->dma_rx); | |
1984 | ||
1985 | clk_disable_unprepare(spi->clk); | |
1986 | ||
038ac869 AD |
1987 | pm_runtime_disable(&pdev->dev); |
1988 | ||
dcbe0d84 AD |
1989 | return 0; |
1990 | } | |
1991 | ||
038ac869 AD |
1992 | #ifdef CONFIG_PM |
1993 | static int stm32_spi_runtime_suspend(struct device *dev) | |
1994 | { | |
1995 | struct spi_master *master = dev_get_drvdata(dev); | |
1996 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1997 | ||
1998 | clk_disable_unprepare(spi->clk); | |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | ||
2003 | static int stm32_spi_runtime_resume(struct device *dev) | |
2004 | { | |
2005 | struct spi_master *master = dev_get_drvdata(dev); | |
2006 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
2007 | ||
2008 | return clk_prepare_enable(spi->clk); | |
2009 | } | |
2010 | #endif | |
2011 | ||
dcbe0d84 AD |
2012 | #ifdef CONFIG_PM_SLEEP |
2013 | static int stm32_spi_suspend(struct device *dev) | |
2014 | { | |
2015 | struct spi_master *master = dev_get_drvdata(dev); | |
dcbe0d84 AD |
2016 | int ret; |
2017 | ||
2018 | ret = spi_master_suspend(master); | |
2019 | if (ret) | |
2020 | return ret; | |
2021 | ||
038ac869 | 2022 | return pm_runtime_force_suspend(dev); |
dcbe0d84 AD |
2023 | } |
2024 | ||
2025 | static int stm32_spi_resume(struct device *dev) | |
2026 | { | |
2027 | struct spi_master *master = dev_get_drvdata(dev); | |
2028 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
2029 | int ret; | |
2030 | ||
038ac869 | 2031 | ret = pm_runtime_force_resume(dev); |
dcbe0d84 AD |
2032 | if (ret) |
2033 | return ret; | |
038ac869 | 2034 | |
dcbe0d84 AD |
2035 | ret = spi_master_resume(master); |
2036 | if (ret) | |
2037 | clk_disable_unprepare(spi->clk); | |
2038 | ||
2039 | return ret; | |
2040 | } | |
2041 | #endif | |
2042 | ||
038ac869 AD |
2043 | static const struct dev_pm_ops stm32_spi_pm_ops = { |
2044 | SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) | |
2045 | SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, | |
2046 | stm32_spi_runtime_resume, NULL) | |
2047 | }; | |
dcbe0d84 AD |
2048 | |
2049 | static struct platform_driver stm32_spi_driver = { | |
2050 | .probe = stm32_spi_probe, | |
2051 | .remove = stm32_spi_remove, | |
2052 | .driver = { | |
2053 | .name = DRIVER_NAME, | |
2054 | .pm = &stm32_spi_pm_ops, | |
2055 | .of_match_table = stm32_spi_of_match, | |
2056 | }, | |
2057 | }; | |
2058 | ||
2059 | module_platform_driver(stm32_spi_driver); | |
2060 | ||
2061 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2062 | MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); | |
2063 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); | |
2064 | MODULE_LICENSE("GPL v2"); |