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d57a984f CG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // STMicroelectronics STM32 SPI Controller driver (master mode only) | |
4 | // | |
5 | // Copyright (C) 2017, STMicroelectronics - All Rights Reserved | |
6 | // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics. | |
7 | ||
5a380b83 | 8 | #include <linux/bitfield.h> |
dcbe0d84 AD |
9 | #include <linux/debugfs.h> |
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/dmaengine.h> | |
dcbe0d84 AD |
13 | #include <linux/interrupt.h> |
14 | #include <linux/iopoll.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of_platform.h> | |
db96bf97 | 17 | #include <linux/pinctrl/consumer.h> |
038ac869 | 18 | #include <linux/pm_runtime.h> |
dcbe0d84 AD |
19 | #include <linux/reset.h> |
20 | #include <linux/spi/spi.h> | |
21 | ||
22 | #define DRIVER_NAME "spi_stm32" | |
23 | ||
00505edf CG |
24 | /* STM32F4 SPI registers */ |
25 | #define STM32F4_SPI_CR1 0x00 | |
26 | #define STM32F4_SPI_CR2 0x04 | |
27 | #define STM32F4_SPI_SR 0x08 | |
28 | #define STM32F4_SPI_DR 0x0C | |
29 | #define STM32F4_SPI_I2SCFGR 0x1C | |
30 | ||
31 | /* STM32F4_SPI_CR1 bit fields */ | |
32 | #define STM32F4_SPI_CR1_CPHA BIT(0) | |
33 | #define STM32F4_SPI_CR1_CPOL BIT(1) | |
34 | #define STM32F4_SPI_CR1_MSTR BIT(2) | |
35 | #define STM32F4_SPI_CR1_BR_SHIFT 3 | |
36 | #define STM32F4_SPI_CR1_BR GENMASK(5, 3) | |
37 | #define STM32F4_SPI_CR1_SPE BIT(6) | |
38 | #define STM32F4_SPI_CR1_LSBFRST BIT(7) | |
39 | #define STM32F4_SPI_CR1_SSI BIT(8) | |
40 | #define STM32F4_SPI_CR1_SSM BIT(9) | |
41 | #define STM32F4_SPI_CR1_RXONLY BIT(10) | |
42 | #define STM32F4_SPI_CR1_DFF BIT(11) | |
43 | #define STM32F4_SPI_CR1_CRCNEXT BIT(12) | |
44 | #define STM32F4_SPI_CR1_CRCEN BIT(13) | |
45 | #define STM32F4_SPI_CR1_BIDIOE BIT(14) | |
46 | #define STM32F4_SPI_CR1_BIDIMODE BIT(15) | |
47 | #define STM32F4_SPI_CR1_BR_MIN 0 | |
48 | #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3) | |
49 | ||
50 | /* STM32F4_SPI_CR2 bit fields */ | |
51 | #define STM32F4_SPI_CR2_RXDMAEN BIT(0) | |
52 | #define STM32F4_SPI_CR2_TXDMAEN BIT(1) | |
53 | #define STM32F4_SPI_CR2_SSOE BIT(2) | |
54 | #define STM32F4_SPI_CR2_FRF BIT(4) | |
55 | #define STM32F4_SPI_CR2_ERRIE BIT(5) | |
56 | #define STM32F4_SPI_CR2_RXNEIE BIT(6) | |
57 | #define STM32F4_SPI_CR2_TXEIE BIT(7) | |
58 | ||
59 | /* STM32F4_SPI_SR bit fields */ | |
60 | #define STM32F4_SPI_SR_RXNE BIT(0) | |
61 | #define STM32F4_SPI_SR_TXE BIT(1) | |
62 | #define STM32F4_SPI_SR_CHSIDE BIT(2) | |
63 | #define STM32F4_SPI_SR_UDR BIT(3) | |
64 | #define STM32F4_SPI_SR_CRCERR BIT(4) | |
65 | #define STM32F4_SPI_SR_MODF BIT(5) | |
66 | #define STM32F4_SPI_SR_OVR BIT(6) | |
67 | #define STM32F4_SPI_SR_BSY BIT(7) | |
68 | #define STM32F4_SPI_SR_FRE BIT(8) | |
69 | ||
70 | /* STM32F4_SPI_I2SCFGR bit fields */ | |
71 | #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11) | |
72 | ||
73 | /* STM32F4 SPI Baud Rate min/max divisor */ | |
74 | #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN) | |
75 | #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX) | |
76 | ||
86026630 CG |
77 | /* STM32H7 SPI registers */ |
78 | #define STM32H7_SPI_CR1 0x00 | |
79 | #define STM32H7_SPI_CR2 0x04 | |
80 | #define STM32H7_SPI_CFG1 0x08 | |
81 | #define STM32H7_SPI_CFG2 0x0C | |
82 | #define STM32H7_SPI_IER 0x10 | |
83 | #define STM32H7_SPI_SR 0x14 | |
84 | #define STM32H7_SPI_IFCR 0x18 | |
85 | #define STM32H7_SPI_TXDR 0x20 | |
86 | #define STM32H7_SPI_RXDR 0x30 | |
87 | #define STM32H7_SPI_I2SCFGR 0x50 | |
88 | ||
89 | /* STM32H7_SPI_CR1 bit fields */ | |
90 | #define STM32H7_SPI_CR1_SPE BIT(0) | |
91 | #define STM32H7_SPI_CR1_MASRX BIT(8) | |
92 | #define STM32H7_SPI_CR1_CSTART BIT(9) | |
93 | #define STM32H7_SPI_CR1_CSUSP BIT(10) | |
94 | #define STM32H7_SPI_CR1_HDDIR BIT(11) | |
95 | #define STM32H7_SPI_CR1_SSI BIT(12) | |
96 | ||
97 | /* STM32H7_SPI_CR2 bit fields */ | |
86026630 | 98 | #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) |
5a380b83 | 99 | #define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0) |
86026630 CG |
100 | |
101 | /* STM32H7_SPI_CFG1 bit fields */ | |
86026630 | 102 | #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) |
86026630 CG |
103 | #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) |
104 | #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) | |
105 | #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) | |
86026630 | 106 | #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) |
5a380b83 | 107 | #define STM32H7_SPI_CFG1_MBR_SHIFT 28 |
86026630 CG |
108 | #define STM32H7_SPI_CFG1_MBR_MIN 0 |
109 | #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) | |
110 | ||
111 | /* STM32H7_SPI_CFG2 bit fields */ | |
86026630 | 112 | #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) |
86026630 | 113 | #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) |
86026630 CG |
114 | #define STM32H7_SPI_CFG2_SP GENMASK(21, 19) |
115 | #define STM32H7_SPI_CFG2_MASTER BIT(22) | |
116 | #define STM32H7_SPI_CFG2_LSBFRST BIT(23) | |
117 | #define STM32H7_SPI_CFG2_CPHA BIT(24) | |
118 | #define STM32H7_SPI_CFG2_CPOL BIT(25) | |
119 | #define STM32H7_SPI_CFG2_SSM BIT(26) | |
120 | #define STM32H7_SPI_CFG2_AFCNTR BIT(31) | |
121 | ||
122 | /* STM32H7_SPI_IER bit fields */ | |
123 | #define STM32H7_SPI_IER_RXPIE BIT(0) | |
124 | #define STM32H7_SPI_IER_TXPIE BIT(1) | |
125 | #define STM32H7_SPI_IER_DXPIE BIT(2) | |
126 | #define STM32H7_SPI_IER_EOTIE BIT(3) | |
127 | #define STM32H7_SPI_IER_TXTFIE BIT(4) | |
128 | #define STM32H7_SPI_IER_OVRIE BIT(6) | |
129 | #define STM32H7_SPI_IER_MODFIE BIT(9) | |
130 | #define STM32H7_SPI_IER_ALL GENMASK(10, 0) | |
131 | ||
132 | /* STM32H7_SPI_SR bit fields */ | |
133 | #define STM32H7_SPI_SR_RXP BIT(0) | |
134 | #define STM32H7_SPI_SR_TXP BIT(1) | |
135 | #define STM32H7_SPI_SR_EOT BIT(3) | |
136 | #define STM32H7_SPI_SR_OVR BIT(6) | |
137 | #define STM32H7_SPI_SR_MODF BIT(9) | |
138 | #define STM32H7_SPI_SR_SUSP BIT(11) | |
86026630 CG |
139 | #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) |
140 | #define STM32H7_SPI_SR_RXWNE BIT(15) | |
141 | ||
142 | /* STM32H7_SPI_IFCR bit fields */ | |
143 | #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) | |
144 | ||
145 | /* STM32H7_SPI_I2SCFGR bit fields */ | |
146 | #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) | |
147 | ||
148 | /* STM32H7 SPI Master Baud Rate min/max divisor */ | |
149 | #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) | |
150 | #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) | |
dcbe0d84 | 151 | |
9d5fce16 CG |
152 | /* STM32H7 SPI Communication mode */ |
153 | #define STM32H7_SPI_FULL_DUPLEX 0 | |
154 | #define STM32H7_SPI_SIMPLEX_TX 1 | |
155 | #define STM32H7_SPI_SIMPLEX_RX 2 | |
156 | #define STM32H7_SPI_HALF_DUPLEX 3 | |
157 | ||
158 | /* SPI Communication type */ | |
dcbe0d84 AD |
159 | #define SPI_FULL_DUPLEX 0 |
160 | #define SPI_SIMPLEX_TX 1 | |
161 | #define SPI_SIMPLEX_RX 2 | |
9d5fce16 CG |
162 | #define SPI_3WIRE_TX 3 |
163 | #define SPI_3WIRE_RX 4 | |
dcbe0d84 | 164 | |
00505edf CG |
165 | /* |
166 | * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers | |
167 | * without fifo buffers. | |
168 | */ | |
169 | #define SPI_DMA_MIN_BYTES 16 | |
170 | ||
55166853 | 171 | /** |
1c52be8b | 172 | * struct stm32_spi_reg - stm32 SPI register & bitfield desc |
55166853 CG |
173 | * @reg: register offset |
174 | * @mask: bitfield mask | |
175 | * @shift: left shift | |
176 | */ | |
177 | struct stm32_spi_reg { | |
178 | int reg; | |
179 | int mask; | |
180 | int shift; | |
181 | }; | |
182 | ||
183 | /** | |
1c52be8b AV |
184 | * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data |
185 | * @en: enable register and SPI enable bit | |
186 | * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit | |
187 | * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit | |
188 | * @cpol: clock polarity register and polarity bit | |
189 | * @cpha: clock phase register and phase bit | |
190 | * @lsb_first: LSB transmitted first register and bit | |
191 | * @br: baud rate register and bitfields | |
192 | * @rx: SPI RX data register | |
193 | * @tx: SPI TX data register | |
55166853 CG |
194 | */ |
195 | struct stm32_spi_regspec { | |
196 | const struct stm32_spi_reg en; | |
197 | const struct stm32_spi_reg dma_rx_en; | |
198 | const struct stm32_spi_reg dma_tx_en; | |
199 | const struct stm32_spi_reg cpol; | |
200 | const struct stm32_spi_reg cpha; | |
201 | const struct stm32_spi_reg lsb_first; | |
202 | const struct stm32_spi_reg br; | |
203 | const struct stm32_spi_reg rx; | |
204 | const struct stm32_spi_reg tx; | |
205 | }; | |
206 | ||
207 | struct stm32_spi; | |
208 | ||
209 | /** | |
1c52be8b | 210 | * struct stm32_spi_cfg - stm32 compatible configuration data |
55166853 CG |
211 | * @regs: registers descriptions |
212 | * @get_fifo_size: routine to get fifo size | |
213 | * @get_bpw_mask: routine to get bits per word mask | |
214 | * @disable: routine to disable controller | |
215 | * @config: routine to configure controller as SPI Master | |
216 | * @set_bpw: routine to configure registers to for bits per word | |
217 | * @set_mode: routine to configure registers to desired mode | |
218 | * @set_data_idleness: optional routine to configure registers to desired idle | |
219 | * time between frames (if driver has this functionality) | |
1c52be8b | 220 | * @set_number_of_data: optional routine to configure registers to desired |
55166853 CG |
221 | * number of data (if driver has this functionality) |
222 | * @can_dma: routine to determine if the transfer is eligible for DMA use | |
223 | * @transfer_one_dma_start: routine to start transfer a single spi_transfer | |
224 | * using DMA | |
1c52be8b AV |
225 | * @dma_rx_cb: routine to call after DMA RX channel operation is complete |
226 | * @dma_tx_cb: routine to call after DMA TX channel operation is complete | |
55166853 CG |
227 | * @transfer_one_irq: routine to configure interrupts for driver |
228 | * @irq_handler_event: Interrupt handler for SPI controller events | |
229 | * @irq_handler_thread: thread of interrupt handler for SPI controller | |
230 | * @baud_rate_div_min: minimum baud rate divisor | |
231 | * @baud_rate_div_max: maximum baud rate divisor | |
232 | * @has_fifo: boolean to know if fifo is used for driver | |
233 | * @has_startbit: boolean to know if start bit is used to start transfer | |
234 | */ | |
235 | struct stm32_spi_cfg { | |
236 | const struct stm32_spi_regspec *regs; | |
237 | int (*get_fifo_size)(struct stm32_spi *spi); | |
238 | int (*get_bpw_mask)(struct stm32_spi *spi); | |
239 | void (*disable)(struct stm32_spi *spi); | |
240 | int (*config)(struct stm32_spi *spi); | |
241 | void (*set_bpw)(struct stm32_spi *spi); | |
242 | int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type); | |
243 | void (*set_data_idleness)(struct stm32_spi *spi, u32 length); | |
244 | int (*set_number_of_data)(struct stm32_spi *spi, u32 length); | |
245 | void (*transfer_one_dma_start)(struct stm32_spi *spi); | |
246 | void (*dma_rx_cb)(void *data); | |
247 | void (*dma_tx_cb)(void *data); | |
248 | int (*transfer_one_irq)(struct stm32_spi *spi); | |
249 | irqreturn_t (*irq_handler_event)(int irq, void *dev_id); | |
250 | irqreturn_t (*irq_handler_thread)(int irq, void *dev_id); | |
251 | unsigned int baud_rate_div_min; | |
252 | unsigned int baud_rate_div_max; | |
253 | bool has_fifo; | |
254 | }; | |
255 | ||
dcbe0d84 AD |
256 | /** |
257 | * struct stm32_spi - private data of the SPI controller | |
258 | * @dev: driver model representation of the controller | |
259 | * @master: controller master interface | |
55166853 | 260 | * @cfg: compatible configuration data |
dcbe0d84 AD |
261 | * @base: virtual memory area |
262 | * @clk: hw kernel clock feeding the SPI clock generator | |
263 | * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator | |
dcbe0d84 AD |
264 | * @lock: prevent I/O concurrent access |
265 | * @irq: SPI controller interrupt line | |
266 | * @fifo_size: size of the embedded fifo in bytes | |
267 | * @cur_midi: master inter-data idleness in ns | |
268 | * @cur_speed: speed configured in Hz | |
269 | * @cur_bpw: number of bits in a single SPI data frame | |
270 | * @cur_fthlv: fifo threshold level (data frames in a single data packet) | |
271 | * @cur_comm: SPI communication mode | |
272 | * @cur_xferlen: current transfer length in bytes | |
273 | * @cur_usedma: boolean to know if dma is used in current transfer | |
274 | * @tx_buf: data to be written, or NULL | |
275 | * @rx_buf: data to be read, or NULL | |
276 | * @tx_len: number of data to be written in bytes | |
277 | * @rx_len: number of data to be read in bytes | |
278 | * @dma_tx: dma channel for TX transfer | |
279 | * @dma_rx: dma channel for RX transfer | |
280 | * @phys_addr: SPI registers physical base address | |
281 | */ | |
282 | struct stm32_spi { | |
283 | struct device *dev; | |
284 | struct spi_master *master; | |
55166853 | 285 | const struct stm32_spi_cfg *cfg; |
dcbe0d84 AD |
286 | void __iomem *base; |
287 | struct clk *clk; | |
288 | u32 clk_rate; | |
dcbe0d84 AD |
289 | spinlock_t lock; /* prevent I/O concurrent access */ |
290 | int irq; | |
291 | unsigned int fifo_size; | |
292 | ||
293 | unsigned int cur_midi; | |
294 | unsigned int cur_speed; | |
295 | unsigned int cur_bpw; | |
296 | unsigned int cur_fthlv; | |
297 | unsigned int cur_comm; | |
298 | unsigned int cur_xferlen; | |
299 | bool cur_usedma; | |
300 | ||
301 | const void *tx_buf; | |
302 | void *rx_buf; | |
303 | int tx_len; | |
304 | int rx_len; | |
305 | struct dma_chan *dma_tx; | |
306 | struct dma_chan *dma_rx; | |
307 | dma_addr_t phys_addr; | |
308 | }; | |
309 | ||
00505edf CG |
310 | static const struct stm32_spi_regspec stm32f4_spi_regspec = { |
311 | .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE }, | |
312 | ||
313 | .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN }, | |
314 | .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN }, | |
315 | ||
316 | .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL }, | |
317 | .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA }, | |
318 | .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST }, | |
319 | .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT }, | |
320 | ||
321 | .rx = { STM32F4_SPI_DR }, | |
322 | .tx = { STM32F4_SPI_DR }, | |
323 | }; | |
324 | ||
55166853 CG |
325 | static const struct stm32_spi_regspec stm32h7_spi_regspec = { |
326 | /* SPI data transfer is enabled but spi_ker_ck is idle. | |
327 | * CFG1 and CFG2 registers are write protected when SPE is enabled. | |
328 | */ | |
329 | .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE }, | |
330 | ||
331 | .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN }, | |
332 | .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN }, | |
333 | ||
334 | .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL }, | |
335 | .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA }, | |
336 | .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST }, | |
337 | .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR, | |
338 | STM32H7_SPI_CFG1_MBR_SHIFT }, | |
339 | ||
340 | .rx = { STM32H7_SPI_RXDR }, | |
341 | .tx = { STM32H7_SPI_TXDR }, | |
342 | }; | |
343 | ||
dcbe0d84 AD |
344 | static inline void stm32_spi_set_bits(struct stm32_spi *spi, |
345 | u32 offset, u32 bits) | |
346 | { | |
347 | writel_relaxed(readl_relaxed(spi->base + offset) | bits, | |
348 | spi->base + offset); | |
349 | } | |
350 | ||
351 | static inline void stm32_spi_clr_bits(struct stm32_spi *spi, | |
352 | u32 offset, u32 bits) | |
353 | { | |
354 | writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, | |
355 | spi->base + offset); | |
356 | } | |
357 | ||
358 | /** | |
55166853 | 359 | * stm32h7_spi_get_fifo_size - Return fifo size |
dcbe0d84 AD |
360 | * @spi: pointer to the spi controller data structure |
361 | */ | |
55166853 | 362 | static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) |
dcbe0d84 AD |
363 | { |
364 | unsigned long flags; | |
365 | u32 count = 0; | |
366 | ||
367 | spin_lock_irqsave(&spi->lock, flags); | |
368 | ||
86026630 | 369 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 370 | |
86026630 CG |
371 | while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) |
372 | writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); | |
dcbe0d84 | 373 | |
86026630 | 374 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 AD |
375 | |
376 | spin_unlock_irqrestore(&spi->lock, flags); | |
377 | ||
378 | dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); | |
379 | ||
380 | return count; | |
381 | } | |
382 | ||
00505edf CG |
383 | /** |
384 | * stm32f4_spi_get_bpw_mask - Return bits per word mask | |
385 | * @spi: pointer to the spi controller data structure | |
386 | */ | |
387 | static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) | |
388 | { | |
389 | dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); | |
390 | return SPI_BPW_MASK(8) | SPI_BPW_MASK(16); | |
391 | } | |
392 | ||
dcbe0d84 | 393 | /** |
55166853 | 394 | * stm32h7_spi_get_bpw_mask - Return bits per word mask |
dcbe0d84 AD |
395 | * @spi: pointer to the spi controller data structure |
396 | */ | |
55166853 | 397 | static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) |
dcbe0d84 AD |
398 | { |
399 | unsigned long flags; | |
400 | u32 cfg1, max_bpw; | |
401 | ||
402 | spin_lock_irqsave(&spi->lock, flags); | |
403 | ||
404 | /* | |
405 | * The most significant bit at DSIZE bit field is reserved when the | |
406 | * maximum data size of periperal instances is limited to 16-bit | |
407 | */ | |
86026630 | 408 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); |
dcbe0d84 | 409 | |
86026630 | 410 | cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); |
5a380b83 | 411 | max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1; |
dcbe0d84 AD |
412 | |
413 | spin_unlock_irqrestore(&spi->lock, flags); | |
414 | ||
415 | dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); | |
416 | ||
417 | return SPI_BPW_RANGE_MASK(4, max_bpw); | |
418 | } | |
419 | ||
420 | /** | |
9d5fce16 | 421 | * stm32_spi_prepare_mbr - Determine baud rate divisor value |
dcbe0d84 AD |
422 | * @spi: pointer to the spi controller data structure |
423 | * @speed_hz: requested speed | |
9d5fce16 CG |
424 | * @min_div: minimum baud rate divisor |
425 | * @max_div: maximum baud rate divisor | |
dcbe0d84 | 426 | * |
9d5fce16 | 427 | * Return baud rate divisor value in case of success or -EINVAL |
dcbe0d84 | 428 | */ |
9d5fce16 CG |
429 | static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, |
430 | u32 min_div, u32 max_div) | |
dcbe0d84 AD |
431 | { |
432 | u32 div, mbrdiv; | |
433 | ||
9cc61973 AD |
434 | /* Ensure spi->clk_rate is even */ |
435 | div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); | |
dcbe0d84 AD |
436 | |
437 | /* | |
438 | * SPI framework set xfer->speed_hz to master->max_speed_hz if | |
439 | * xfer->speed_hz is greater than master->max_speed_hz, and it returns | |
440 | * an error when xfer->speed_hz is lower than master->min_speed_hz, so | |
441 | * no need to check it there. | |
442 | * However, we need to ensure the following calculations. | |
443 | */ | |
9d5fce16 | 444 | if ((div < min_div) || (div > max_div)) |
dcbe0d84 AD |
445 | return -EINVAL; |
446 | ||
447 | /* Determine the first power of 2 greater than or equal to div */ | |
128ebb89 AD |
448 | if (div & (div - 1)) |
449 | mbrdiv = fls(div); | |
450 | else | |
451 | mbrdiv = fls(div) - 1; | |
dcbe0d84 AD |
452 | |
453 | spi->cur_speed = spi->clk_rate / (1 << mbrdiv); | |
454 | ||
455 | return mbrdiv - 1; | |
456 | } | |
457 | ||
458 | /** | |
55166853 | 459 | * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level |
dcbe0d84 | 460 | * @spi: pointer to the spi controller data structure |
3373e900 | 461 | * @xfer_len: length of the message to be transferred |
dcbe0d84 | 462 | */ |
3373e900 | 463 | static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) |
dcbe0d84 | 464 | { |
970e8eaa | 465 | u32 packet, bpw; |
dcbe0d84 AD |
466 | |
467 | /* data packet should not exceed 1/2 of fifo space */ | |
970e8eaa | 468 | packet = clamp(xfer_len, 1U, spi->fifo_size / 2); |
dcbe0d84 AD |
469 | |
470 | /* align packet size with data registers access */ | |
970e8eaa MV |
471 | bpw = DIV_ROUND_UP(spi->cur_bpw, 8); |
472 | return DIV_ROUND_UP(packet, bpw); | |
dcbe0d84 AD |
473 | } |
474 | ||
00505edf CG |
475 | /** |
476 | * stm32f4_spi_write_tx - Write bytes to Transmit Data Register | |
477 | * @spi: pointer to the spi controller data structure | |
478 | * | |
479 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
480 | * tx_buf end. | |
481 | */ | |
482 | static void stm32f4_spi_write_tx(struct stm32_spi *spi) | |
483 | { | |
484 | if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
485 | STM32F4_SPI_SR_TXE)) { | |
486 | u32 offs = spi->cur_xferlen - spi->tx_len; | |
487 | ||
488 | if (spi->cur_bpw == 16) { | |
489 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
490 | ||
491 | writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); | |
492 | spi->tx_len -= sizeof(u16); | |
493 | } else { | |
494 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
495 | ||
496 | writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); | |
497 | spi->tx_len -= sizeof(u8); | |
498 | } | |
499 | } | |
500 | ||
501 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
502 | } | |
503 | ||
dcbe0d84 | 504 | /** |
55166853 | 505 | * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register |
dcbe0d84 AD |
506 | * @spi: pointer to the spi controller data structure |
507 | * | |
508 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
509 | * tx_buf end. | |
510 | */ | |
55166853 | 511 | static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) |
dcbe0d84 AD |
512 | { |
513 | while ((spi->tx_len > 0) && | |
86026630 CG |
514 | (readl_relaxed(spi->base + STM32H7_SPI_SR) & |
515 | STM32H7_SPI_SR_TXP)) { | |
dcbe0d84 AD |
516 | u32 offs = spi->cur_xferlen - spi->tx_len; |
517 | ||
518 | if (spi->tx_len >= sizeof(u32)) { | |
519 | const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); | |
520 | ||
86026630 | 521 | writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
522 | spi->tx_len -= sizeof(u32); |
523 | } else if (spi->tx_len >= sizeof(u16)) { | |
524 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
525 | ||
86026630 | 526 | writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
527 | spi->tx_len -= sizeof(u16); |
528 | } else { | |
529 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
530 | ||
86026630 | 531 | writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
532 | spi->tx_len -= sizeof(u8); |
533 | } | |
534 | } | |
535 | ||
536 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
537 | } | |
538 | ||
00505edf CG |
539 | /** |
540 | * stm32f4_spi_read_rx - Read bytes from Receive Data Register | |
541 | * @spi: pointer to the spi controller data structure | |
542 | * | |
543 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
544 | * rx_buf end. | |
545 | */ | |
546 | static void stm32f4_spi_read_rx(struct stm32_spi *spi) | |
547 | { | |
548 | if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
549 | STM32F4_SPI_SR_RXNE)) { | |
550 | u32 offs = spi->cur_xferlen - spi->rx_len; | |
551 | ||
552 | if (spi->cur_bpw == 16) { | |
553 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
554 | ||
555 | *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); | |
556 | spi->rx_len -= sizeof(u16); | |
557 | } else { | |
558 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
559 | ||
560 | *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); | |
561 | spi->rx_len -= sizeof(u8); | |
562 | } | |
563 | } | |
564 | ||
565 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); | |
566 | } | |
567 | ||
dcbe0d84 | 568 | /** |
55166853 | 569 | * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register |
dcbe0d84 | 570 | * @spi: pointer to the spi controller data structure |
1c52be8b | 571 | * @flush: boolean indicating that FIFO should be flushed |
dcbe0d84 AD |
572 | * |
573 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
574 | * rx_buf end. | |
575 | */ | |
55166853 | 576 | static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) |
dcbe0d84 | 577 | { |
86026630 | 578 | u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
5a380b83 | 579 | u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr); |
dcbe0d84 AD |
580 | |
581 | while ((spi->rx_len > 0) && | |
86026630 CG |
582 | ((sr & STM32H7_SPI_SR_RXP) || |
583 | (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { | |
dcbe0d84 AD |
584 | u32 offs = spi->cur_xferlen - spi->rx_len; |
585 | ||
586 | if ((spi->rx_len >= sizeof(u32)) || | |
86026630 | 587 | (flush && (sr & STM32H7_SPI_SR_RXWNE))) { |
dcbe0d84 AD |
588 | u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); |
589 | ||
86026630 | 590 | *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
591 | spi->rx_len -= sizeof(u32); |
592 | } else if ((spi->rx_len >= sizeof(u16)) || | |
593 | (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { | |
594 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
595 | ||
86026630 | 596 | *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
597 | spi->rx_len -= sizeof(u16); |
598 | } else { | |
599 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
600 | ||
86026630 | 601 | *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
602 | spi->rx_len -= sizeof(u8); |
603 | } | |
604 | ||
86026630 | 605 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
5a380b83 | 606 | rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr); |
dcbe0d84 AD |
607 | } |
608 | ||
609 | dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, | |
610 | flush ? "(flush)" : "", spi->rx_len); | |
611 | } | |
612 | ||
613 | /** | |
614 | * stm32_spi_enable - Enable SPI controller | |
615 | * @spi: pointer to the spi controller data structure | |
dcbe0d84 AD |
616 | */ |
617 | static void stm32_spi_enable(struct stm32_spi *spi) | |
618 | { | |
619 | dev_dbg(spi->dev, "enable controller\n"); | |
620 | ||
55166853 CG |
621 | stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, |
622 | spi->cfg->regs->en.mask); | |
dcbe0d84 AD |
623 | } |
624 | ||
00505edf CG |
625 | /** |
626 | * stm32f4_spi_disable - Disable SPI controller | |
627 | * @spi: pointer to the spi controller data structure | |
628 | */ | |
629 | static void stm32f4_spi_disable(struct stm32_spi *spi) | |
630 | { | |
631 | unsigned long flags; | |
632 | u32 sr; | |
633 | ||
634 | dev_dbg(spi->dev, "disable controller\n"); | |
635 | ||
636 | spin_lock_irqsave(&spi->lock, flags); | |
637 | ||
638 | if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & | |
639 | STM32F4_SPI_CR1_SPE)) { | |
640 | spin_unlock_irqrestore(&spi->lock, flags); | |
641 | return; | |
642 | } | |
643 | ||
644 | /* Disable interrupts */ | |
645 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | | |
646 | STM32F4_SPI_CR2_RXNEIE | | |
647 | STM32F4_SPI_CR2_ERRIE); | |
648 | ||
649 | /* Wait until BSY = 0 */ | |
650 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, | |
651 | sr, !(sr & STM32F4_SPI_SR_BSY), | |
652 | 10, 100000) < 0) { | |
653 | dev_warn(spi->dev, "disabling condition timeout\n"); | |
654 | } | |
655 | ||
656 | if (spi->cur_usedma && spi->dma_tx) | |
657 | dmaengine_terminate_all(spi->dma_tx); | |
658 | if (spi->cur_usedma && spi->dma_rx) | |
659 | dmaengine_terminate_all(spi->dma_rx); | |
660 | ||
661 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); | |
662 | ||
663 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | | |
664 | STM32F4_SPI_CR2_RXDMAEN); | |
665 | ||
666 | /* Sequence to clear OVR flag */ | |
667 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
668 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
669 | ||
670 | spin_unlock_irqrestore(&spi->lock, flags); | |
671 | } | |
672 | ||
dcbe0d84 | 673 | /** |
55166853 | 674 | * stm32h7_spi_disable - Disable SPI controller |
dcbe0d84 AD |
675 | * @spi: pointer to the spi controller data structure |
676 | * | |
677 | * RX-Fifo is flushed when SPI controller is disabled. To prevent any data | |
55166853 | 678 | * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in |
dcbe0d84 | 679 | * RX-Fifo. |
55166853 CG |
680 | * Normally, if TSIZE has been configured, we should relax the hardware at the |
681 | * reception of the EOT interrupt. But in case of error, EOT will not be | |
682 | * raised. So the subsystem unprepare_message call allows us to properly | |
683 | * complete the transfer from an hardware point of view. | |
dcbe0d84 | 684 | */ |
55166853 | 685 | static void stm32h7_spi_disable(struct stm32_spi *spi) |
dcbe0d84 AD |
686 | { |
687 | unsigned long flags; | |
688 | u32 cr1, sr; | |
689 | ||
690 | dev_dbg(spi->dev, "disable controller\n"); | |
691 | ||
692 | spin_lock_irqsave(&spi->lock, flags); | |
693 | ||
86026630 | 694 | cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); |
dcbe0d84 | 695 | |
86026630 | 696 | if (!(cr1 & STM32H7_SPI_CR1_SPE)) { |
dcbe0d84 AD |
697 | spin_unlock_irqrestore(&spi->lock, flags); |
698 | return; | |
699 | } | |
700 | ||
701 | /* Wait on EOT or suspend the flow */ | |
86026630 CG |
702 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, |
703 | sr, !(sr & STM32H7_SPI_SR_EOT), | |
dcbe0d84 | 704 | 10, 100000) < 0) { |
86026630 CG |
705 | if (cr1 & STM32H7_SPI_CR1_CSTART) { |
706 | writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, | |
707 | spi->base + STM32H7_SPI_CR1); | |
dcbe0d84 | 708 | if (readl_relaxed_poll_timeout_atomic( |
86026630 CG |
709 | spi->base + STM32H7_SPI_SR, |
710 | sr, !(sr & STM32H7_SPI_SR_SUSP), | |
dcbe0d84 AD |
711 | 10, 100000) < 0) |
712 | dev_warn(spi->dev, | |
713 | "Suspend request timeout\n"); | |
714 | } | |
715 | } | |
716 | ||
717 | if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) | |
55166853 | 718 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 | 719 | |
2cbee7f8 | 720 | if (spi->cur_usedma && spi->dma_tx) |
dcbe0d84 | 721 | dmaengine_terminate_all(spi->dma_tx); |
2cbee7f8 | 722 | if (spi->cur_usedma && spi->dma_rx) |
dcbe0d84 AD |
723 | dmaengine_terminate_all(spi->dma_rx); |
724 | ||
86026630 | 725 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 726 | |
86026630 CG |
727 | stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | |
728 | STM32H7_SPI_CFG1_RXDMAEN); | |
dcbe0d84 AD |
729 | |
730 | /* Disable interrupts and clear status flags */ | |
86026630 CG |
731 | writel_relaxed(0, spi->base + STM32H7_SPI_IER); |
732 | writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); | |
dcbe0d84 AD |
733 | |
734 | spin_unlock_irqrestore(&spi->lock, flags); | |
735 | } | |
736 | ||
737 | /** | |
738 | * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use | |
1c52be8b AV |
739 | * @master: controller master interface |
740 | * @spi_dev: pointer to the spi device | |
741 | * @transfer: pointer to spi transfer | |
dcbe0d84 | 742 | * |
00505edf CG |
743 | * If driver has fifo and the current transfer size is greater than fifo size, |
744 | * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes. | |
dcbe0d84 AD |
745 | */ |
746 | static bool stm32_spi_can_dma(struct spi_master *master, | |
747 | struct spi_device *spi_dev, | |
748 | struct spi_transfer *transfer) | |
749 | { | |
00505edf | 750 | unsigned int dma_size; |
dcbe0d84 AD |
751 | struct stm32_spi *spi = spi_master_get_devdata(master); |
752 | ||
00505edf CG |
753 | if (spi->cfg->has_fifo) |
754 | dma_size = spi->fifo_size; | |
755 | else | |
756 | dma_size = SPI_DMA_MIN_BYTES; | |
757 | ||
dcbe0d84 | 758 | dev_dbg(spi->dev, "%s: %s\n", __func__, |
00505edf | 759 | (transfer->len > dma_size) ? "true" : "false"); |
dcbe0d84 | 760 | |
00505edf CG |
761 | return (transfer->len > dma_size); |
762 | } | |
763 | ||
764 | /** | |
765 | * stm32f4_spi_irq_event - Interrupt handler for SPI controller events | |
766 | * @irq: interrupt line | |
767 | * @dev_id: SPI controller master interface | |
768 | */ | |
769 | static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) | |
770 | { | |
771 | struct spi_master *master = dev_id; | |
772 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
773 | u32 sr, mask = 0; | |
00505edf CG |
774 | bool end = false; |
775 | ||
e2368933 | 776 | spin_lock(&spi->lock); |
00505edf CG |
777 | |
778 | sr = readl_relaxed(spi->base + STM32F4_SPI_SR); | |
779 | /* | |
780 | * BSY flag is not handled in interrupt but it is normal behavior when | |
781 | * this flag is set. | |
782 | */ | |
783 | sr &= ~STM32F4_SPI_SR_BSY; | |
784 | ||
785 | if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || | |
786 | spi->cur_comm == SPI_3WIRE_TX)) { | |
787 | /* OVR flag shouldn't be handled for TX only mode */ | |
788 | sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE; | |
789 | mask |= STM32F4_SPI_SR_TXE; | |
790 | } | |
791 | ||
61367d0b | 792 | if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || |
793 | spi->cur_comm == SPI_SIMPLEX_RX || | |
794 | spi->cur_comm == SPI_3WIRE_RX)) { | |
00505edf CG |
795 | /* TXE flag is set and is handled when RXNE flag occurs */ |
796 | sr &= ~STM32F4_SPI_SR_TXE; | |
797 | mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; | |
798 | } | |
799 | ||
800 | if (!(sr & mask)) { | |
801 | dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); | |
e2368933 | 802 | spin_unlock(&spi->lock); |
00505edf CG |
803 | return IRQ_NONE; |
804 | } | |
805 | ||
806 | if (sr & STM32F4_SPI_SR_OVR) { | |
807 | dev_warn(spi->dev, "Overrun: received value discarded\n"); | |
808 | ||
809 | /* Sequence to clear OVR flag */ | |
810 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
811 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
812 | ||
813 | /* | |
814 | * If overrun is detected, it means that something went wrong, | |
815 | * so stop the current transfer. Transfer can wait for next | |
816 | * RXNE but DR is already read and end never happens. | |
817 | */ | |
818 | end = true; | |
819 | goto end_irq; | |
820 | } | |
821 | ||
822 | if (sr & STM32F4_SPI_SR_TXE) { | |
823 | if (spi->tx_buf) | |
824 | stm32f4_spi_write_tx(spi); | |
825 | if (spi->tx_len == 0) | |
826 | end = true; | |
827 | } | |
828 | ||
829 | if (sr & STM32F4_SPI_SR_RXNE) { | |
830 | stm32f4_spi_read_rx(spi); | |
831 | if (spi->rx_len == 0) | |
832 | end = true; | |
61367d0b | 833 | else if (spi->tx_buf)/* Load data for discontinuous mode */ |
00505edf CG |
834 | stm32f4_spi_write_tx(spi); |
835 | } | |
836 | ||
837 | end_irq: | |
838 | if (end) { | |
839 | /* Immediately disable interrupts to do not generate new one */ | |
840 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, | |
841 | STM32F4_SPI_CR2_TXEIE | | |
842 | STM32F4_SPI_CR2_RXNEIE | | |
843 | STM32F4_SPI_CR2_ERRIE); | |
e2368933 | 844 | spin_unlock(&spi->lock); |
00505edf CG |
845 | return IRQ_WAKE_THREAD; |
846 | } | |
847 | ||
e2368933 | 848 | spin_unlock(&spi->lock); |
00505edf CG |
849 | return IRQ_HANDLED; |
850 | } | |
851 | ||
852 | /** | |
853 | * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller | |
854 | * @irq: interrupt line | |
855 | * @dev_id: SPI controller master interface | |
856 | */ | |
857 | static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id) | |
858 | { | |
859 | struct spi_master *master = dev_id; | |
860 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
861 | ||
862 | spi_finalize_current_transfer(master); | |
863 | stm32f4_spi_disable(spi); | |
864 | ||
865 | return IRQ_HANDLED; | |
dcbe0d84 AD |
866 | } |
867 | ||
868 | /** | |
55166853 | 869 | * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller |
dcbe0d84 AD |
870 | * @irq: interrupt line |
871 | * @dev_id: SPI controller master interface | |
872 | */ | |
55166853 | 873 | static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) |
dcbe0d84 AD |
874 | { |
875 | struct spi_master *master = dev_id; | |
876 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
877 | u32 sr, ier, mask; | |
878 | unsigned long flags; | |
879 | bool end = false; | |
880 | ||
881 | spin_lock_irqsave(&spi->lock, flags); | |
882 | ||
86026630 CG |
883 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
884 | ier = readl_relaxed(spi->base + STM32H7_SPI_IER); | |
dcbe0d84 AD |
885 | |
886 | mask = ier; | |
887 | /* EOTIE is triggered on EOT, SUSP and TXC events. */ | |
86026630 | 888 | mask |= STM32H7_SPI_SR_SUSP; |
dcbe0d84 AD |
889 | /* |
890 | * When TXTF is set, DXPIE and TXPIE are cleared. So in case of | |
891 | * Full-Duplex, need to poll RXP event to know if there are remaining | |
892 | * data, before disabling SPI. | |
893 | */ | |
128ebb89 | 894 | if (spi->rx_buf && !spi->cur_usedma) |
86026630 | 895 | mask |= STM32H7_SPI_SR_RXP; |
dcbe0d84 AD |
896 | |
897 | if (!(sr & mask)) { | |
c64e7efe AV |
898 | dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", |
899 | sr, ier); | |
dcbe0d84 AD |
900 | spin_unlock_irqrestore(&spi->lock, flags); |
901 | return IRQ_NONE; | |
902 | } | |
903 | ||
86026630 | 904 | if (sr & STM32H7_SPI_SR_SUSP) { |
ea8be08c MV |
905 | static DEFINE_RATELIMIT_STATE(rs, |
906 | DEFAULT_RATELIMIT_INTERVAL * 10, | |
907 | 1); | |
908 | if (__ratelimit(&rs)) | |
909 | dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); | |
dcbe0d84 | 910 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 911 | stm32h7_spi_read_rxfifo(spi, false); |
c67ad368 AD |
912 | /* |
913 | * If communication is suspended while using DMA, it means | |
914 | * that something went wrong, so stop the current transfer | |
915 | */ | |
916 | if (spi->cur_usedma) | |
917 | end = true; | |
dcbe0d84 AD |
918 | } |
919 | ||
86026630 | 920 | if (sr & STM32H7_SPI_SR_MODF) { |
dcbe0d84 AD |
921 | dev_warn(spi->dev, "Mode fault: transfer aborted\n"); |
922 | end = true; | |
923 | } | |
924 | ||
86026630 | 925 | if (sr & STM32H7_SPI_SR_OVR) { |
c64e7efe AV |
926 | dev_err(spi->dev, "Overrun: RX data lost\n"); |
927 | end = true; | |
dcbe0d84 AD |
928 | } |
929 | ||
86026630 | 930 | if (sr & STM32H7_SPI_SR_EOT) { |
dcbe0d84 | 931 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 932 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 AD |
933 | end = true; |
934 | } | |
935 | ||
86026630 | 936 | if (sr & STM32H7_SPI_SR_TXP) |
dcbe0d84 | 937 | if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) |
55166853 | 938 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 939 | |
86026630 | 940 | if (sr & STM32H7_SPI_SR_RXP) |
dcbe0d84 | 941 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 942 | stm32h7_spi_read_rxfifo(spi, false); |
dcbe0d84 | 943 | |
ae1ba50f | 944 | writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); |
dcbe0d84 AD |
945 | |
946 | spin_unlock_irqrestore(&spi->lock, flags); | |
947 | ||
948 | if (end) { | |
55166853 | 949 | stm32h7_spi_disable(spi); |
135dd873 | 950 | spi_finalize_current_transfer(master); |
dcbe0d84 AD |
951 | } |
952 | ||
953 | return IRQ_HANDLED; | |
954 | } | |
955 | ||
dcbe0d84 AD |
956 | /** |
957 | * stm32_spi_prepare_msg - set up the controller to transfer a single message | |
1c52be8b AV |
958 | * @master: controller master interface |
959 | * @msg: pointer to spi message | |
dcbe0d84 AD |
960 | */ |
961 | static int stm32_spi_prepare_msg(struct spi_master *master, | |
962 | struct spi_message *msg) | |
963 | { | |
964 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
965 | struct spi_device *spi_dev = msg->spi; | |
966 | struct device_node *np = spi_dev->dev.of_node; | |
967 | unsigned long flags; | |
55166853 | 968 | u32 clrb = 0, setb = 0; |
dcbe0d84 AD |
969 | |
970 | /* SPI slave device may need time between data frames */ | |
971 | spi->cur_midi = 0; | |
042c1c60 | 972 | if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) |
dcbe0d84 AD |
973 | dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); |
974 | ||
975 | if (spi_dev->mode & SPI_CPOL) | |
55166853 | 976 | setb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 | 977 | else |
55166853 | 978 | clrb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 AD |
979 | |
980 | if (spi_dev->mode & SPI_CPHA) | |
55166853 | 981 | setb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 | 982 | else |
55166853 | 983 | clrb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 AD |
984 | |
985 | if (spi_dev->mode & SPI_LSB_FIRST) | |
55166853 | 986 | setb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 | 987 | else |
55166853 | 988 | clrb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 AD |
989 | |
990 | dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", | |
8b835da6 AA |
991 | !!(spi_dev->mode & SPI_CPOL), |
992 | !!(spi_dev->mode & SPI_CPHA), | |
993 | !!(spi_dev->mode & SPI_LSB_FIRST), | |
994 | !!(spi_dev->mode & SPI_CS_HIGH)); | |
dcbe0d84 | 995 | |
084de523 AV |
996 | /* On STM32H7, messages should not exceed a maximum size setted |
997 | * afterward via the set_number_of_data function. In order to | |
998 | * ensure that, split large messages into several messages | |
999 | */ | |
1000 | if (spi->cfg->set_number_of_data) { | |
1001 | int ret; | |
1002 | ||
1003 | ret = spi_split_transfers_maxsize(master, msg, | |
1004 | STM32H7_SPI_TSIZE_MAX, | |
1005 | GFP_KERNEL | GFP_DMA); | |
1006 | if (ret) | |
1007 | return ret; | |
1008 | } | |
1009 | ||
dcbe0d84 AD |
1010 | spin_lock_irqsave(&spi->lock, flags); |
1011 | ||
55166853 CG |
1012 | /* CPOL, CPHA and LSB FIRST bits have common register */ |
1013 | if (clrb || setb) | |
dcbe0d84 | 1014 | writel_relaxed( |
55166853 CG |
1015 | (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & |
1016 | ~clrb) | setb, | |
1017 | spi->base + spi->cfg->regs->cpol.reg); | |
dcbe0d84 AD |
1018 | |
1019 | spin_unlock_irqrestore(&spi->lock, flags); | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
00505edf CG |
1024 | /** |
1025 | * stm32f4_spi_dma_tx_cb - dma callback | |
1c52be8b | 1026 | * @data: pointer to the spi controller data structure |
00505edf CG |
1027 | * |
1028 | * DMA callback is called when the transfer is complete for DMA TX channel. | |
1029 | */ | |
1030 | static void stm32f4_spi_dma_tx_cb(void *data) | |
1031 | { | |
1032 | struct stm32_spi *spi = data; | |
1033 | ||
1034 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1035 | spi_finalize_current_transfer(spi->master); | |
1036 | stm32f4_spi_disable(spi); | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * stm32f4_spi_dma_rx_cb - dma callback | |
1c52be8b | 1042 | * @data: pointer to the spi controller data structure |
00505edf CG |
1043 | * |
1044 | * DMA callback is called when the transfer is complete for DMA RX channel. | |
1045 | */ | |
1046 | static void stm32f4_spi_dma_rx_cb(void *data) | |
1047 | { | |
1048 | struct stm32_spi *spi = data; | |
1049 | ||
1050 | spi_finalize_current_transfer(spi->master); | |
1051 | stm32f4_spi_disable(spi); | |
1052 | } | |
1053 | ||
dcbe0d84 | 1054 | /** |
55166853 | 1055 | * stm32h7_spi_dma_cb - dma callback |
1c52be8b | 1056 | * @data: pointer to the spi controller data structure |
dcbe0d84 AD |
1057 | * |
1058 | * DMA callback is called when the transfer is complete or when an error | |
1059 | * occurs. If the transfer is complete, EOT flag is raised. | |
1060 | */ | |
55166853 | 1061 | static void stm32h7_spi_dma_cb(void *data) |
dcbe0d84 AD |
1062 | { |
1063 | struct stm32_spi *spi = data; | |
1064 | unsigned long flags; | |
1065 | u32 sr; | |
1066 | ||
1067 | spin_lock_irqsave(&spi->lock, flags); | |
1068 | ||
86026630 | 1069 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
dcbe0d84 AD |
1070 | |
1071 | spin_unlock_irqrestore(&spi->lock, flags); | |
1072 | ||
86026630 | 1073 | if (!(sr & STM32H7_SPI_SR_EOT)) |
c67ad368 | 1074 | dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); |
dcbe0d84 | 1075 | |
c67ad368 | 1076 | /* Now wait for EOT, or SUSP or OVR in case of error */ |
dcbe0d84 AD |
1077 | } |
1078 | ||
1079 | /** | |
1080 | * stm32_spi_dma_config - configure dma slave channel depending on current | |
1081 | * transfer bits_per_word. | |
1c52be8b AV |
1082 | * @spi: pointer to the spi controller data structure |
1083 | * @dma_conf: pointer to the dma_slave_config structure | |
1084 | * @dir: direction of the dma transfer | |
dcbe0d84 AD |
1085 | */ |
1086 | static void stm32_spi_dma_config(struct stm32_spi *spi, | |
1087 | struct dma_slave_config *dma_conf, | |
1088 | enum dma_transfer_direction dir) | |
1089 | { | |
1090 | enum dma_slave_buswidth buswidth; | |
1091 | u32 maxburst; | |
1092 | ||
128ebb89 AD |
1093 | if (spi->cur_bpw <= 8) |
1094 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1095 | else if (spi->cur_bpw <= 16) | |
1096 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1097 | else | |
1098 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
dcbe0d84 | 1099 | |
00505edf CG |
1100 | if (spi->cfg->has_fifo) { |
1101 | /* Valid for DMA Half or Full Fifo threshold */ | |
1102 | if (spi->cur_fthlv == 2) | |
1103 | maxburst = 1; | |
1104 | else | |
1105 | maxburst = spi->cur_fthlv; | |
1106 | } else { | |
128ebb89 | 1107 | maxburst = 1; |
00505edf | 1108 | } |
dcbe0d84 AD |
1109 | |
1110 | memset(dma_conf, 0, sizeof(struct dma_slave_config)); | |
1111 | dma_conf->direction = dir; | |
1112 | if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ | |
55166853 | 1113 | dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; |
dcbe0d84 AD |
1114 | dma_conf->src_addr_width = buswidth; |
1115 | dma_conf->src_maxburst = maxburst; | |
1116 | ||
1117 | dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", | |
1118 | buswidth, maxburst); | |
1119 | } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ | |
55166853 | 1120 | dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; |
dcbe0d84 AD |
1121 | dma_conf->dst_addr_width = buswidth; |
1122 | dma_conf->dst_maxburst = maxburst; | |
1123 | ||
1124 | dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", | |
1125 | buswidth, maxburst); | |
1126 | } | |
1127 | } | |
1128 | ||
00505edf CG |
1129 | /** |
1130 | * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using | |
1131 | * interrupts | |
1c52be8b | 1132 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1133 | * |
1134 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1135 | * in progress. | |
1136 | */ | |
1137 | static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) | |
1138 | { | |
1139 | unsigned long flags; | |
1140 | u32 cr2 = 0; | |
1141 | ||
1142 | /* Enable the interrupts relative to the current communication mode */ | |
1143 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1144 | cr2 |= STM32F4_SPI_CR2_TXEIE; | |
61367d0b | 1145 | } else if (spi->cur_comm == SPI_FULL_DUPLEX || |
1146 | spi->cur_comm == SPI_SIMPLEX_RX || | |
1147 | spi->cur_comm == SPI_3WIRE_RX) { | |
00505edf CG |
1148 | /* In transmit-only mode, the OVR flag is set in the SR register |
1149 | * since the received data are never read. Therefore set OVR | |
1150 | * interrupt only when rx buffer is available. | |
1151 | */ | |
1152 | cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE; | |
1153 | } else { | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | ||
1157 | spin_lock_irqsave(&spi->lock, flags); | |
1158 | ||
1159 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); | |
1160 | ||
1161 | stm32_spi_enable(spi); | |
1162 | ||
1163 | /* starting data transfer when buffer is loaded */ | |
1164 | if (spi->tx_buf) | |
1165 | stm32f4_spi_write_tx(spi); | |
1166 | ||
1167 | spin_unlock_irqrestore(&spi->lock, flags); | |
1168 | ||
1169 | return 1; | |
1170 | } | |
1171 | ||
dcbe0d84 | 1172 | /** |
55166853 CG |
1173 | * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using |
1174 | * interrupts | |
1c52be8b | 1175 | * @spi: pointer to the spi controller data structure |
dcbe0d84 AD |
1176 | * |
1177 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1178 | * in progress. | |
1179 | */ | |
55166853 | 1180 | static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) |
dcbe0d84 AD |
1181 | { |
1182 | unsigned long flags; | |
1183 | u32 ier = 0; | |
1184 | ||
1185 | /* Enable the interrupts relative to the current communication mode */ | |
1186 | if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ | |
86026630 | 1187 | ier |= STM32H7_SPI_IER_DXPIE; |
dcbe0d84 | 1188 | else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ |
86026630 | 1189 | ier |= STM32H7_SPI_IER_TXPIE; |
dcbe0d84 | 1190 | else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ |
86026630 | 1191 | ier |= STM32H7_SPI_IER_RXPIE; |
dcbe0d84 AD |
1192 | |
1193 | /* Enable the interrupts relative to the end of transfer */ | |
86026630 CG |
1194 | ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | |
1195 | STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; | |
dcbe0d84 AD |
1196 | |
1197 | spin_lock_irqsave(&spi->lock, flags); | |
1198 | ||
1199 | stm32_spi_enable(spi); | |
1200 | ||
1201 | /* Be sure to have data in fifo before starting data transfer */ | |
1202 | if (spi->tx_buf) | |
55166853 | 1203 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 1204 | |
86026630 | 1205 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); |
dcbe0d84 | 1206 | |
86026630 | 1207 | writel_relaxed(ier, spi->base + STM32H7_SPI_IER); |
dcbe0d84 AD |
1208 | |
1209 | spin_unlock_irqrestore(&spi->lock, flags); | |
1210 | ||
1211 | return 1; | |
1212 | } | |
1213 | ||
00505edf CG |
1214 | /** |
1215 | * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start | |
1216 | * transfer using DMA | |
1c52be8b | 1217 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1218 | */ |
1219 | static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) | |
1220 | { | |
1221 | /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ | |
1222 | if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || | |
1223 | spi->cur_comm == SPI_FULL_DUPLEX) { | |
1224 | /* | |
1225 | * In transmit-only mode, the OVR flag is set in the SR register | |
1226 | * since the received data are never read. Therefore set OVR | |
1227 | * interrupt only when rx buffer is available. | |
1228 | */ | |
1229 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); | |
1230 | } | |
1231 | ||
1232 | stm32_spi_enable(spi); | |
1233 | } | |
1234 | ||
f8bb12f2 | 1235 | /** |
55166853 CG |
1236 | * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start |
1237 | * transfer using DMA | |
1c52be8b | 1238 | * @spi: pointer to the spi controller data structure |
f8bb12f2 | 1239 | */ |
55166853 | 1240 | static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) |
f8bb12f2 CG |
1241 | { |
1242 | /* Enable the interrupts relative to the end of transfer */ | |
1243 | stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | | |
1244 | STM32H7_SPI_IER_TXTFIE | | |
1245 | STM32H7_SPI_IER_OVRIE | | |
1246 | STM32H7_SPI_IER_MODFIE); | |
1247 | ||
1248 | stm32_spi_enable(spi); | |
1249 | ||
1250 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); | |
1251 | } | |
1252 | ||
dcbe0d84 AD |
1253 | /** |
1254 | * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA | |
1c52be8b AV |
1255 | * @spi: pointer to the spi controller data structure |
1256 | * @xfer: pointer to the spi_transfer structure | |
dcbe0d84 AD |
1257 | * |
1258 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1259 | * in progress. | |
1260 | */ | |
1261 | static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, | |
1262 | struct spi_transfer *xfer) | |
1263 | { | |
1264 | struct dma_slave_config tx_dma_conf, rx_dma_conf; | |
1265 | struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; | |
1266 | unsigned long flags; | |
dcbe0d84 AD |
1267 | |
1268 | spin_lock_irqsave(&spi->lock, flags); | |
1269 | ||
1270 | rx_dma_desc = NULL; | |
2cbee7f8 | 1271 | if (spi->rx_buf && spi->dma_rx) { |
dcbe0d84 AD |
1272 | stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); |
1273 | dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); | |
1274 | ||
1275 | /* Enable Rx DMA request */ | |
55166853 CG |
1276 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1277 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1278 | |
1279 | rx_dma_desc = dmaengine_prep_slave_sg( | |
1280 | spi->dma_rx, xfer->rx_sg.sgl, | |
1281 | xfer->rx_sg.nents, | |
1282 | rx_dma_conf.direction, | |
1283 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1284 | } |
1285 | ||
1286 | tx_dma_desc = NULL; | |
2cbee7f8 | 1287 | if (spi->tx_buf && spi->dma_tx) { |
dcbe0d84 AD |
1288 | stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); |
1289 | dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); | |
1290 | ||
1291 | tx_dma_desc = dmaengine_prep_slave_sg( | |
1292 | spi->dma_tx, xfer->tx_sg.sgl, | |
1293 | xfer->tx_sg.nents, | |
1294 | tx_dma_conf.direction, | |
1295 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1296 | } |
1297 | ||
2cbee7f8 CG |
1298 | if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || |
1299 | (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) | |
1300 | goto dma_desc_error; | |
1301 | ||
1302 | if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) | |
dcbe0d84 AD |
1303 | goto dma_desc_error; |
1304 | ||
1305 | if (rx_dma_desc) { | |
55166853 | 1306 | rx_dma_desc->callback = spi->cfg->dma_rx_cb; |
7b821a64 AD |
1307 | rx_dma_desc->callback_param = spi; |
1308 | ||
dcbe0d84 AD |
1309 | if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { |
1310 | dev_err(spi->dev, "Rx DMA submit failed\n"); | |
1311 | goto dma_desc_error; | |
1312 | } | |
1313 | /* Enable Rx DMA channel */ | |
1314 | dma_async_issue_pending(spi->dma_rx); | |
1315 | } | |
1316 | ||
1317 | if (tx_dma_desc) { | |
9d5fce16 CG |
1318 | if (spi->cur_comm == SPI_SIMPLEX_TX || |
1319 | spi->cur_comm == SPI_3WIRE_TX) { | |
55166853 | 1320 | tx_dma_desc->callback = spi->cfg->dma_tx_cb; |
7b821a64 AD |
1321 | tx_dma_desc->callback_param = spi; |
1322 | } | |
1323 | ||
dcbe0d84 AD |
1324 | if (dma_submit_error(dmaengine_submit(tx_dma_desc))) { |
1325 | dev_err(spi->dev, "Tx DMA submit failed\n"); | |
1326 | goto dma_submit_error; | |
1327 | } | |
1328 | /* Enable Tx DMA channel */ | |
1329 | dma_async_issue_pending(spi->dma_tx); | |
1330 | ||
1331 | /* Enable Tx DMA request */ | |
55166853 CG |
1332 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, |
1333 | spi->cfg->regs->dma_tx_en.mask); | |
dcbe0d84 AD |
1334 | } |
1335 | ||
55166853 | 1336 | spi->cfg->transfer_one_dma_start(spi); |
dcbe0d84 AD |
1337 | |
1338 | spin_unlock_irqrestore(&spi->lock, flags); | |
1339 | ||
1340 | return 1; | |
1341 | ||
1342 | dma_submit_error: | |
2cbee7f8 | 1343 | if (spi->dma_rx) |
dcbe0d84 AD |
1344 | dmaengine_terminate_all(spi->dma_rx); |
1345 | ||
1346 | dma_desc_error: | |
55166853 CG |
1347 | stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1348 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1349 | |
1350 | spin_unlock_irqrestore(&spi->lock, flags); | |
1351 | ||
1352 | dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); | |
1353 | ||
2cbee7f8 | 1354 | spi->cur_usedma = false; |
55166853 | 1355 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1356 | } |
1357 | ||
00505edf CG |
1358 | /** |
1359 | * stm32f4_spi_set_bpw - Configure bits per word | |
1360 | * @spi: pointer to the spi controller data structure | |
1361 | */ | |
1362 | static void stm32f4_spi_set_bpw(struct stm32_spi *spi) | |
1363 | { | |
1364 | if (spi->cur_bpw == 16) | |
1365 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1366 | else | |
1367 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1368 | } | |
1369 | ||
dcbe0d84 | 1370 | /** |
55166853 | 1371 | * stm32h7_spi_set_bpw - configure bits per word |
9d5fce16 | 1372 | * @spi: pointer to the spi controller data structure |
dcbe0d84 | 1373 | */ |
55166853 | 1374 | static void stm32h7_spi_set_bpw(struct stm32_spi *spi) |
dcbe0d84 | 1375 | { |
9d5fce16 CG |
1376 | u32 bpw, fthlv; |
1377 | u32 cfg1_clrb = 0, cfg1_setb = 0; | |
dcbe0d84 | 1378 | |
9d5fce16 | 1379 | bpw = spi->cur_bpw - 1; |
dcbe0d84 | 1380 | |
9d5fce16 | 1381 | cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; |
5a380b83 | 1382 | cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw); |
dcbe0d84 | 1383 | |
3373e900 | 1384 | spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); |
9d5fce16 | 1385 | fthlv = spi->cur_fthlv - 1; |
dcbe0d84 | 1386 | |
9d5fce16 | 1387 | cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; |
5a380b83 | 1388 | cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv); |
dcbe0d84 | 1389 | |
9d5fce16 CG |
1390 | writel_relaxed( |
1391 | (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & | |
1392 | ~cfg1_clrb) | cfg1_setb, | |
1393 | spi->base + STM32H7_SPI_CFG1); | |
1394 | } | |
dcbe0d84 | 1395 | |
9d5fce16 CG |
1396 | /** |
1397 | * stm32_spi_set_mbr - Configure baud rate divisor in master mode | |
1398 | * @spi: pointer to the spi controller data structure | |
1399 | * @mbrdiv: baud rate divisor value | |
1400 | */ | |
1401 | static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) | |
1402 | { | |
55166853 | 1403 | u32 clrb = 0, setb = 0; |
dcbe0d84 | 1404 | |
55166853 | 1405 | clrb |= spi->cfg->regs->br.mask; |
5a380b83 | 1406 | setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; |
dcbe0d84 | 1407 | |
55166853 CG |
1408 | writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & |
1409 | ~clrb) | setb, | |
1410 | spi->base + spi->cfg->regs->br.reg); | |
9d5fce16 | 1411 | } |
dcbe0d84 | 1412 | |
9d5fce16 CG |
1413 | /** |
1414 | * stm32_spi_communication_type - return transfer communication type | |
1415 | * @spi_dev: pointer to the spi device | |
1c52be8b | 1416 | * @transfer: pointer to spi transfer |
9d5fce16 CG |
1417 | */ |
1418 | static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev, | |
1419 | struct spi_transfer *transfer) | |
1420 | { | |
1421 | unsigned int type = SPI_FULL_DUPLEX; | |
dcbe0d84 | 1422 | |
dcbe0d84 AD |
1423 | if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ |
1424 | /* | |
1425 | * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL | |
9d5fce16 | 1426 | * is forbidden and unvalidated by SPI subsystem so depending |
dcbe0d84 AD |
1427 | * on the valid buffer, we can determine the direction of the |
1428 | * transfer. | |
1429 | */ | |
dcbe0d84 | 1430 | if (!transfer->tx_buf) |
9d5fce16 CG |
1431 | type = SPI_3WIRE_RX; |
1432 | else | |
1433 | type = SPI_3WIRE_TX; | |
dcbe0d84 AD |
1434 | } else { |
1435 | if (!transfer->tx_buf) | |
9d5fce16 | 1436 | type = SPI_SIMPLEX_RX; |
dcbe0d84 | 1437 | else if (!transfer->rx_buf) |
9d5fce16 | 1438 | type = SPI_SIMPLEX_TX; |
dcbe0d84 | 1439 | } |
dcbe0d84 | 1440 | |
9d5fce16 CG |
1441 | return type; |
1442 | } | |
1443 | ||
00505edf CG |
1444 | /** |
1445 | * stm32f4_spi_set_mode - configure communication mode | |
1446 | * @spi: pointer to the spi controller data structure | |
1447 | * @comm_type: type of communication to configure | |
1448 | */ | |
1449 | static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) | |
1450 | { | |
1451 | if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) { | |
1452 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, | |
1453 | STM32F4_SPI_CR1_BIDIMODE | | |
1454 | STM32F4_SPI_CR1_BIDIOE); | |
61367d0b | 1455 | } else if (comm_type == SPI_FULL_DUPLEX || |
1456 | comm_type == SPI_SIMPLEX_RX) { | |
00505edf CG |
1457 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, |
1458 | STM32F4_SPI_CR1_BIDIMODE | | |
1459 | STM32F4_SPI_CR1_BIDIOE); | |
61367d0b | 1460 | } else if (comm_type == SPI_3WIRE_RX) { |
1461 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, | |
1462 | STM32F4_SPI_CR1_BIDIMODE); | |
1463 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, | |
1464 | STM32F4_SPI_CR1_BIDIOE); | |
00505edf CG |
1465 | } else { |
1466 | return -EINVAL; | |
1467 | } | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | ||
9d5fce16 | 1472 | /** |
55166853 | 1473 | * stm32h7_spi_set_mode - configure communication mode |
9d5fce16 CG |
1474 | * @spi: pointer to the spi controller data structure |
1475 | * @comm_type: type of communication to configure | |
1476 | */ | |
55166853 | 1477 | static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) |
9d5fce16 CG |
1478 | { |
1479 | u32 mode; | |
1480 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1481 | ||
1482 | if (comm_type == SPI_3WIRE_RX) { | |
1483 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1484 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1485 | } else if (comm_type == SPI_3WIRE_TX) { | |
1486 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1487 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1488 | } else if (comm_type == SPI_SIMPLEX_RX) { | |
1489 | mode = STM32H7_SPI_SIMPLEX_RX; | |
1490 | } else if (comm_type == SPI_SIMPLEX_TX) { | |
1491 | mode = STM32H7_SPI_SIMPLEX_TX; | |
1492 | } else { | |
1493 | mode = STM32H7_SPI_FULL_DUPLEX; | |
dcbe0d84 AD |
1494 | } |
1495 | ||
9d5fce16 | 1496 | cfg2_clrb |= STM32H7_SPI_CFG2_COMM; |
5a380b83 | 1497 | cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode); |
9d5fce16 CG |
1498 | |
1499 | writel_relaxed( | |
1500 | (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & | |
1501 | ~cfg2_clrb) | cfg2_setb, | |
1502 | spi->base + STM32H7_SPI_CFG2); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | /** | |
55166853 CG |
1508 | * stm32h7_spi_data_idleness - configure minimum time delay inserted between two |
1509 | * consecutive data frames in master mode | |
9d5fce16 CG |
1510 | * @spi: pointer to the spi controller data structure |
1511 | * @len: transfer len | |
1512 | */ | |
55166853 | 1513 | static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) |
9d5fce16 CG |
1514 | { |
1515 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1516 | ||
86026630 | 1517 | cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; |
9d5fce16 | 1518 | if ((len > 1) && (spi->cur_midi > 0)) { |
e1e2093b | 1519 | u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); |
5a380b83 AD |
1520 | u32 midi = min_t(u32, |
1521 | DIV_ROUND_UP(spi->cur_midi, sck_period_ns), | |
1522 | FIELD_GET(STM32H7_SPI_CFG2_MIDI, | |
1523 | STM32H7_SPI_CFG2_MIDI)); | |
1524 | ||
dcbe0d84 AD |
1525 | |
1526 | dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", | |
1527 | sck_period_ns, midi, midi * sck_period_ns); | |
5a380b83 | 1528 | cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi); |
dcbe0d84 AD |
1529 | } |
1530 | ||
9d5fce16 CG |
1531 | writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & |
1532 | ~cfg2_clrb) | cfg2_setb, | |
1533 | spi->base + STM32H7_SPI_CFG2); | |
1534 | } | |
1535 | ||
1536 | /** | |
55166853 | 1537 | * stm32h7_spi_number_of_data - configure number of data at current transfer |
9d5fce16 | 1538 | * @spi: pointer to the spi controller data structure |
1c52be8b | 1539 | * @nb_words: transfer length (in words) |
9d5fce16 | 1540 | */ |
55166853 | 1541 | static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) |
9d5fce16 | 1542 | { |
5a380b83 AD |
1543 | if (nb_words <= STM32H7_SPI_TSIZE_MAX) { |
1544 | writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words), | |
9d5fce16 CG |
1545 | spi->base + STM32H7_SPI_CR2); |
1546 | } else { | |
1547 | return -EMSGSIZE; | |
1548 | } | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | /** | |
1554 | * stm32_spi_transfer_one_setup - common setup to transfer a single | |
1555 | * spi_transfer either using DMA or | |
1556 | * interrupts. | |
1c52be8b AV |
1557 | * @spi: pointer to the spi controller data structure |
1558 | * @spi_dev: pointer to the spi device | |
1559 | * @transfer: pointer to spi transfer | |
9d5fce16 CG |
1560 | */ |
1561 | static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, | |
1562 | struct spi_device *spi_dev, | |
1563 | struct spi_transfer *transfer) | |
1564 | { | |
1565 | unsigned long flags; | |
1566 | unsigned int comm_type; | |
1567 | int nb_words, ret = 0; | |
60ccb351 | 1568 | int mbr; |
9d5fce16 CG |
1569 | |
1570 | spin_lock_irqsave(&spi->lock, flags); | |
1571 | ||
3373e900 AD |
1572 | spi->cur_xferlen = transfer->len; |
1573 | ||
60ccb351 AV |
1574 | spi->cur_bpw = transfer->bits_per_word; |
1575 | spi->cfg->set_bpw(spi); | |
9d5fce16 | 1576 | |
60ccb351 AV |
1577 | /* Update spi->cur_speed with real clock speed */ |
1578 | mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, | |
1579 | spi->cfg->baud_rate_div_min, | |
1580 | spi->cfg->baud_rate_div_max); | |
1581 | if (mbr < 0) { | |
1582 | ret = mbr; | |
1583 | goto out; | |
9d5fce16 CG |
1584 | } |
1585 | ||
60ccb351 AV |
1586 | transfer->speed_hz = spi->cur_speed; |
1587 | stm32_spi_set_mbr(spi, mbr); | |
9d5fce16 | 1588 | |
60ccb351 AV |
1589 | comm_type = stm32_spi_communication_type(spi_dev, transfer); |
1590 | ret = spi->cfg->set_mode(spi, comm_type); | |
1591 | if (ret < 0) | |
1592 | goto out; | |
9d5fce16 | 1593 | |
60ccb351 | 1594 | spi->cur_comm = comm_type; |
9d5fce16 | 1595 | |
55166853 CG |
1596 | if (spi->cfg->set_data_idleness) |
1597 | spi->cfg->set_data_idleness(spi, transfer->len); | |
dcbe0d84 | 1598 | |
128ebb89 AD |
1599 | if (spi->cur_bpw <= 8) |
1600 | nb_words = transfer->len; | |
1601 | else if (spi->cur_bpw <= 16) | |
1602 | nb_words = DIV_ROUND_UP(transfer->len * 8, 16); | |
1603 | else | |
1604 | nb_words = DIV_ROUND_UP(transfer->len * 8, 32); | |
dcbe0d84 | 1605 | |
55166853 CG |
1606 | if (spi->cfg->set_number_of_data) { |
1607 | ret = spi->cfg->set_number_of_data(spi, nb_words); | |
1608 | if (ret < 0) | |
1609 | goto out; | |
1610 | } | |
dcbe0d84 | 1611 | |
dcbe0d84 AD |
1612 | dev_dbg(spi->dev, "transfer communication mode set to %d\n", |
1613 | spi->cur_comm); | |
1614 | dev_dbg(spi->dev, | |
1615 | "data frame of %d-bit, data packet of %d data frames\n", | |
1616 | spi->cur_bpw, spi->cur_fthlv); | |
1617 | dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); | |
1618 | dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", | |
1619 | spi->cur_xferlen, nb_words); | |
1620 | dev_dbg(spi->dev, "dma %s\n", | |
1621 | (spi->cur_usedma) ? "enabled" : "disabled"); | |
1622 | ||
1623 | out: | |
1624 | spin_unlock_irqrestore(&spi->lock, flags); | |
1625 | ||
1626 | return ret; | |
1627 | } | |
1628 | ||
1629 | /** | |
1630 | * stm32_spi_transfer_one - transfer a single spi_transfer | |
1c52be8b AV |
1631 | * @master: controller master interface |
1632 | * @spi_dev: pointer to the spi device | |
1633 | * @transfer: pointer to spi transfer | |
dcbe0d84 AD |
1634 | * |
1635 | * It must return 0 if the transfer is finished or 1 if the transfer is still | |
1636 | * in progress. | |
1637 | */ | |
1638 | static int stm32_spi_transfer_one(struct spi_master *master, | |
1639 | struct spi_device *spi_dev, | |
1640 | struct spi_transfer *transfer) | |
1641 | { | |
1642 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1643 | int ret; | |
1644 | ||
2269f5a8 AV |
1645 | /* Don't do anything on 0 bytes transfers */ |
1646 | if (transfer->len == 0) | |
1647 | return 0; | |
1648 | ||
dcbe0d84 AD |
1649 | spi->tx_buf = transfer->tx_buf; |
1650 | spi->rx_buf = transfer->rx_buf; | |
1651 | spi->tx_len = spi->tx_buf ? transfer->len : 0; | |
1652 | spi->rx_len = spi->rx_buf ? transfer->len : 0; | |
1653 | ||
c67ad368 | 1654 | spi->cur_usedma = (master->can_dma && |
2cbee7f8 | 1655 | master->can_dma(master, spi_dev, transfer)); |
dcbe0d84 AD |
1656 | |
1657 | ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); | |
1658 | if (ret) { | |
1659 | dev_err(spi->dev, "SPI transfer setup failed\n"); | |
1660 | return ret; | |
1661 | } | |
1662 | ||
1663 | if (spi->cur_usedma) | |
1664 | return stm32_spi_transfer_one_dma(spi, transfer); | |
1665 | else | |
55166853 | 1666 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1667 | } |
1668 | ||
1669 | /** | |
1670 | * stm32_spi_unprepare_msg - relax the hardware | |
1c52be8b AV |
1671 | * @master: controller master interface |
1672 | * @msg: pointer to the spi message | |
dcbe0d84 AD |
1673 | */ |
1674 | static int stm32_spi_unprepare_msg(struct spi_master *master, | |
1675 | struct spi_message *msg) | |
1676 | { | |
1677 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1678 | ||
55166853 | 1679 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1680 | |
1681 | return 0; | |
1682 | } | |
1683 | ||
00505edf CG |
1684 | /** |
1685 | * stm32f4_spi_config - Configure SPI controller as SPI master | |
1c52be8b | 1686 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1687 | */ |
1688 | static int stm32f4_spi_config(struct stm32_spi *spi) | |
1689 | { | |
1690 | unsigned long flags; | |
1691 | ||
1692 | spin_lock_irqsave(&spi->lock, flags); | |
1693 | ||
1694 | /* Ensure I2SMOD bit is kept cleared */ | |
1695 | stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, | |
1696 | STM32F4_SPI_I2SCFGR_I2SMOD); | |
1697 | ||
1698 | /* | |
1699 | * - SS input value high | |
1700 | * - transmitter half duplex direction | |
1701 | * - Set the master mode (default Motorola mode) | |
1702 | * - Consider 1 master/n slaves configuration and | |
1703 | * SS input value is determined by the SSI bit | |
1704 | */ | |
1705 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | | |
1706 | STM32F4_SPI_CR1_BIDIOE | | |
1707 | STM32F4_SPI_CR1_MSTR | | |
1708 | STM32F4_SPI_CR1_SSM); | |
1709 | ||
1710 | spin_unlock_irqrestore(&spi->lock, flags); | |
1711 | ||
1712 | return 0; | |
1713 | } | |
1714 | ||
dcbe0d84 | 1715 | /** |
55166853 | 1716 | * stm32h7_spi_config - Configure SPI controller as SPI master |
1c52be8b | 1717 | * @spi: pointer to the spi controller data structure |
dcbe0d84 | 1718 | */ |
55166853 | 1719 | static int stm32h7_spi_config(struct stm32_spi *spi) |
dcbe0d84 AD |
1720 | { |
1721 | unsigned long flags; | |
1722 | ||
1723 | spin_lock_irqsave(&spi->lock, flags); | |
1724 | ||
1725 | /* Ensure I2SMOD bit is kept cleared */ | |
86026630 CG |
1726 | stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, |
1727 | STM32H7_SPI_I2SCFGR_I2SMOD); | |
dcbe0d84 AD |
1728 | |
1729 | /* | |
1730 | * - SS input value high | |
1731 | * - transmitter half duplex direction | |
1732 | * - automatic communication suspend when RX-Fifo is full | |
1733 | */ | |
86026630 CG |
1734 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | |
1735 | STM32H7_SPI_CR1_HDDIR | | |
1736 | STM32H7_SPI_CR1_MASRX); | |
dcbe0d84 AD |
1737 | |
1738 | /* | |
1739 | * - Set the master mode (default Motorola mode) | |
1740 | * - Consider 1 master/n slaves configuration and | |
1741 | * SS input value is determined by the SSI bit | |
1742 | * - keep control of all associated GPIOs | |
1743 | */ | |
86026630 CG |
1744 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | |
1745 | STM32H7_SPI_CFG2_SSM | | |
1746 | STM32H7_SPI_CFG2_AFCNTR); | |
dcbe0d84 AD |
1747 | |
1748 | spin_unlock_irqrestore(&spi->lock, flags); | |
1749 | ||
1750 | return 0; | |
1751 | } | |
1752 | ||
00505edf CG |
1753 | static const struct stm32_spi_cfg stm32f4_spi_cfg = { |
1754 | .regs = &stm32f4_spi_regspec, | |
1755 | .get_bpw_mask = stm32f4_spi_get_bpw_mask, | |
1756 | .disable = stm32f4_spi_disable, | |
1757 | .config = stm32f4_spi_config, | |
1758 | .set_bpw = stm32f4_spi_set_bpw, | |
1759 | .set_mode = stm32f4_spi_set_mode, | |
1760 | .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start, | |
1761 | .dma_tx_cb = stm32f4_spi_dma_tx_cb, | |
1762 | .dma_rx_cb = stm32f4_spi_dma_rx_cb, | |
1763 | .transfer_one_irq = stm32f4_spi_transfer_one_irq, | |
1764 | .irq_handler_event = stm32f4_spi_irq_event, | |
1765 | .irq_handler_thread = stm32f4_spi_irq_thread, | |
1766 | .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN, | |
1767 | .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX, | |
1768 | .has_fifo = false, | |
1769 | }; | |
1770 | ||
55166853 CG |
1771 | static const struct stm32_spi_cfg stm32h7_spi_cfg = { |
1772 | .regs = &stm32h7_spi_regspec, | |
1773 | .get_fifo_size = stm32h7_spi_get_fifo_size, | |
1774 | .get_bpw_mask = stm32h7_spi_get_bpw_mask, | |
1775 | .disable = stm32h7_spi_disable, | |
1776 | .config = stm32h7_spi_config, | |
1777 | .set_bpw = stm32h7_spi_set_bpw, | |
1778 | .set_mode = stm32h7_spi_set_mode, | |
1779 | .set_data_idleness = stm32h7_spi_data_idleness, | |
1780 | .set_number_of_data = stm32h7_spi_number_of_data, | |
1781 | .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start, | |
1782 | .dma_rx_cb = stm32h7_spi_dma_cb, | |
1783 | .dma_tx_cb = stm32h7_spi_dma_cb, | |
1784 | .transfer_one_irq = stm32h7_spi_transfer_one_irq, | |
1785 | .irq_handler_thread = stm32h7_spi_irq_thread, | |
1786 | .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN, | |
1787 | .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX, | |
1788 | .has_fifo = true, | |
1789 | }; | |
1790 | ||
dcbe0d84 | 1791 | static const struct of_device_id stm32_spi_of_match[] = { |
55166853 | 1792 | { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg }, |
00505edf | 1793 | { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg }, |
dcbe0d84 AD |
1794 | {}, |
1795 | }; | |
1796 | MODULE_DEVICE_TABLE(of, stm32_spi_of_match); | |
1797 | ||
1798 | static int stm32_spi_probe(struct platform_device *pdev) | |
1799 | { | |
1800 | struct spi_master *master; | |
1801 | struct stm32_spi *spi; | |
1802 | struct resource *res; | |
1c75cfd5 | 1803 | struct reset_control *rst; |
8a6553ec | 1804 | int ret; |
dcbe0d84 | 1805 | |
79c6246a | 1806 | master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); |
dcbe0d84 AD |
1807 | if (!master) { |
1808 | dev_err(&pdev->dev, "spi master allocation failed\n"); | |
1809 | return -ENOMEM; | |
1810 | } | |
1811 | platform_set_drvdata(pdev, master); | |
1812 | ||
1813 | spi = spi_master_get_devdata(master); | |
1814 | spi->dev = &pdev->dev; | |
1815 | spi->master = master; | |
1816 | spin_lock_init(&spi->lock); | |
1817 | ||
55166853 CG |
1818 | spi->cfg = (const struct stm32_spi_cfg *) |
1819 | of_match_device(pdev->dev.driver->of_match_table, | |
1820 | &pdev->dev)->data; | |
1821 | ||
dcbe0d84 AD |
1822 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1823 | spi->base = devm_ioremap_resource(&pdev->dev, res); | |
79c6246a AV |
1824 | if (IS_ERR(spi->base)) |
1825 | return PTR_ERR(spi->base); | |
55166853 | 1826 | |
dcbe0d84 AD |
1827 | spi->phys_addr = (dma_addr_t)res->start; |
1828 | ||
1829 | spi->irq = platform_get_irq(pdev, 0); | |
79c6246a AV |
1830 | if (spi->irq <= 0) |
1831 | return dev_err_probe(&pdev->dev, spi->irq, | |
1832 | "failed to get irq\n"); | |
1833 | ||
55166853 CG |
1834 | ret = devm_request_threaded_irq(&pdev->dev, spi->irq, |
1835 | spi->cfg->irq_handler_event, | |
1836 | spi->cfg->irq_handler_thread, | |
1837 | IRQF_ONESHOT, pdev->name, master); | |
dcbe0d84 AD |
1838 | if (ret) { |
1839 | dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, | |
1840 | ret); | |
79c6246a | 1841 | return ret; |
dcbe0d84 AD |
1842 | } |
1843 | ||
d4c9134a | 1844 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
dcbe0d84 AD |
1845 | if (IS_ERR(spi->clk)) { |
1846 | ret = PTR_ERR(spi->clk); | |
1847 | dev_err(&pdev->dev, "clk get failed: %d\n", ret); | |
79c6246a | 1848 | return ret; |
dcbe0d84 AD |
1849 | } |
1850 | ||
1851 | ret = clk_prepare_enable(spi->clk); | |
1852 | if (ret) { | |
1853 | dev_err(&pdev->dev, "clk enable failed: %d\n", ret); | |
79c6246a | 1854 | return ret; |
dcbe0d84 AD |
1855 | } |
1856 | spi->clk_rate = clk_get_rate(spi->clk); | |
1857 | if (!spi->clk_rate) { | |
1858 | dev_err(&pdev->dev, "clk rate = 0\n"); | |
1859 | ret = -EINVAL; | |
3dbb3eef | 1860 | goto err_clk_disable; |
dcbe0d84 AD |
1861 | } |
1862 | ||
c63b95b7 AV |
1863 | rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); |
1864 | if (rst) { | |
1865 | if (IS_ERR(rst)) { | |
1866 | ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), | |
1867 | "failed to get reset\n"); | |
1868 | goto err_clk_disable; | |
1869 | } | |
1870 | ||
1c75cfd5 | 1871 | reset_control_assert(rst); |
dcbe0d84 | 1872 | udelay(2); |
1c75cfd5 | 1873 | reset_control_deassert(rst); |
dcbe0d84 AD |
1874 | } |
1875 | ||
55166853 CG |
1876 | if (spi->cfg->has_fifo) |
1877 | spi->fifo_size = spi->cfg->get_fifo_size(spi); | |
dcbe0d84 | 1878 | |
55166853 | 1879 | ret = spi->cfg->config(spi); |
dcbe0d84 AD |
1880 | if (ret) { |
1881 | dev_err(&pdev->dev, "controller configuration failed: %d\n", | |
1882 | ret); | |
1883 | goto err_clk_disable; | |
1884 | } | |
1885 | ||
1886 | master->dev.of_node = pdev->dev.of_node; | |
1887 | master->auto_runtime_pm = true; | |
1888 | master->bus_num = pdev->id; | |
d6cea11b | 1889 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | |
6962b055 | 1890 | SPI_3WIRE; |
55166853 CG |
1891 | master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); |
1892 | master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; | |
1893 | master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; | |
8a6553ec | 1894 | master->use_gpio_descriptors = true; |
dcbe0d84 AD |
1895 | master->prepare_message = stm32_spi_prepare_msg; |
1896 | master->transfer_one = stm32_spi_transfer_one; | |
1897 | master->unprepare_message = stm32_spi_unprepare_msg; | |
61367d0b | 1898 | master->flags = SPI_MASTER_MUST_TX; |
dcbe0d84 | 1899 | |
0a454258 PU |
1900 | spi->dma_tx = dma_request_chan(spi->dev, "tx"); |
1901 | if (IS_ERR(spi->dma_tx)) { | |
1902 | ret = PTR_ERR(spi->dma_tx); | |
1903 | spi->dma_tx = NULL; | |
1904 | if (ret == -EPROBE_DEFER) | |
1905 | goto err_clk_disable; | |
1906 | ||
dcbe0d84 | 1907 | dev_warn(&pdev->dev, "failed to request tx dma channel\n"); |
0a454258 | 1908 | } else { |
dcbe0d84 | 1909 | master->dma_tx = spi->dma_tx; |
0a454258 PU |
1910 | } |
1911 | ||
1912 | spi->dma_rx = dma_request_chan(spi->dev, "rx"); | |
1913 | if (IS_ERR(spi->dma_rx)) { | |
1914 | ret = PTR_ERR(spi->dma_rx); | |
1915 | spi->dma_rx = NULL; | |
1916 | if (ret == -EPROBE_DEFER) | |
1917 | goto err_dma_release; | |
dcbe0d84 | 1918 | |
dcbe0d84 | 1919 | dev_warn(&pdev->dev, "failed to request rx dma channel\n"); |
0a454258 | 1920 | } else { |
dcbe0d84 | 1921 | master->dma_rx = spi->dma_rx; |
0a454258 | 1922 | } |
dcbe0d84 AD |
1923 | |
1924 | if (spi->dma_tx || spi->dma_rx) | |
1925 | master->can_dma = stm32_spi_can_dma; | |
1926 | ||
038ac869 AD |
1927 | pm_runtime_set_active(&pdev->dev); |
1928 | pm_runtime_enable(&pdev->dev); | |
1929 | ||
8d559a64 | 1930 | ret = spi_register_master(master); |
dcbe0d84 AD |
1931 | if (ret) { |
1932 | dev_err(&pdev->dev, "spi master registration failed: %d\n", | |
1933 | ret); | |
0a454258 | 1934 | goto err_pm_disable; |
dcbe0d84 AD |
1935 | } |
1936 | ||
dcbe0d84 AD |
1937 | dev_info(&pdev->dev, "driver initialized\n"); |
1938 | ||
1939 | return 0; | |
1940 | ||
0a454258 PU |
1941 | err_pm_disable: |
1942 | pm_runtime_disable(&pdev->dev); | |
dcbe0d84 AD |
1943 | err_dma_release: |
1944 | if (spi->dma_tx) | |
1945 | dma_release_channel(spi->dma_tx); | |
1946 | if (spi->dma_rx) | |
1947 | dma_release_channel(spi->dma_rx); | |
1948 | err_clk_disable: | |
1949 | clk_disable_unprepare(spi->clk); | |
dcbe0d84 AD |
1950 | |
1951 | return ret; | |
1952 | } | |
1953 | ||
1954 | static int stm32_spi_remove(struct platform_device *pdev) | |
1955 | { | |
1956 | struct spi_master *master = platform_get_drvdata(pdev); | |
1957 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1958 | ||
8d559a64 | 1959 | spi_unregister_master(master); |
55166853 | 1960 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1961 | |
1962 | if (master->dma_tx) | |
1963 | dma_release_channel(master->dma_tx); | |
1964 | if (master->dma_rx) | |
1965 | dma_release_channel(master->dma_rx); | |
1966 | ||
1967 | clk_disable_unprepare(spi->clk); | |
1968 | ||
038ac869 AD |
1969 | pm_runtime_disable(&pdev->dev); |
1970 | ||
db96bf97 AD |
1971 | pinctrl_pm_select_sleep_state(&pdev->dev); |
1972 | ||
dcbe0d84 AD |
1973 | return 0; |
1974 | } | |
1975 | ||
12ef51b1 | 1976 | static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev) |
038ac869 AD |
1977 | { |
1978 | struct spi_master *master = dev_get_drvdata(dev); | |
1979 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1980 | ||
1981 | clk_disable_unprepare(spi->clk); | |
1982 | ||
db96bf97 | 1983 | return pinctrl_pm_select_sleep_state(dev); |
038ac869 AD |
1984 | } |
1985 | ||
12ef51b1 | 1986 | static int __maybe_unused stm32_spi_runtime_resume(struct device *dev) |
038ac869 AD |
1987 | { |
1988 | struct spi_master *master = dev_get_drvdata(dev); | |
1989 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
db96bf97 AD |
1990 | int ret; |
1991 | ||
1992 | ret = pinctrl_pm_select_default_state(dev); | |
1993 | if (ret) | |
1994 | return ret; | |
038ac869 AD |
1995 | |
1996 | return clk_prepare_enable(spi->clk); | |
1997 | } | |
038ac869 | 1998 | |
12ef51b1 | 1999 | static int __maybe_unused stm32_spi_suspend(struct device *dev) |
dcbe0d84 AD |
2000 | { |
2001 | struct spi_master *master = dev_get_drvdata(dev); | |
dcbe0d84 AD |
2002 | int ret; |
2003 | ||
2004 | ret = spi_master_suspend(master); | |
2005 | if (ret) | |
2006 | return ret; | |
2007 | ||
038ac869 | 2008 | return pm_runtime_force_suspend(dev); |
dcbe0d84 AD |
2009 | } |
2010 | ||
12ef51b1 | 2011 | static int __maybe_unused stm32_spi_resume(struct device *dev) |
dcbe0d84 AD |
2012 | { |
2013 | struct spi_master *master = dev_get_drvdata(dev); | |
2014 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
2015 | int ret; | |
2016 | ||
038ac869 | 2017 | ret = pm_runtime_force_resume(dev); |
dcbe0d84 AD |
2018 | if (ret) |
2019 | return ret; | |
038ac869 | 2020 | |
dcbe0d84 | 2021 | ret = spi_master_resume(master); |
db96bf97 | 2022 | if (ret) { |
dcbe0d84 | 2023 | clk_disable_unprepare(spi->clk); |
db96bf97 AD |
2024 | return ret; |
2025 | } | |
dcbe0d84 | 2026 | |
db96bf97 | 2027 | ret = pm_runtime_get_sync(dev); |
c170a5a3 | 2028 | if (ret < 0) { |
900ccdcb | 2029 | pm_runtime_put_noidle(dev); |
db96bf97 AD |
2030 | dev_err(dev, "Unable to power device:%d\n", ret); |
2031 | return ret; | |
2032 | } | |
2033 | ||
2034 | spi->cfg->config(spi); | |
2035 | ||
2036 | pm_runtime_mark_last_busy(dev); | |
2037 | pm_runtime_put_autosuspend(dev); | |
2038 | ||
2039 | return 0; | |
dcbe0d84 | 2040 | } |
dcbe0d84 | 2041 | |
038ac869 AD |
2042 | static const struct dev_pm_ops stm32_spi_pm_ops = { |
2043 | SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) | |
2044 | SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, | |
2045 | stm32_spi_runtime_resume, NULL) | |
2046 | }; | |
dcbe0d84 AD |
2047 | |
2048 | static struct platform_driver stm32_spi_driver = { | |
2049 | .probe = stm32_spi_probe, | |
2050 | .remove = stm32_spi_remove, | |
2051 | .driver = { | |
2052 | .name = DRIVER_NAME, | |
2053 | .pm = &stm32_spi_pm_ops, | |
2054 | .of_match_table = stm32_spi_of_match, | |
2055 | }, | |
2056 | }; | |
2057 | ||
2058 | module_platform_driver(stm32_spi_driver); | |
2059 | ||
2060 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2061 | MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); | |
2062 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); | |
2063 | MODULE_LICENSE("GPL v2"); |