[linux-2.6-block.git] / drivers / spi / spi-sprd-adi.c

/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>

/* Registers definitions for ADI controller */
#define REG_ADI_CTRL0			0x4
#define REG_ADI_CHN_PRIL		0x8
#define REG_ADI_CHN_PRIH		0xc
#define REG_ADI_INT_EN			0x10
#define REG_ADI_INT_RAW			0x14
#define REG_ADI_INT_MASK		0x18
#define REG_ADI_INT_CLR			0x1c
#define REG_ADI_GSSI_CFG0		0x20
#define REG_ADI_GSSI_CFG1		0x24
#define REG_ADI_RD_CMD			0x28
#define REG_ADI_RD_DATA			0x2c
#define REG_ADI_ARM_FIFO_STS		0x30
#define REG_ADI_STS			0x34
#define REG_ADI_EVT_FIFO_STS		0x38
#define REG_ADI_ARM_CMD_STS		0x3c
#define REG_ADI_CHN_EN			0x40
#define REG_ADI_CHN_ADDR(id)		(0x44 + (id - 2) * 4)
#define REG_ADI_CHN_EN1			0x20c

/* Bits definitions for register REG_ADI_GSSI_CFG0 */
#define BIT_CLK_ALL_ON			BIT(30)

/* Bits definitions for register REG_ADI_RD_DATA */
#define BIT_RD_CMD_BUSY			BIT(31)
#define RD_ADDR_SHIFT			16
#define RD_VALUE_MASK			GENMASK(15, 0)
#define RD_ADDR_MASK			GENMASK(30, 16)

/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
#define BIT_FIFO_FULL			BIT(11)
#define BIT_FIFO_EMPTY			BIT(10)

/*
 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
 * The slave devices address offset is always 0x8000 and size is 4K.
 */
#define ADI_SLAVE_ADDR_SIZE		SZ_4K
#define ADI_SLAVE_OFFSET		0x8000

/* Timeout (ms) for the trylock of hardware spinlocks */
#define ADI_HWSPINLOCK_TIMEOUT		5000
/*
 * ADI controller has 50 channels including 2 software channels
 * and 48 hardware channels.
 */
#define ADI_HW_CHNS			50

#define ADI_FIFO_DRAIN_TIMEOUT		1000
#define ADI_READ_TIMEOUT		2000
#define REG_ADDR_LOW_MASK		GENMASK(11, 0)

/* Registers definitions for PMIC watchdog controller */
#define REG_WDG_LOAD_LOW		0x80
#define REG_WDG_LOAD_HIGH		0x84
#define REG_WDG_CTRL			0x88
#define REG_WDG_LOCK			0xa0

/* Bits definitions for register REG_WDG_CTRL */
#define BIT_WDG_RUN			BIT(1)
#define BIT_WDG_RST			BIT(3)

/* Registers definitions for PMIC */
#define PMIC_RST_STATUS			0xee8
#define PMIC_MODULE_EN			0xc08
#define PMIC_CLK_EN			0xc18
#define BIT_WDG_EN			BIT(2)

/* Definition of PMIC reset status register */
#define HWRST_STATUS_SECURITY		0x02
#define HWRST_STATUS_RECOVERY		0x20
#define HWRST_STATUS_NORMAL		0x40
#define HWRST_STATUS_ALARM		0x50
#define HWRST_STATUS_SLEEP		0x60
#define HWRST_STATUS_FASTBOOT		0x30
#define HWRST_STATUS_SPECIAL		0x70
#define HWRST_STATUS_PANIC		0x80
#define HWRST_STATUS_CFTREBOOT		0x90
#define HWRST_STATUS_AUTODLOADER	0xa0
#define HWRST_STATUS_IQMODE		0xb0
#define HWRST_STATUS_SPRDISK		0xc0

/* Use default timeout 50 ms that converts to watchdog values */
#define WDG_LOAD_VAL			((50 * 1000) / 32768)
#define WDG_LOAD_MASK			GENMASK(15, 0)
#define WDG_UNLOCK_KEY			0xe551

struct sprd_adi {
	struct spi_controller	*ctlr;
	struct device		*dev;
	void __iomem		*base;
	struct hwspinlock	*hwlock;
	unsigned long		slave_vbase;
	unsigned long		slave_pbase;
	struct notifier_block	restart_handler;
};

static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
{
	if (paddr < sadi->slave_pbase || paddr >
	    (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
		dev_err(sadi->dev,
			"slave physical address is incorrect, addr = 0x%x\n",
			paddr);
		return -EINVAL;
	}

	return 0;
}

static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
{
	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
}

static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
{
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	u32 sts;

	do {
		sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
		if (sts & BIT_FIFO_EMPTY)
			break;

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "drain write fifo timeout\n");
		return -EBUSY;
	}

	return 0;
}

static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
{
	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
}

static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
{
	int read_timeout = ADI_READ_TIMEOUT;
	unsigned long flags;
	u32 val, rd_addr;
	int ret;

	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
					  ADI_HWSPINLOCK_TIMEOUT,
					  &flags);
	if (ret) {
		dev_err(sadi->dev, "get the hw lock failed\n");
		return ret;
	}

	/*
	 * Set the physical register address need to read into RD_CMD register,
	 * then ADI controller will start to transfer automatically.
	 */
	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);

	/*
	 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	 * simultaneously when writing read command to register, and the
	 * BIT_RD_CMD_BUSY will be cleared after the read operation is
	 * completed.
	 */
	do {
		val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
		if (!(val & BIT_RD_CMD_BUSY))
			break;

		cpu_relax();
	} while (--read_timeout);

	if (read_timeout == 0) {
		dev_err(sadi->dev, "ADI read timeout\n");
		ret = -EBUSY;
		goto out;
	}

	/*
	 * The return value includes data and read register address, from bit 0
	 * to bit 15 are data, and from bit 16 to bit 30 are read register
	 * address. Then we can check the returned register address to validate
	 * data.
	 */
	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;

	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
		dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
			reg_paddr, val);
		ret = -EIO;
		goto out;
	}

	*read_val = val & RD_VALUE_MASK;

out:
	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
{
	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	unsigned long flags;
	int ret;

	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
					  ADI_HWSPINLOCK_TIMEOUT,
					  &flags);
	if (ret) {
		dev_err(sadi->dev, "get the hw lock failed\n");
		return ret;
	}

	ret = sprd_adi_drain_fifo(sadi);
	if (ret < 0)
		goto out;

	/*
	 * we should wait for write fifo is empty before writing data to PMIC
	 * registers.
	 */
	do {
		if (!sprd_adi_fifo_is_full(sadi)) {
			writel_relaxed(val, (void __iomem *)reg);
			break;
		}

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "write fifo is full\n");
		ret = -EBUSY;
	}

out:
	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_transfer_one(struct spi_controller *ctlr,
				 struct spi_device *spi_dev,
				 struct spi_transfer *t)
{
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	u32 phy_reg, val;
	int ret;

	if (t->rx_buf) {
		phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;

		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		ret = sprd_adi_read(sadi, phy_reg, &val);
		if (ret)
			return ret;

		*(u32 *)t->rx_buf = val;
	} else if (t->tx_buf) {
		u32 *p = (u32 *)t->tx_buf;

		/*
		 * Get the physical register address need to write and convert
		 * the physical address to virtual address. Since we need
		 * virtual register address to write.
		 */
		phy_reg = *p++ + sadi->slave_pbase;
		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		val = *p;
		ret = sprd_adi_write(sadi, phy_reg, val);
		if (ret)
			return ret;
	} else {
		dev_err(sadi->dev, "no buffer for transfer\n");
		return -EINVAL;
	}

	return 0;
}

static int sprd_adi_restart_handler(struct notifier_block *this,
				    unsigned long mode, void *cmd)
{
	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
					     restart_handler);
	u32 val, reboot_mode = 0;

	if (!cmd)
		reboot_mode = HWRST_STATUS_NORMAL;
	else if (!strncmp(cmd, "recovery", 8))
		reboot_mode = HWRST_STATUS_RECOVERY;
	else if (!strncmp(cmd, "alarm", 5))
		reboot_mode = HWRST_STATUS_ALARM;
	else if (!strncmp(cmd, "fastsleep", 9))
		reboot_mode = HWRST_STATUS_SLEEP;
	else if (!strncmp(cmd, "bootloader", 10))
		reboot_mode = HWRST_STATUS_FASTBOOT;
	else if (!strncmp(cmd, "panic", 5))
		reboot_mode = HWRST_STATUS_PANIC;
	else if (!strncmp(cmd, "special", 7))
		reboot_mode = HWRST_STATUS_SPECIAL;
	else if (!strncmp(cmd, "cftreboot", 9))
		reboot_mode = HWRST_STATUS_CFTREBOOT;
	else if (!strncmp(cmd, "autodloader", 11))
		reboot_mode = HWRST_STATUS_AUTODLOADER;
	else if (!strncmp(cmd, "iqmode", 6))
		reboot_mode = HWRST_STATUS_IQMODE;
	else if (!strncmp(cmd, "sprdisk", 7))
		reboot_mode = HWRST_STATUS_SPRDISK;
	else if (!strncmp(cmd, "tospanic", 8))
		reboot_mode = HWRST_STATUS_SECURITY;
	else
		reboot_mode = HWRST_STATUS_NORMAL;

	/* Record the reboot mode */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	val |= reboot_mode;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);

	/* Enable the interface clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);

	/* Enable the work clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);

	/* Unlock the watchdog */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);

	/* Load the watchdog timeout value, 50ms is always enough. */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
		       WDG_LOAD_VAL & WDG_LOAD_MASK);
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);

	/* Start the watchdog to reset system */
	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	val |= BIT_WDG_RUN | BIT_WDG_RST;
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);

	mdelay(1000);

	dev_emerg(sadi->dev, "Unable to restart system\n");
	return NOTIFY_DONE;
}

static void sprd_adi_hw_init(struct sprd_adi *sadi)
{
	struct device_node *np = sadi->dev->of_node;
	int i, size, chn_cnt;
	const __be32 *list;
	u32 tmp;

	/* Set all channels as default priority */
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);

	/* Set clock auto gate mode */
	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	tmp &= ~BIT_CLK_ALL_ON;
	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);

	/* Set hardware channels setting */
	list = of_get_property(np, "sprd,hw-channels", &size);
	if (!list || !size) {
		dev_info(sadi->dev, "no hw channels setting in node\n");
		return;
	}

	chn_cnt = size / 8;
	for (i = 0; i < chn_cnt; i++) {
		u32 value;
		u32 chn_id = be32_to_cpu(*list++);
		u32 chn_config = be32_to_cpu(*list++);

		/* Channel 0 and 1 are software channels */
		if (chn_id < 2)
			continue;

		writel_relaxed(chn_config, sadi->base +
			       REG_ADI_CHN_ADDR(chn_id));

		if (chn_id < 32) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
			value |= BIT(chn_id);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
		} else if (chn_id < ADI_HW_CHNS) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
			value |= BIT(chn_id - 32);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
		}
	}
}

static int sprd_adi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_controller *ctlr;
	struct sprd_adi *sadi;
	struct resource *res;
	u32 num_chipselect;
	int ret;

	if (!np) {
		dev_err(&pdev->dev, "can not find the adi bus node\n");
		return -ENODEV;
	}

	pdev->id = of_alias_get_id(np, "spi");
	num_chipselect = of_get_child_count(np);

	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	if (!ctlr)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, ctlr);
	sadi = spi_controller_get_devdata(ctlr);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sadi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sadi->base)) {
		ret = PTR_ERR(sadi->base);
		goto put_ctlr;
	}

	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	sadi->ctlr = ctlr;
	sadi->dev = &pdev->dev;
	ret = of_hwspin_lock_get_id_byname(np, "adi");
	if (ret < 0) {
		dev_err(&pdev->dev, "can not get the hardware spinlock\n");
		goto put_ctlr;
	}

	sadi->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
	if (!sadi->hwlock) {
		ret = -ENXIO;
		goto put_ctlr;
	}

	sprd_adi_hw_init(sadi);

	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->bus_num = pdev->id;
	ctlr->num_chipselect = num_chipselect;
	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	ctlr->bits_per_word_mask = 0;
	ctlr->transfer_one = sprd_adi_transfer_one;

	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	if (ret) {
		dev_err(&pdev->dev, "failed to register SPI controller\n");
		goto put_ctlr;
	}

	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	sadi->restart_handler.priority = 128;
	ret = register_restart_handler(&sadi->restart_handler);
	if (ret) {
		dev_err(&pdev->dev, "can not register restart handler\n");
		goto put_ctlr;
	}

	return 0;

put_ctlr:
	spi_controller_put(ctlr);
	return ret;
}

static int sprd_adi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);

	unregister_restart_handler(&sadi->restart_handler);
	return 0;
}

static const struct of_device_id sprd_adi_of_match[] = {
	{
		.compatible = "sprd,sc9860-adi",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, sprd_adi_of_match);

static struct platform_driver sprd_adi_driver = {
	.driver = {
		.name = "sprd-adi",
		.of_match_table = sprd_adi_of_match,
	},
	.probe = sprd_adi_probe,
	.remove = sprd_adi_remove,
};
module_platform_driver(sprd_adi_driver);

MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7e2903cb BW	1	/*
	2	* Copyright (C) 2017 Spreadtrum Communications Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
ac177501	7	#include <linux/delay.h>
7e2903cb BW	8	#include <linux/hwspinlock.h>
	9	#include <linux/init.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/of_device.h>
	15	#include <linux/platform_device.h>
ac177501	16	#include <linux/reboot.h>
7e2903cb BW	17	#include <linux/spi/spi.h>
	18	#include <linux/sizes.h>
	19
	20	/* Registers definitions for ADI controller */
	21	#define REG_ADI_CTRL0 0x4
	22	#define REG_ADI_CHN_PRIL 0x8
	23	#define REG_ADI_CHN_PRIH 0xc
	24	#define REG_ADI_INT_EN 0x10
	25	#define REG_ADI_INT_RAW 0x14
	26	#define REG_ADI_INT_MASK 0x18
	27	#define REG_ADI_INT_CLR 0x1c
	28	#define REG_ADI_GSSI_CFG0 0x20
	29	#define REG_ADI_GSSI_CFG1 0x24
	30	#define REG_ADI_RD_CMD 0x28
	31	#define REG_ADI_RD_DATA 0x2c
	32	#define REG_ADI_ARM_FIFO_STS 0x30
	33	#define REG_ADI_STS 0x34
	34	#define REG_ADI_EVT_FIFO_STS 0x38
	35	#define REG_ADI_ARM_CMD_STS 0x3c
	36	#define REG_ADI_CHN_EN 0x40
	37	#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
	38	#define REG_ADI_CHN_EN1 0x20c
	39
	40	/* Bits definitions for register REG_ADI_GSSI_CFG0 */
	41	#define BIT_CLK_ALL_ON BIT(30)
	42
	43	/* Bits definitions for register REG_ADI_RD_DATA */
	44	#define BIT_RD_CMD_BUSY BIT(31)
	45	#define RD_ADDR_SHIFT 16
	46	#define RD_VALUE_MASK GENMASK(15, 0)
	47	#define RD_ADDR_MASK GENMASK(30, 16)
	48
	49	/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
	50	#define BIT_FIFO_FULL BIT(11)
	51	#define BIT_FIFO_EMPTY BIT(10)
	52
	53	/*
	54	* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
	55	* The slave devices address offset is always 0x8000 and size is 4K.
	56	*/
	57	#define ADI_SLAVE_ADDR_SIZE SZ_4K
	58	#define ADI_SLAVE_OFFSET 0x8000
	59
	60	/* Timeout (ms) for the trylock of hardware spinlocks */
	61	#define ADI_HWSPINLOCK_TIMEOUT 5000
	62	/*
	63	* ADI controller has 50 channels including 2 software channels
	64	* and 48 hardware channels.
	65	*/
	66	#define ADI_HW_CHNS 50
	67
	68	#define ADI_FIFO_DRAIN_TIMEOUT 1000
	69	#define ADI_READ_TIMEOUT 2000
	70	#define REG_ADDR_LOW_MASK GENMASK(11, 0)
	71
ac177501 BW	72	/* Registers definitions for PMIC watchdog controller */
	73	#define REG_WDG_LOAD_LOW 0x80
	74	#define REG_WDG_LOAD_HIGH 0x84
	75	#define REG_WDG_CTRL 0x88
	76	#define REG_WDG_LOCK 0xa0
	77
	78	/* Bits definitions for register REG_WDG_CTRL */
	79	#define BIT_WDG_RUN BIT(1)
	80	#define BIT_WDG_RST BIT(3)
	81
	82	/* Registers definitions for PMIC */
	83	#define PMIC_RST_STATUS 0xee8
	84	#define PMIC_MODULE_EN 0xc08
	85	#define PMIC_CLK_EN 0xc18
	86	#define BIT_WDG_EN BIT(2)
	87
	88	/* Definition of PMIC reset status register */
cc6b3431	89	#define HWRST_STATUS_SECURITY 0x02
ac177501 BW	90	#define HWRST_STATUS_RECOVERY 0x20
	91	#define HWRST_STATUS_NORMAL 0x40
	92	#define HWRST_STATUS_ALARM 0x50
	93	#define HWRST_STATUS_SLEEP 0x60
	94	#define HWRST_STATUS_FASTBOOT 0x30
	95	#define HWRST_STATUS_SPECIAL 0x70
	96	#define HWRST_STATUS_PANIC 0x80
	97	#define HWRST_STATUS_CFTREBOOT 0x90
	98	#define HWRST_STATUS_AUTODLOADER 0xa0
	99	#define HWRST_STATUS_IQMODE 0xb0
	100	#define HWRST_STATUS_SPRDISK 0xc0
	101
	102	/* Use default timeout 50 ms that converts to watchdog values */
	103	#define WDG_LOAD_VAL ((50 * 1000) / 32768)
	104	#define WDG_LOAD_MASK GENMASK(15, 0)
	105	#define WDG_UNLOCK_KEY 0xe551
	106
7e2903cb BW	107	struct sprd_adi {
	108	struct spi_controller *ctlr;
	109	struct device *dev;
	110	void __iomem *base;
	111	struct hwspinlock *hwlock;
	112	unsigned long slave_vbase;
	113	unsigned long slave_pbase;
ac177501	114	struct notifier_block restart_handler;
7e2903cb BW	115	};
	116
	117	static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
	118	{
	119	if (paddr < sadi->slave_pbase \|\| paddr >
	120	(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
	121	dev_err(sadi->dev,
	122	"slave physical address is incorrect, addr = 0x%x\n",
	123	paddr);
	124	return -EINVAL;
	125	}
	126
	127	return 0;
	128	}
	129
	130	static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
	131	{
	132	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
	133	}
	134
	135	static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
	136	{
	137	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	138	u32 sts;
	139
	140	do {
	141	sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
	142	if (sts & BIT_FIFO_EMPTY)
	143	break;
	144
	145	cpu_relax();
	146	} while (--timeout);
	147
	148	if (timeout == 0) {
	149	dev_err(sadi->dev, "drain write fifo timeout\n");
	150	return -EBUSY;
	151	}
	152
	153	return 0;
	154	}
	155
	156	static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
	157	{
	158	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
	159	}
	160
	161	static int sprd_adi_read(struct sprd_adi sadi, u32 reg_paddr, u32 read_val)
	162	{
	163	int read_timeout = ADI_READ_TIMEOUT;
a61aa683	164	unsigned long flags;
7e2903cb	165	u32 val, rd_addr;
a61aa683 BW	166	int ret;
	167
	168	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	169	ADI_HWSPINLOCK_TIMEOUT,
	170	&flags);
	171	if (ret) {
	172	dev_err(sadi->dev, "get the hw lock failed\n");
	173	return ret;
	174	}
7e2903cb BW	175
	176	/*
	177	* Set the physical register address need to read into RD_CMD register,
	178	* then ADI controller will start to transfer automatically.
	179	*/
	180	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
	181
	182	/*
	183	* Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	184	* simultaneously when writing read command to register, and the
	185	* BIT_RD_CMD_BUSY will be cleared after the read operation is
	186	* completed.
	187	*/
	188	do {
	189	val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
	190	if (!(val & BIT_RD_CMD_BUSY))
	191	break;
	192
	193	cpu_relax();
	194	} while (--read_timeout);
	195
	196	if (read_timeout == 0) {
	197	dev_err(sadi->dev, "ADI read timeout\n");
a61aa683 BW	198	ret = -EBUSY;
a61aa683 BW	199	goto out;
7e2903cb BW	200	}
	201
	202	/*
	203	* The return value includes data and read register address, from bit 0
	204	* to bit 15 are data, and from bit 16 to bit 30 are read register
	205	* address. Then we can check the returned register address to validate
	206	* data.
	207	*/
	208	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
	209
	210	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
	211	dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
	212	reg_paddr, val);
a61aa683 BW	213	ret = -EIO;
a61aa683 BW	214	goto out;
7e2903cb BW	215	}
	216
	217	*read_val = val & RD_VALUE_MASK;
a61aa683 BW	218
	219	out:
	220	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	221	return ret;
7e2903cb BW	222	}
7e2903cb BW	223
a61aa683	224	static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
7e2903cb	225	{
a61aa683	226	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
7e2903cb	227	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
a61aa683	228	unsigned long flags;
7e2903cb BW	229	int ret;
7e2903cb BW	230
a61aa683 BW	231	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	232	ADI_HWSPINLOCK_TIMEOUT,
	233	&flags);
	234	if (ret) {
	235	dev_err(sadi->dev, "get the hw lock failed\n");
	236	return ret;
	237	}
	238
7e2903cb BW	239	ret = sprd_adi_drain_fifo(sadi);
7e2903cb BW	240	if (ret < 0)
a61aa683	241	goto out;
7e2903cb BW	242
	243	/*
	244	* we should wait for write fifo is empty before writing data to PMIC
	245	* registers.
	246	*/
	247	do {
	248	if (!sprd_adi_fifo_is_full(sadi)) {
	249	writel_relaxed(val, (void __iomem *)reg);
	250	break;
	251	}
	252
	253	cpu_relax();
	254	} while (--timeout);
	255
	256	if (timeout == 0) {
	257	dev_err(sadi->dev, "write fifo is full\n");
a61aa683	258	ret = -EBUSY;
7e2903cb BW	259	}
7e2903cb BW	260
a61aa683 BW	261	out:
	262	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	263	return ret;
7e2903cb BW	264	}
	265
	266	static int sprd_adi_transfer_one(struct spi_controller *ctlr,
	267	struct spi_device *spi_dev,
	268	struct spi_transfer *t)
	269	{
	270	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
7e2903cb BW	271	u32 phy_reg, val;
	272	int ret;
	273
	274	if (t->rx_buf) {
	275	phy_reg = (u32 )t->rx_buf + sadi->slave_pbase;
	276
	277	ret = sprd_adi_check_paddr(sadi, phy_reg);
	278	if (ret)
	279	return ret;
	280
7e2903cb	281	ret = sprd_adi_read(sadi, phy_reg, &val);
7e2903cb BW	282	if (ret)
	283	return ret;
	284
	285	(u32 )t->rx_buf = val;
	286	} else if (t->tx_buf) {
	287	u32 p = (u32 )t->tx_buf;
	288
	289	/*
	290	* Get the physical register address need to write and convert
	291	* the physical address to virtual address. Since we need
	292	* virtual register address to write.
	293	*/
	294	phy_reg = *p++ + sadi->slave_pbase;
	295	ret = sprd_adi_check_paddr(sadi, phy_reg);
	296	if (ret)
	297	return ret;
	298
7e2903cb	299	val = *p;
a61aa683	300	ret = sprd_adi_write(sadi, phy_reg, val);
7e2903cb BW	301	if (ret)
	302	return ret;
	303	} else {
	304	dev_err(sadi->dev, "no buffer for transfer\n");
	305	return -EINVAL;
	306	}
	307
	308	return 0;
	309	}
	310
ac177501 BW	311	static int sprd_adi_restart_handler(struct notifier_block *this,
	312	unsigned long mode, void *cmd)
	313	{
	314	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
	315	restart_handler);
	316	u32 val, reboot_mode = 0;
	317
	318	if (!cmd)
	319	reboot_mode = HWRST_STATUS_NORMAL;
	320	else if (!strncmp(cmd, "recovery", 8))
	321	reboot_mode = HWRST_STATUS_RECOVERY;
	322	else if (!strncmp(cmd, "alarm", 5))
	323	reboot_mode = HWRST_STATUS_ALARM;
	324	else if (!strncmp(cmd, "fastsleep", 9))
	325	reboot_mode = HWRST_STATUS_SLEEP;
	326	else if (!strncmp(cmd, "bootloader", 10))
	327	reboot_mode = HWRST_STATUS_FASTBOOT;
	328	else if (!strncmp(cmd, "panic", 5))
	329	reboot_mode = HWRST_STATUS_PANIC;
	330	else if (!strncmp(cmd, "special", 7))
	331	reboot_mode = HWRST_STATUS_SPECIAL;
	332	else if (!strncmp(cmd, "cftreboot", 9))
	333	reboot_mode = HWRST_STATUS_CFTREBOOT;
	334	else if (!strncmp(cmd, "autodloader", 11))
	335	reboot_mode = HWRST_STATUS_AUTODLOADER;
	336	else if (!strncmp(cmd, "iqmode", 6))
	337	reboot_mode = HWRST_STATUS_IQMODE;
	338	else if (!strncmp(cmd, "sprdisk", 7))
	339	reboot_mode = HWRST_STATUS_SPRDISK;
cc6b3431 CW	340	else if (!strncmp(cmd, "tospanic", 8))
cc6b3431 CW	341	reboot_mode = HWRST_STATUS_SECURITY;
ac177501 BW	342	else
	343	reboot_mode = HWRST_STATUS_NORMAL;
	344
	345	/* Record the reboot mode */
	346	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	347	val \|= reboot_mode;
	348	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
	349
	350	/* Enable the interface clock of the watchdog */
	351	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	352	val \|= BIT_WDG_EN;
	353	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
	354
	355	/* Enable the work clock of the watchdog */
	356	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	357	val \|= BIT_WDG_EN;
	358	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
	359
	360	/* Unlock the watchdog */
	361	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
	362
	363	/* Load the watchdog timeout value, 50ms is always enough. */
	364	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
	365	WDG_LOAD_VAL & WDG_LOAD_MASK);
	366	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
	367
	368	/* Start the watchdog to reset system */
	369	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	370	val \|= BIT_WDG_RUN \| BIT_WDG_RST;
	371	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
	372
	373	mdelay(1000);
	374
	375	dev_emerg(sadi->dev, "Unable to restart system\n");
	376	return NOTIFY_DONE;
	377	}
	378
7e2903cb BW	379	static void sprd_adi_hw_init(struct sprd_adi *sadi)
	380	{
	381	struct device_node *np = sadi->dev->of_node;
	382	int i, size, chn_cnt;
	383	const __be32 *list;
	384	u32 tmp;
	385
7e2903cb BW	386	/* Set all channels as default priority */
	387	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	388	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
	389
	390	/* Set clock auto gate mode */
	391	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	392	tmp &= ~BIT_CLK_ALL_ON;
	393	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
	394
	395	/* Set hardware channels setting */
	396	list = of_get_property(np, "sprd,hw-channels", &size);
b0d6e097	397	if (!list \|\| !size) {
7e2903cb BW	398	dev_info(sadi->dev, "no hw channels setting in node\n");
	399	return;
	400	}
	401
	402	chn_cnt = size / 8;
	403	for (i = 0; i < chn_cnt; i++) {
	404	u32 value;
	405	u32 chn_id = be32_to_cpu(*list++);
	406	u32 chn_config = be32_to_cpu(*list++);
	407
	408	/* Channel 0 and 1 are software channels */
	409	if (chn_id < 2)
	410	continue;
	411
	412	writel_relaxed(chn_config, sadi->base +
	413	REG_ADI_CHN_ADDR(chn_id));
	414
54e2fc28	415	if (chn_id < 32) {
7e2903cb BW	416	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
	417	value \|= BIT(chn_id);
	418	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
	419	} else if (chn_id < ADI_HW_CHNS) {
	420	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
	421	value \|= BIT(chn_id - 32);
	422	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
	423	}
	424	}
	425	}
	426
	427	static int sprd_adi_probe(struct platform_device *pdev)
	428	{
	429	struct device_node *np = pdev->dev.of_node;
	430	struct spi_controller *ctlr;
	431	struct sprd_adi *sadi;
	432	struct resource *res;
	433	u32 num_chipselect;
	434	int ret;
	435
	436	if (!np) {
	437	dev_err(&pdev->dev, "can not find the adi bus node\n");
	438	return -ENODEV;
	439	}
	440
	441	pdev->id = of_alias_get_id(np, "spi");
	442	num_chipselect = of_get_child_count(np);
	443
	444	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	445	if (!ctlr)
	446	return -ENOMEM;
	447
	448	dev_set_drvdata(&pdev->dev, ctlr);
	449	sadi = spi_controller_get_devdata(ctlr);
	450
	451	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	452	sadi->base = devm_ioremap_resource(&pdev->dev, res);
04063a01 DC	453	if (IS_ERR(sadi->base)) {
04063a01 DC	454	ret = PTR_ERR(sadi->base);
7e2903cb BW	455	goto put_ctlr;
	456	}
	457
	458	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	459	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	460	sadi->ctlr = ctlr;
	461	sadi->dev = &pdev->dev;
d4942c11	462	ret = of_hwspin_lock_get_id_byname(np, "adi");
7e2903cb BW	463	if (ret < 0) {
	464	dev_err(&pdev->dev, "can not get the hardware spinlock\n");
	465	goto put_ctlr;
	466	}
	467
c8d04989	468	sadi->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
7e2903cb BW	469	if (!sadi->hwlock) {
	470	ret = -ENXIO;
	471	goto put_ctlr;
	472	}
	473
	474	sprd_adi_hw_init(sadi);
	475
	476	ctlr->dev.of_node = pdev->dev.of_node;
	477	ctlr->bus_num = pdev->id;
	478	ctlr->num_chipselect = num_chipselect;
	479	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	480	ctlr->bits_per_word_mask = 0;
	481	ctlr->transfer_one = sprd_adi_transfer_one;
	482
	483	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	484	if (ret) {
	485	dev_err(&pdev->dev, "failed to register SPI controller\n");
c8d04989	486	goto put_ctlr;
7e2903cb BW	487	}
7e2903cb BW	488
ac177501 BW	489	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	490	sadi->restart_handler.priority = 128;
	491	ret = register_restart_handler(&sadi->restart_handler);
	492	if (ret) {
	493	dev_err(&pdev->dev, "can not register restart handler\n");
c8d04989	494	goto put_ctlr;
ac177501 BW	495	}
ac177501 BW	496
7e2903cb BW	497	return 0;
7e2903cb BW	498
7e2903cb BW	499	put_ctlr:
	500	spi_controller_put(ctlr);
	501	return ret;
	502	}
	503
	504	static int sprd_adi_remove(struct platform_device *pdev)
	505	{
	506	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	507	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	508
ac177501	509	unregister_restart_handler(&sadi->restart_handler);
7e2903cb BW	510	return 0;
	511	}
	512
	513	static const struct of_device_id sprd_adi_of_match[] = {
	514	{
	515	.compatible = "sprd,sc9860-adi",
	516	},
	517	{ },
	518	};
	519	MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
	520
	521	static struct platform_driver sprd_adi_driver = {
	522	.driver = {
	523	.name = "sprd-adi",
7e2903cb BW	524	.of_match_table = sprd_adi_of_match,
	525	},
	526	.probe = sprd_adi_probe,
	527	.remove = sprd_adi_remove,
	528	};
	529	module_platform_driver(sprd_adi_driver);
	530
	531	MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
	532	MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
	533	MODULE_LICENSE("GPL v2");