[linux-2.6-block.git] / drivers / spi / spi-sprd-adi.c

/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>

/* Registers definitions for ADI controller */
#define REG_ADI_CTRL0			0x4
#define REG_ADI_CHN_PRIL		0x8
#define REG_ADI_CHN_PRIH		0xc
#define REG_ADI_INT_EN			0x10
#define REG_ADI_INT_RAW			0x14
#define REG_ADI_INT_MASK		0x18
#define REG_ADI_INT_CLR			0x1c
#define REG_ADI_GSSI_CFG0		0x20
#define REG_ADI_GSSI_CFG1		0x24
#define REG_ADI_RD_CMD			0x28
#define REG_ADI_RD_DATA			0x2c
#define REG_ADI_ARM_FIFO_STS		0x30
#define REG_ADI_STS			0x34
#define REG_ADI_EVT_FIFO_STS		0x38
#define REG_ADI_ARM_CMD_STS		0x3c
#define REG_ADI_CHN_EN			0x40
#define REG_ADI_CHN_ADDR(id)		(0x44 + (id - 2) * 4)
#define REG_ADI_CHN_EN1			0x20c

/* Bits definitions for register REG_ADI_GSSI_CFG0 */
#define BIT_CLK_ALL_ON			BIT(30)

/* Bits definitions for register REG_ADI_RD_DATA */
#define BIT_RD_CMD_BUSY			BIT(31)
#define RD_ADDR_SHIFT			16
#define RD_VALUE_MASK			GENMASK(15, 0)
#define RD_ADDR_MASK			GENMASK(30, 16)

/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
#define BIT_FIFO_FULL			BIT(11)
#define BIT_FIFO_EMPTY			BIT(10)

/*
 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
 * The slave devices address offset is always 0x8000 and size is 4K.
 */
#define ADI_SLAVE_ADDR_SIZE		SZ_4K
#define ADI_SLAVE_OFFSET		0x8000

/* Timeout (ms) for the trylock of hardware spinlocks */
#define ADI_HWSPINLOCK_TIMEOUT		5000
/*
 * ADI controller has 50 channels including 2 software channels
 * and 48 hardware channels.
 */
#define ADI_HW_CHNS			50

#define ADI_FIFO_DRAIN_TIMEOUT		1000
#define ADI_READ_TIMEOUT		2000
#define REG_ADDR_LOW_MASK		GENMASK(11, 0)

/* Registers definitions for PMIC watchdog controller */
#define REG_WDG_LOAD_LOW		0x80
#define REG_WDG_LOAD_HIGH		0x84
#define REG_WDG_CTRL			0x88
#define REG_WDG_LOCK			0xa0

/* Bits definitions for register REG_WDG_CTRL */
#define BIT_WDG_RUN			BIT(1)
#define BIT_WDG_RST			BIT(3)

/* Registers definitions for PMIC */
#define PMIC_RST_STATUS			0xee8
#define PMIC_MODULE_EN			0xc08
#define PMIC_CLK_EN			0xc18
#define BIT_WDG_EN			BIT(2)

/* Definition of PMIC reset status register */
#define HWRST_STATUS_SECURITY		0x02
#define HWRST_STATUS_RECOVERY		0x20
#define HWRST_STATUS_NORMAL		0x40
#define HWRST_STATUS_ALARM		0x50
#define HWRST_STATUS_SLEEP		0x60
#define HWRST_STATUS_FASTBOOT		0x30
#define HWRST_STATUS_SPECIAL		0x70
#define HWRST_STATUS_PANIC		0x80
#define HWRST_STATUS_CFTREBOOT		0x90
#define HWRST_STATUS_AUTODLOADER	0xa0
#define HWRST_STATUS_IQMODE		0xb0
#define HWRST_STATUS_SPRDISK		0xc0
#define HWRST_STATUS_FACTORYTEST	0xe0
#define HWRST_STATUS_WATCHDOG		0xf0

/* Use default timeout 50 ms that converts to watchdog values */
#define WDG_LOAD_VAL			((50 * 1000) / 32768)
#define WDG_LOAD_MASK			GENMASK(15, 0)
#define WDG_UNLOCK_KEY			0xe551

struct sprd_adi {
	struct spi_controller	*ctlr;
	struct device		*dev;
	void __iomem		*base;
	struct hwspinlock	*hwlock;
	unsigned long		slave_vbase;
	unsigned long		slave_pbase;
	struct notifier_block	restart_handler;
};

static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
{
	if (paddr < sadi->slave_pbase || paddr >
	    (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
		dev_err(sadi->dev,
			"slave physical address is incorrect, addr = 0x%x\n",
			paddr);
		return -EINVAL;
	}

	return 0;
}

static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
{
	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
}

static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
{
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	u32 sts;

	do {
		sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
		if (sts & BIT_FIFO_EMPTY)
			break;

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "drain write fifo timeout\n");
		return -EBUSY;
	}

	return 0;
}

static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
{
	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
}

static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
{
	int read_timeout = ADI_READ_TIMEOUT;
	unsigned long flags;
	u32 val, rd_addr;
	int ret = 0;

	if (sadi->hwlock) {
		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}
	}

	/*
	 * Set the physical register address need to read into RD_CMD register,
	 * then ADI controller will start to transfer automatically.
	 */
	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);

	/*
	 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	 * simultaneously when writing read command to register, and the
	 * BIT_RD_CMD_BUSY will be cleared after the read operation is
	 * completed.
	 */
	do {
		val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
		if (!(val & BIT_RD_CMD_BUSY))
			break;

		cpu_relax();
	} while (--read_timeout);

	if (read_timeout == 0) {
		dev_err(sadi->dev, "ADI read timeout\n");
		ret = -EBUSY;
		goto out;
	}

	/*
	 * The return value includes data and read register address, from bit 0
	 * to bit 15 are data, and from bit 16 to bit 30 are read register
	 * address. Then we can check the returned register address to validate
	 * data.
	 */
	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;

	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
		dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
			reg_paddr, val);
		ret = -EIO;
		goto out;
	}

	*read_val = val & RD_VALUE_MASK;

out:
	if (sadi->hwlock)
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
{
	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	unsigned long flags;
	int ret;

	if (sadi->hwlock) {
		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}
	}

	ret = sprd_adi_drain_fifo(sadi);
	if (ret < 0)
		goto out;

	/*
	 * we should wait for write fifo is empty before writing data to PMIC
	 * registers.
	 */
	do {
		if (!sprd_adi_fifo_is_full(sadi)) {
			writel_relaxed(val, (void __iomem *)reg);
			break;
		}

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "write fifo is full\n");
		ret = -EBUSY;
	}

out:
	if (sadi->hwlock)
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_transfer_one(struct spi_controller *ctlr,
				 struct spi_device *spi_dev,
				 struct spi_transfer *t)
{
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	u32 phy_reg, val;
	int ret;

	if (t->rx_buf) {
		phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;

		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		ret = sprd_adi_read(sadi, phy_reg, &val);
		if (ret)
			return ret;

		*(u32 *)t->rx_buf = val;
	} else if (t->tx_buf) {
		u32 *p = (u32 *)t->tx_buf;

		/*
		 * Get the physical register address need to write and convert
		 * the physical address to virtual address. Since we need
		 * virtual register address to write.
		 */
		phy_reg = *p++ + sadi->slave_pbase;
		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		val = *p;
		ret = sprd_adi_write(sadi, phy_reg, val);
		if (ret)
			return ret;
	} else {
		dev_err(sadi->dev, "no buffer for transfer\n");
		return -EINVAL;
	}

	return 0;
}

static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
{
#ifdef CONFIG_SPRD_WATCHDOG
	u32 val;

	/* Set default watchdog reboot mode */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	val |= HWRST_STATUS_WATCHDOG;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
#endif
}

static int sprd_adi_restart_handler(struct notifier_block *this,
				    unsigned long mode, void *cmd)
{
	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
					     restart_handler);
	u32 val, reboot_mode = 0;

	if (!cmd)
		reboot_mode = HWRST_STATUS_NORMAL;
	else if (!strncmp(cmd, "recovery", 8))
		reboot_mode = HWRST_STATUS_RECOVERY;
	else if (!strncmp(cmd, "alarm", 5))
		reboot_mode = HWRST_STATUS_ALARM;
	else if (!strncmp(cmd, "fastsleep", 9))
		reboot_mode = HWRST_STATUS_SLEEP;
	else if (!strncmp(cmd, "bootloader", 10))
		reboot_mode = HWRST_STATUS_FASTBOOT;
	else if (!strncmp(cmd, "panic", 5))
		reboot_mode = HWRST_STATUS_PANIC;
	else if (!strncmp(cmd, "special", 7))
		reboot_mode = HWRST_STATUS_SPECIAL;
	else if (!strncmp(cmd, "cftreboot", 9))
		reboot_mode = HWRST_STATUS_CFTREBOOT;
	else if (!strncmp(cmd, "autodloader", 11))
		reboot_mode = HWRST_STATUS_AUTODLOADER;
	else if (!strncmp(cmd, "iqmode", 6))
		reboot_mode = HWRST_STATUS_IQMODE;
	else if (!strncmp(cmd, "sprdisk", 7))
		reboot_mode = HWRST_STATUS_SPRDISK;
	else if (!strncmp(cmd, "tospanic", 8))
		reboot_mode = HWRST_STATUS_SECURITY;
	else if (!strncmp(cmd, "factorytest", 11))
		reboot_mode = HWRST_STATUS_FACTORYTEST;
	else
		reboot_mode = HWRST_STATUS_NORMAL;

	/* Record the reboot mode */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	val &= ~HWRST_STATUS_WATCHDOG;
	val |= reboot_mode;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);

	/* Enable the interface clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);

	/* Enable the work clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);

	/* Unlock the watchdog */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);

	/* Load the watchdog timeout value, 50ms is always enough. */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
		       WDG_LOAD_VAL & WDG_LOAD_MASK);
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);

	/* Start the watchdog to reset system */
	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	val |= BIT_WDG_RUN | BIT_WDG_RST;
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);

	mdelay(1000);

	dev_emerg(sadi->dev, "Unable to restart system\n");
	return NOTIFY_DONE;
}

static void sprd_adi_hw_init(struct sprd_adi *sadi)
{
	struct device_node *np = sadi->dev->of_node;
	int i, size, chn_cnt;
	const __be32 *list;
	u32 tmp;

	/* Set all channels as default priority */
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);

	/* Set clock auto gate mode */
	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	tmp &= ~BIT_CLK_ALL_ON;
	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);

	/* Set hardware channels setting */
	list = of_get_property(np, "sprd,hw-channels", &size);
	if (!list || !size) {
		dev_info(sadi->dev, "no hw channels setting in node\n");
		return;
	}

	chn_cnt = size / 8;
	for (i = 0; i < chn_cnt; i++) {
		u32 value;
		u32 chn_id = be32_to_cpu(*list++);
		u32 chn_config = be32_to_cpu(*list++);

		/* Channel 0 and 1 are software channels */
		if (chn_id < 2)
			continue;

		writel_relaxed(chn_config, sadi->base +
			       REG_ADI_CHN_ADDR(chn_id));

		if (chn_id < 32) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
			value |= BIT(chn_id);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
		} else if (chn_id < ADI_HW_CHNS) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
			value |= BIT(chn_id - 32);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
		}
	}
}

static int sprd_adi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_controller *ctlr;
	struct sprd_adi *sadi;
	struct resource *res;
	u32 num_chipselect;
	int ret;

	if (!np) {
		dev_err(&pdev->dev, "can not find the adi bus node\n");
		return -ENODEV;
	}

	pdev->id = of_alias_get_id(np, "spi");
	num_chipselect = of_get_child_count(np);

	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	if (!ctlr)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, ctlr);
	sadi = spi_controller_get_devdata(ctlr);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sadi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sadi->base)) {
		ret = PTR_ERR(sadi->base);
		goto put_ctlr;
	}

	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	sadi->ctlr = ctlr;
	sadi->dev = &pdev->dev;
	ret = of_hwspin_lock_get_id(np, 0);
	if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
		sadi->hwlock =
			devm_hwspin_lock_request_specific(&pdev->dev, ret);
		if (!sadi->hwlock) {
			ret = -ENXIO;
			goto put_ctlr;
		}
	} else {
		switch (ret) {
		case -ENOENT:
			dev_info(&pdev->dev, "no hardware spinlock supplied\n");
			break;
		default:
			dev_err(&pdev->dev,
				"failed to find hwlock id, %d\n", ret);
			/* fall-through */
		case -EPROBE_DEFER:
			goto put_ctlr;
		}
	}

	sprd_adi_hw_init(sadi);
	sprd_adi_set_wdt_rst_mode(sadi);

	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->bus_num = pdev->id;
	ctlr->num_chipselect = num_chipselect;
	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	ctlr->bits_per_word_mask = 0;
	ctlr->transfer_one = sprd_adi_transfer_one;

	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	if (ret) {
		dev_err(&pdev->dev, "failed to register SPI controller\n");
		goto put_ctlr;
	}

	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	sadi->restart_handler.priority = 128;
	ret = register_restart_handler(&sadi->restart_handler);
	if (ret) {
		dev_err(&pdev->dev, "can not register restart handler\n");
		goto put_ctlr;
	}

	return 0;

put_ctlr:
	spi_controller_put(ctlr);
	return ret;
}

static int sprd_adi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);

	unregister_restart_handler(&sadi->restart_handler);
	return 0;
}

static const struct of_device_id sprd_adi_of_match[] = {
	{
		.compatible = "sprd,sc9860-adi",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, sprd_adi_of_match);

static struct platform_driver sprd_adi_driver = {
	.driver = {
		.name = "sprd-adi",
		.of_match_table = sprd_adi_of_match,
	},
	.probe = sprd_adi_probe,
	.remove = sprd_adi_remove,
};
module_platform_driver(sprd_adi_driver);

MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7e2903cb BW	1	/*
	2	* Copyright (C) 2017 Spreadtrum Communications Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
ac177501	7	#include <linux/delay.h>
7e2903cb BW	8	#include <linux/hwspinlock.h>
	9	#include <linux/init.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/of_device.h>
	15	#include <linux/platform_device.h>
ac177501	16	#include <linux/reboot.h>
7e2903cb BW	17	#include <linux/spi/spi.h>
	18	#include <linux/sizes.h>
	19
	20	/* Registers definitions for ADI controller */
	21	#define REG_ADI_CTRL0 0x4
	22	#define REG_ADI_CHN_PRIL 0x8
	23	#define REG_ADI_CHN_PRIH 0xc
	24	#define REG_ADI_INT_EN 0x10
	25	#define REG_ADI_INT_RAW 0x14
	26	#define REG_ADI_INT_MASK 0x18
	27	#define REG_ADI_INT_CLR 0x1c
	28	#define REG_ADI_GSSI_CFG0 0x20
	29	#define REG_ADI_GSSI_CFG1 0x24
	30	#define REG_ADI_RD_CMD 0x28
	31	#define REG_ADI_RD_DATA 0x2c
	32	#define REG_ADI_ARM_FIFO_STS 0x30
	33	#define REG_ADI_STS 0x34
	34	#define REG_ADI_EVT_FIFO_STS 0x38
	35	#define REG_ADI_ARM_CMD_STS 0x3c
	36	#define REG_ADI_CHN_EN 0x40
	37	#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
	38	#define REG_ADI_CHN_EN1 0x20c
	39
	40	/* Bits definitions for register REG_ADI_GSSI_CFG0 */
	41	#define BIT_CLK_ALL_ON BIT(30)
	42
	43	/* Bits definitions for register REG_ADI_RD_DATA */
	44	#define BIT_RD_CMD_BUSY BIT(31)
	45	#define RD_ADDR_SHIFT 16
	46	#define RD_VALUE_MASK GENMASK(15, 0)
	47	#define RD_ADDR_MASK GENMASK(30, 16)
	48
	49	/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
	50	#define BIT_FIFO_FULL BIT(11)
	51	#define BIT_FIFO_EMPTY BIT(10)
	52
	53	/*
	54	* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
	55	* The slave devices address offset is always 0x8000 and size is 4K.
	56	*/
	57	#define ADI_SLAVE_ADDR_SIZE SZ_4K
	58	#define ADI_SLAVE_OFFSET 0x8000
	59
	60	/* Timeout (ms) for the trylock of hardware spinlocks */
	61	#define ADI_HWSPINLOCK_TIMEOUT 5000
	62	/*
	63	* ADI controller has 50 channels including 2 software channels
	64	* and 48 hardware channels.
	65	*/
	66	#define ADI_HW_CHNS 50
	67
	68	#define ADI_FIFO_DRAIN_TIMEOUT 1000
	69	#define ADI_READ_TIMEOUT 2000
	70	#define REG_ADDR_LOW_MASK GENMASK(11, 0)
	71
ac177501 BW	72	/* Registers definitions for PMIC watchdog controller */
	73	#define REG_WDG_LOAD_LOW 0x80
	74	#define REG_WDG_LOAD_HIGH 0x84
	75	#define REG_WDG_CTRL 0x88
	76	#define REG_WDG_LOCK 0xa0
	77
	78	/* Bits definitions for register REG_WDG_CTRL */
	79	#define BIT_WDG_RUN BIT(1)
	80	#define BIT_WDG_RST BIT(3)
	81
	82	/* Registers definitions for PMIC */
	83	#define PMIC_RST_STATUS 0xee8
	84	#define PMIC_MODULE_EN 0xc08
	85	#define PMIC_CLK_EN 0xc18
	86	#define BIT_WDG_EN BIT(2)
	87
	88	/* Definition of PMIC reset status register */
cc6b3431	89	#define HWRST_STATUS_SECURITY 0x02
ac177501 BW	90	#define HWRST_STATUS_RECOVERY 0x20
	91	#define HWRST_STATUS_NORMAL 0x40
	92	#define HWRST_STATUS_ALARM 0x50
	93	#define HWRST_STATUS_SLEEP 0x60
	94	#define HWRST_STATUS_FASTBOOT 0x30
	95	#define HWRST_STATUS_SPECIAL 0x70
	96	#define HWRST_STATUS_PANIC 0x80
	97	#define HWRST_STATUS_CFTREBOOT 0x90
	98	#define HWRST_STATUS_AUTODLOADER 0xa0
	99	#define HWRST_STATUS_IQMODE 0xb0
	100	#define HWRST_STATUS_SPRDISK 0xc0
9d9aa1cc	101	#define HWRST_STATUS_FACTORYTEST 0xe0
e6d722ca	102	#define HWRST_STATUS_WATCHDOG 0xf0
ac177501 BW	103
	104	/* Use default timeout 50 ms that converts to watchdog values */
	105	#define WDG_LOAD_VAL ((50 * 1000) / 32768)
	106	#define WDG_LOAD_MASK GENMASK(15, 0)
	107	#define WDG_UNLOCK_KEY 0xe551
	108
7e2903cb BW	109	struct sprd_adi {
	110	struct spi_controller *ctlr;
	111	struct device *dev;
	112	void __iomem *base;
	113	struct hwspinlock *hwlock;
	114	unsigned long slave_vbase;
	115	unsigned long slave_pbase;
ac177501	116	struct notifier_block restart_handler;
7e2903cb BW	117	};
	118
	119	static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
	120	{
	121	if (paddr < sadi->slave_pbase \|\| paddr >
	122	(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
	123	dev_err(sadi->dev,
	124	"slave physical address is incorrect, addr = 0x%x\n",
	125	paddr);
	126	return -EINVAL;
	127	}
	128
	129	return 0;
	130	}
	131
	132	static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
	133	{
	134	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
	135	}
	136
	137	static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
	138	{
	139	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	140	u32 sts;
	141
	142	do {
	143	sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
	144	if (sts & BIT_FIFO_EMPTY)
	145	break;
	146
	147	cpu_relax();
	148	} while (--timeout);
	149
	150	if (timeout == 0) {
	151	dev_err(sadi->dev, "drain write fifo timeout\n");
	152	return -EBUSY;
	153	}
	154
	155	return 0;
	156	}
	157
	158	static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
	159	{
	160	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
	161	}
	162
	163	static int sprd_adi_read(struct sprd_adi sadi, u32 reg_paddr, u32 read_val)
	164	{
	165	int read_timeout = ADI_READ_TIMEOUT;
a61aa683	166	unsigned long flags;
7e2903cb	167	u32 val, rd_addr;
f9adf61e BW	168	int ret = 0;
	169
	170	if (sadi->hwlock) {
	171	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	172	ADI_HWSPINLOCK_TIMEOUT,
	173	&flags);
	174	if (ret) {
	175	dev_err(sadi->dev, "get the hw lock failed\n");
	176	return ret;
	177	}
a61aa683	178	}
7e2903cb BW	179
	180	/*
	181	* Set the physical register address need to read into RD_CMD register,
	182	* then ADI controller will start to transfer automatically.
	183	*/
	184	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
	185
	186	/*
	187	* Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	188	* simultaneously when writing read command to register, and the
	189	* BIT_RD_CMD_BUSY will be cleared after the read operation is
	190	* completed.
	191	*/
	192	do {
	193	val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
	194	if (!(val & BIT_RD_CMD_BUSY))
	195	break;
	196
	197	cpu_relax();
	198	} while (--read_timeout);
	199
	200	if (read_timeout == 0) {
	201	dev_err(sadi->dev, "ADI read timeout\n");
a61aa683 BW	202	ret = -EBUSY;
a61aa683 BW	203	goto out;
7e2903cb BW	204	}
	205
	206	/*
	207	* The return value includes data and read register address, from bit 0
	208	* to bit 15 are data, and from bit 16 to bit 30 are read register
	209	* address. Then we can check the returned register address to validate
	210	* data.
	211	*/
	212	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
	213
	214	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
	215	dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
	216	reg_paddr, val);
a61aa683 BW	217	ret = -EIO;
a61aa683 BW	218	goto out;
7e2903cb BW	219	}
	220
	221	*read_val = val & RD_VALUE_MASK;
a61aa683 BW	222
a61aa683 BW	223	out:
f9adf61e BW	224	if (sadi->hwlock)
f9adf61e BW	225	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
a61aa683	226	return ret;
7e2903cb BW	227	}
7e2903cb BW	228
a61aa683	229	static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
7e2903cb	230	{
a61aa683	231	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
7e2903cb	232	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
a61aa683	233	unsigned long flags;
7e2903cb BW	234	int ret;
7e2903cb BW	235
f9adf61e BW	236	if (sadi->hwlock) {
	237	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	238	ADI_HWSPINLOCK_TIMEOUT,
	239	&flags);
	240	if (ret) {
	241	dev_err(sadi->dev, "get the hw lock failed\n");
	242	return ret;
	243	}
a61aa683 BW	244	}
a61aa683 BW	245
7e2903cb BW	246	ret = sprd_adi_drain_fifo(sadi);
7e2903cb BW	247	if (ret < 0)
a61aa683	248	goto out;
7e2903cb BW	249
	250	/*
	251	* we should wait for write fifo is empty before writing data to PMIC
	252	* registers.
	253	*/
	254	do {
	255	if (!sprd_adi_fifo_is_full(sadi)) {
	256	writel_relaxed(val, (void __iomem *)reg);
	257	break;
	258	}
	259
	260	cpu_relax();
	261	} while (--timeout);
	262
	263	if (timeout == 0) {
	264	dev_err(sadi->dev, "write fifo is full\n");
a61aa683	265	ret = -EBUSY;
7e2903cb BW	266	}
7e2903cb BW	267
a61aa683	268	out:
f9adf61e BW	269	if (sadi->hwlock)
f9adf61e BW	270	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
a61aa683	271	return ret;
7e2903cb BW	272	}
	273
	274	static int sprd_adi_transfer_one(struct spi_controller *ctlr,
	275	struct spi_device *spi_dev,
	276	struct spi_transfer *t)
	277	{
	278	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
7e2903cb BW	279	u32 phy_reg, val;
	280	int ret;
	281
	282	if (t->rx_buf) {
	283	phy_reg = (u32 )t->rx_buf + sadi->slave_pbase;
	284
	285	ret = sprd_adi_check_paddr(sadi, phy_reg);
	286	if (ret)
	287	return ret;
	288
7e2903cb	289	ret = sprd_adi_read(sadi, phy_reg, &val);
7e2903cb BW	290	if (ret)
	291	return ret;
	292
	293	(u32 )t->rx_buf = val;
	294	} else if (t->tx_buf) {
	295	u32 p = (u32 )t->tx_buf;
	296
	297	/*
	298	* Get the physical register address need to write and convert
	299	* the physical address to virtual address. Since we need
	300	* virtual register address to write.
	301	*/
	302	phy_reg = *p++ + sadi->slave_pbase;
	303	ret = sprd_adi_check_paddr(sadi, phy_reg);
	304	if (ret)
	305	return ret;
	306
7e2903cb	307	val = *p;
a61aa683	308	ret = sprd_adi_write(sadi, phy_reg, val);
7e2903cb BW	309	if (ret)
	310	return ret;
	311	} else {
	312	dev_err(sadi->dev, "no buffer for transfer\n");
	313	return -EINVAL;
	314	}
	315
	316	return 0;
	317	}
	318
e6d722ca SZ	319	static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
	320	{
	321	#ifdef CONFIG_SPRD_WATCHDOG
	322	u32 val;
	323
	324	/* Set default watchdog reboot mode */
	325	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	326	val \|= HWRST_STATUS_WATCHDOG;
	327	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
	328	#endif
	329	}
	330
ac177501 BW	331	static int sprd_adi_restart_handler(struct notifier_block *this,
	332	unsigned long mode, void *cmd)
	333	{
	334	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
	335	restart_handler);
	336	u32 val, reboot_mode = 0;
	337
	338	if (!cmd)
	339	reboot_mode = HWRST_STATUS_NORMAL;
	340	else if (!strncmp(cmd, "recovery", 8))
	341	reboot_mode = HWRST_STATUS_RECOVERY;
	342	else if (!strncmp(cmd, "alarm", 5))
	343	reboot_mode = HWRST_STATUS_ALARM;
	344	else if (!strncmp(cmd, "fastsleep", 9))
	345	reboot_mode = HWRST_STATUS_SLEEP;
	346	else if (!strncmp(cmd, "bootloader", 10))
	347	reboot_mode = HWRST_STATUS_FASTBOOT;
	348	else if (!strncmp(cmd, "panic", 5))
	349	reboot_mode = HWRST_STATUS_PANIC;
	350	else if (!strncmp(cmd, "special", 7))
	351	reboot_mode = HWRST_STATUS_SPECIAL;
	352	else if (!strncmp(cmd, "cftreboot", 9))
	353	reboot_mode = HWRST_STATUS_CFTREBOOT;
	354	else if (!strncmp(cmd, "autodloader", 11))
	355	reboot_mode = HWRST_STATUS_AUTODLOADER;
	356	else if (!strncmp(cmd, "iqmode", 6))
	357	reboot_mode = HWRST_STATUS_IQMODE;
	358	else if (!strncmp(cmd, "sprdisk", 7))
	359	reboot_mode = HWRST_STATUS_SPRDISK;
cc6b3431 CW	360	else if (!strncmp(cmd, "tospanic", 8))
cc6b3431 CW	361	reboot_mode = HWRST_STATUS_SECURITY;
9d9aa1cc SZ	362	else if (!strncmp(cmd, "factorytest", 11))
9d9aa1cc SZ	363	reboot_mode = HWRST_STATUS_FACTORYTEST;
ac177501 BW	364	else
	365	reboot_mode = HWRST_STATUS_NORMAL;
	366
	367	/* Record the reboot mode */
	368	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
e6d722ca	369	val &= ~HWRST_STATUS_WATCHDOG;
ac177501 BW	370	val \|= reboot_mode;
	371	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
	372
	373	/* Enable the interface clock of the watchdog */
	374	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	375	val \|= BIT_WDG_EN;
	376	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
	377
	378	/* Enable the work clock of the watchdog */
	379	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	380	val \|= BIT_WDG_EN;
	381	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
	382
	383	/* Unlock the watchdog */
	384	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
	385
	386	/* Load the watchdog timeout value, 50ms is always enough. */
	387	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
	388	WDG_LOAD_VAL & WDG_LOAD_MASK);
	389	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
	390
	391	/* Start the watchdog to reset system */
	392	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	393	val \|= BIT_WDG_RUN \| BIT_WDG_RST;
	394	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
	395
	396	mdelay(1000);
	397
	398	dev_emerg(sadi->dev, "Unable to restart system\n");
	399	return NOTIFY_DONE;
	400	}
	401
7e2903cb BW	402	static void sprd_adi_hw_init(struct sprd_adi *sadi)
	403	{
	404	struct device_node *np = sadi->dev->of_node;
	405	int i, size, chn_cnt;
	406	const __be32 *list;
	407	u32 tmp;
	408
7e2903cb BW	409	/* Set all channels as default priority */
	410	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	411	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
	412
	413	/* Set clock auto gate mode */
	414	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	415	tmp &= ~BIT_CLK_ALL_ON;
	416	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
	417
	418	/* Set hardware channels setting */
	419	list = of_get_property(np, "sprd,hw-channels", &size);
b0d6e097	420	if (!list \|\| !size) {
7e2903cb BW	421	dev_info(sadi->dev, "no hw channels setting in node\n");
	422	return;
	423	}
	424
	425	chn_cnt = size / 8;
	426	for (i = 0; i < chn_cnt; i++) {
	427	u32 value;
	428	u32 chn_id = be32_to_cpu(*list++);
	429	u32 chn_config = be32_to_cpu(*list++);
	430
	431	/* Channel 0 and 1 are software channels */
	432	if (chn_id < 2)
	433	continue;
	434
	435	writel_relaxed(chn_config, sadi->base +
	436	REG_ADI_CHN_ADDR(chn_id));
	437
54e2fc28	438	if (chn_id < 32) {
7e2903cb BW	439	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
	440	value \|= BIT(chn_id);
	441	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
	442	} else if (chn_id < ADI_HW_CHNS) {
	443	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
	444	value \|= BIT(chn_id - 32);
	445	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
	446	}
	447	}
	448	}
	449
	450	static int sprd_adi_probe(struct platform_device *pdev)
	451	{
	452	struct device_node *np = pdev->dev.of_node;
	453	struct spi_controller *ctlr;
	454	struct sprd_adi *sadi;
	455	struct resource *res;
	456	u32 num_chipselect;
	457	int ret;
	458
	459	if (!np) {
	460	dev_err(&pdev->dev, "can not find the adi bus node\n");
	461	return -ENODEV;
	462	}
	463
	464	pdev->id = of_alias_get_id(np, "spi");
	465	num_chipselect = of_get_child_count(np);
	466
	467	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	468	if (!ctlr)
	469	return -ENOMEM;
	470
	471	dev_set_drvdata(&pdev->dev, ctlr);
	472	sadi = spi_controller_get_devdata(ctlr);
	473
	474	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	475	sadi->base = devm_ioremap_resource(&pdev->dev, res);
04063a01 DC	476	if (IS_ERR(sadi->base)) {
04063a01 DC	477	ret = PTR_ERR(sadi->base);
7e2903cb BW	478	goto put_ctlr;
	479	}
	480
	481	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	482	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	483	sadi->ctlr = ctlr;
	484	sadi->dev = &pdev->dev;
f9adf61e BW	485	ret = of_hwspin_lock_get_id(np, 0);
	486	if (ret > 0 \|\| (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
	487	sadi->hwlock =
	488	devm_hwspin_lock_request_specific(&pdev->dev, ret);
	489	if (!sadi->hwlock) {
	490	ret = -ENXIO;
	491	goto put_ctlr;
	492	}
	493	} else {
	494	switch (ret) {
	495	case -ENOENT:
	496	dev_info(&pdev->dev, "no hardware spinlock supplied\n");
	497	break;
	498	default:
	499	dev_err(&pdev->dev,
	500	"failed to find hwlock id, %d\n", ret);
	501	/* fall-through */
	502	case -EPROBE_DEFER:
	503	goto put_ctlr;
	504	}
7e2903cb BW	505	}
	506
	507	sprd_adi_hw_init(sadi);
e6d722ca	508	sprd_adi_set_wdt_rst_mode(sadi);
7e2903cb BW	509
	510	ctlr->dev.of_node = pdev->dev.of_node;
	511	ctlr->bus_num = pdev->id;
	512	ctlr->num_chipselect = num_chipselect;
	513	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	514	ctlr->bits_per_word_mask = 0;
	515	ctlr->transfer_one = sprd_adi_transfer_one;
	516
	517	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	518	if (ret) {
	519	dev_err(&pdev->dev, "failed to register SPI controller\n");
c8d04989	520	goto put_ctlr;
7e2903cb BW	521	}
7e2903cb BW	522
ac177501 BW	523	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	524	sadi->restart_handler.priority = 128;
	525	ret = register_restart_handler(&sadi->restart_handler);
	526	if (ret) {
	527	dev_err(&pdev->dev, "can not register restart handler\n");
c8d04989	528	goto put_ctlr;
ac177501 BW	529	}
ac177501 BW	530
7e2903cb BW	531	return 0;
7e2903cb BW	532
7e2903cb BW	533	put_ctlr:
	534	spi_controller_put(ctlr);
	535	return ret;
	536	}
	537
	538	static int sprd_adi_remove(struct platform_device *pdev)
	539	{
	540	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	541	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	542
ac177501	543	unregister_restart_handler(&sadi->restart_handler);
7e2903cb BW	544	return 0;
	545	}
	546
	547	static const struct of_device_id sprd_adi_of_match[] = {
	548	{
	549	.compatible = "sprd,sc9860-adi",
	550	},
	551	{ },
	552	};
	553	MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
	554
	555	static struct platform_driver sprd_adi_driver = {
	556	.driver = {
	557	.name = "sprd-adi",
7e2903cb BW	558	.of_match_table = sprd_adi_of_match,
	559	},
	560	.probe = sprd_adi_probe,
	561	.remove = sprd_adi_remove,
	562	};
	563	module_platform_driver(sprd_adi_driver);
	564
	565	MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
	566	MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
	567	MODULE_LICENSE("GPL v2");