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spi/sirf: Depends on SIRF_DMA
[linux-2.6-block.git] / drivers / spi / spi-sirf.c
CommitLineData
1cc2df9d
ZS		 1/*
2 * SPI bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/of_gpio.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
de39f5fa
BS		 22#include <linux/dmaengine.h>
23#include <linux/dma-direction.h>
24#include <linux/dma-mapping.h>
25#include <linux/sirfsoc_dma.h>
1cc2df9d
ZS		 26
27#define DRIVER_NAME "sirfsoc_spi"
28
29#define SIRFSOC_SPI_CTRL 0x0000
30#define SIRFSOC_SPI_CMD 0x0004
31#define SIRFSOC_SPI_TX_RX_EN 0x0008
32#define SIRFSOC_SPI_INT_EN 0x000C
33#define SIRFSOC_SPI_INT_STATUS 0x0010
34#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
35#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
36#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
37#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
38#define SIRFSOC_SPI_TXFIFO_OP 0x0110
39#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
40#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
41#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
42#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
43#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
44#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
45#define SIRFSOC_SPI_RXFIFO_OP 0x0130
46#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
47#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
48#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
49
50/* SPI CTRL register defines */
51#define SIRFSOC_SPI_SLV_MODE BIT(16)
52#define SIRFSOC_SPI_CMD_MODE BIT(17)
53#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
54#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
55#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
56#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
57#define SIRFSOC_SPI_TRAN_MSB BIT(22)
58#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
59#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
60#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
62#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
63#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
64#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
65#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
66#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
67#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
68
69/* Interrupt Enable */
70#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
71#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
72#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
73#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
74#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
75#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
76#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
77#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
78#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
79#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
80#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
81
82#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
83
84/* Interrupt status */
85#define SIRFSOC_SPI_RX_DONE BIT(0)
86#define SIRFSOC_SPI_TX_DONE BIT(1)
87#define SIRFSOC_SPI_RX_OFLOW BIT(2)
88#define SIRFSOC_SPI_TX_UFLOW BIT(3)
89#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
90#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
91#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
92#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
93#define SIRFSOC_SPI_FRM_END BIT(10)
94
95/* TX RX enable */
96#define SIRFSOC_SPI_RX_EN BIT(0)
97#define SIRFSOC_SPI_TX_EN BIT(1)
98#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
99
100#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
101#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
102
103/* FIFO OPs */
104#define SIRFSOC_SPI_FIFO_RESET BIT(0)
105#define SIRFSOC_SPI_FIFO_START BIT(1)
106
107/* FIFO CTRL */
108#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
109#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
110#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
111
112/* FIFO Status */
113#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
114#define SIRFSOC_SPI_FIFO_FULL BIT(8)
115#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
116
117/* 256 bytes rx/tx FIFO */
118#define SIRFSOC_SPI_FIFO_SIZE 256
119#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
120
121#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
122#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
123#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
124#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
125
de39f5fa
BS		 126/*
127 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
128 * due to the limitation of dma controller
129 */
130
131#define ALIGNED(x) (!((u32)x & 0x3))
132#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
133 ALIGNED(x->len * sspi->word_width) && (x->len * sspi->word_width < \
134 2 * PAGE_SIZE))
135
1cc2df9d
ZS		 136struct sirfsoc_spi {
137 struct spi_bitbang bitbang;
de39f5fa
BS		 138 struct completion rx_done;
139 struct completion tx_done;
1cc2df9d
ZS		 140
141 void __iomem *base;
142 u32 ctrl_freq; /* SPI controller clock speed */
143 struct clk *clk;
1cc2df9d
ZS		 144
145 /* rx & tx bufs from the spi_transfer */
146 const void *tx;
147 void *rx;
148
149 /* place received word into rx buffer */
150 void (*rx_word) (struct sirfsoc_spi *);
151 /* get word from tx buffer for sending */
152 void (*tx_word) (struct sirfsoc_spi *);
153
154 /* number of words left to be tranmitted/received */
155 unsigned int left_tx_cnt;
156 unsigned int left_rx_cnt;
157
de39f5fa
BS		 158 /* rx & tx DMA channels */
159 struct dma_chan *rx_chan;
160 struct dma_chan *tx_chan;
161 dma_addr_t src_start;
162 dma_addr_t dst_start;
163 void *dummypage;
164 int word_width; /* in bytes */
165
1cc2df9d
ZS		 166 int chipselect[0];
167};
168
169static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
170{
171 u32 data;
172 u8 *rx = sspi->rx;
173
174 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
175
176 if (rx) {
177 *rx++ = (u8) data;
178 sspi->rx = rx;
179 }
180
181 sspi->left_rx_cnt--;
182}
183
184static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
185{
186 u32 data = 0;
187 const u8 *tx = sspi->tx;
188
189 if (tx) {
190 data = *tx++;
191 sspi->tx = tx;
192 }
193
194 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
195 sspi->left_tx_cnt--;
196}
197
198static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
199{
200 u32 data;
201 u16 *rx = sspi->rx;
202
203 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
204
205 if (rx) {
206 *rx++ = (u16) data;
207 sspi->rx = rx;
208 }
209
210 sspi->left_rx_cnt--;
211}
212
213static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
214{
215 u32 data = 0;
216 const u16 *tx = sspi->tx;
217
218 if (tx) {
219 data = *tx++;
220 sspi->tx = tx;
221 }
222
223 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
224 sspi->left_tx_cnt--;
225}
226
227static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
228{
229 u32 data;
230 u32 *rx = sspi->rx;
231
232 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
233
234 if (rx) {
235 *rx++ = (u32) data;
236 sspi->rx = rx;
237 }
238
239 sspi->left_rx_cnt--;
240
241}
242
243static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
244{
245 u32 data = 0;
246 const u32 *tx = sspi->tx;
247
248 if (tx) {
249 data = *tx++;
250 sspi->tx = tx;
251 }
252
253 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
254 sspi->left_tx_cnt--;
255}
256
1cc2df9d
ZS		 257static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
258{
259 struct sirfsoc_spi *sspi = dev_id;
260 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
261
262 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
263
264 /* Error Conditions */
265 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
266 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
de39f5fa 267 complete(&sspi->rx_done);
1cc2df9d
ZS		 268 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
269 }
270
237ce466
QL		 271 if (spi_stat & (SIRFSOC_SPI_FRM_END
272 | SIRFSOC_SPI_RXFIFO_THD_REACH))
1cc2df9d
ZS		 273 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
274 & SIRFSOC_SPI_FIFO_EMPTY)) &&
275 sspi->left_rx_cnt)
276 sspi->rx_word(sspi);
277
237ce466
QL		 278 if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
279 | SIRFSOC_SPI_TXFIFO_THD_REACH))
280 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
281 & SIRFSOC_SPI_FIFO_FULL)) &&
282 sspi->left_tx_cnt)
283 sspi->tx_word(sspi);
1cc2df9d 284
237ce466
QL		 285 /* Received all words */
286 if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
de39f5fa 287 complete(&sspi->rx_done);
237ce466
QL		 288 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
289 }
1cc2df9d
ZS		 290 return IRQ_HANDLED;
291}
292
de39f5fa
BS		 293static void spi_sirfsoc_dma_fini_callback(void *data)
294{
295 struct completion *dma_complete = data;
296
297 complete(dma_complete);
298}
299
1cc2df9d
ZS		 300static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
301{
302 struct sirfsoc_spi *sspi;
303 int timeout = t->len * 10;
304 sspi = spi_master_get_devdata(spi->master);
305
de39f5fa
BS		 306 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
307 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
1cc2df9d 308 sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
de39f5fa
BS		 309 INIT_COMPLETION(sspi->rx_done);
310 INIT_COMPLETION(sspi->tx_done);
1cc2df9d
ZS		 311
312 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
313
314 if (t->len == 1) {
315 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
316 SIRFSOC_SPI_ENA_AUTO_CLR,
317 sspi->base + SIRFSOC_SPI_CTRL);
318 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
319 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
320 } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
321 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
322 SIRFSOC_SPI_MUL_DAT_MODE |
323 SIRFSOC_SPI_ENA_AUTO_CLR,
324 sspi->base + SIRFSOC_SPI_CTRL);
325 writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
326 writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
327 } else {
328 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
329 sspi->base + SIRFSOC_SPI_CTRL);
330 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
331 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
332 }
333
334 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
335 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
336 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
337 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
338
de39f5fa
BS		 339 if (IS_DMA_VALID(t)) {
340 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
341 unsigned int size = t->len * sspi->word_width;
342
343 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE);
344 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
345 sspi->dst_start, size, DMA_DEV_TO_MEM,
346 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
347 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
348 rx_desc->callback_param = &sspi->rx_done;
349
350 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE);
351 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
352 sspi->src_start, size, DMA_MEM_TO_DEV,
353 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
354 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
355 tx_desc->callback_param = &sspi->tx_done;
356
357 dmaengine_submit(tx_desc);
358 dmaengine_submit(rx_desc);
359 dma_async_issue_pending(sspi->tx_chan);
360 dma_async_issue_pending(sspi->rx_chan);
361 } else {
362 /* Send the first word to trigger the whole tx/rx process */
363 sspi->tx_word(sspi);
364
365 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
366 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
367 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
368 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
369 }
1cc2df9d 370
1cc2df9d
ZS		 371 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
372
de39f5fa
BS		 373 if (!IS_DMA_VALID(t)) { /* for PIO */
374 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
375 dev_err(&spi->dev, "transfer timeout\n");
376 } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
1cc2df9d 377 dev_err(&spi->dev, "transfer timeout\n");
de39f5fa
BS		 378 dmaengine_terminate_all(sspi->rx_chan);
379 } else
380 sspi->left_rx_cnt = 0;
381
382 /*
383 * we only wait tx-done event if transferring by DMA. for PIO,
384 * we get rx data by writing tx data, so if rx is done, tx has
385 * done earlier
386 */
387 if (IS_DMA_VALID(t)) {
388 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
389 dev_err(&spi->dev, "transfer timeout\n");
390 dmaengine_terminate_all(sspi->tx_chan);
391 }
392 }
393
394 if (IS_DMA_VALID(t)) {
395 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
396 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
397 }
1cc2df9d
ZS		 398
399 /* TX, RX FIFO stop */
400 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
401 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
402 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
403 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
404
405 return t->len - sspi->left_rx_cnt;
406}
407
408static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
409{
410 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
411
412 if (sspi->chipselect[spi->chip_select] == 0) {
413 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
1cc2df9d
ZS		 414 switch (value) {
415 case BITBANG_CS_ACTIVE:
416 if (spi->mode & SPI_CS_HIGH)
417 regval |= SIRFSOC_SPI_CS_IO_OUT;
418 else
419 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
420 break;
421 case BITBANG_CS_INACTIVE:
422 if (spi->mode & SPI_CS_HIGH)
423 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
424 else
425 regval |= SIRFSOC_SPI_CS_IO_OUT;
426 break;
427 }
428 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
429 } else {
430 int gpio = sspi->chipselect[spi->chip_select];
431 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
432 }
433}
434
435static int
436spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
437{
438 struct sirfsoc_spi *sspi;
439 u8 bits_per_word = 0;
440 int hz = 0;
441 u32 regval;
442 u32 txfifo_ctrl, rxfifo_ctrl;
443 u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
444
445 sspi = spi_master_get_devdata(spi->master);
446
766ed704 447 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
1cc2df9d
ZS		 448 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
449
1cc2df9d 450 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
1cc2df9d
ZS		 451 if (regval > 0xFFFF || regval < 0) {
452 dev_err(&spi->dev, "Speed %d not supported\n", hz);
453 return -EINVAL;
454 }
455
456 switch (bits_per_word) {
457 case 8:
458 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
459 sspi->rx_word = spi_sirfsoc_rx_word_u8;
460 sspi->tx_word = spi_sirfsoc_tx_word_u8;
461 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
462 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
463 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
464 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
de39f5fa 465 sspi->word_width = 1;
1cc2df9d
ZS		 466 break;
467 case 12:
468 case 16:
469 regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
470 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
471 sspi->rx_word = spi_sirfsoc_rx_word_u16;
472 sspi->tx_word = spi_sirfsoc_tx_word_u16;
473 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
474 SIRFSOC_SPI_FIFO_WIDTH_WORD;
475 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
476 SIRFSOC_SPI_FIFO_WIDTH_WORD;
de39f5fa 477 sspi->word_width = 2;
1cc2df9d
ZS		 478 break;
479 case 32:
480 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
481 sspi->rx_word = spi_sirfsoc_rx_word_u32;
482 sspi->tx_word = spi_sirfsoc_tx_word_u32;
483 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
484 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
485 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
486 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
de39f5fa 487 sspi->word_width = 4;
1cc2df9d 488 break;
804ae438
AB		 489 default:
490 BUG();
1cc2df9d
ZS		 491 }
492
493 if (!(spi->mode & SPI_CS_HIGH))
494 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
495 if (!(spi->mode & SPI_LSB_FIRST))
496 regval |= SIRFSOC_SPI_TRAN_MSB;
497 if (spi->mode & SPI_CPOL)
498 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
499
500 /*
501 * Data should be driven at least 1/2 cycle before the fetch edge to make
502 * sure that data gets stable at the fetch edge.
503 */
504 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
505 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
506 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
507 else
508 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
509
510 writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
511 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
512 SIRFSOC_SPI_FIFO_HC(2),
513 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
514 writel(SIRFSOC_SPI_FIFO_SC(2) |
515 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
516 SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
517 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
518 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
519 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
520
521 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
de39f5fa
BS		 522
523 if (IS_DMA_VALID(t)) {
524 /* Enable DMA mode for RX, TX */
525 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
526 writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
527 } else {
528 /* Enable IO mode for RX, TX */
529 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
530 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
531 }
532
1cc2df9d
ZS		 533 return 0;
534}
535
536static int spi_sirfsoc_setup(struct spi_device *spi)
537{
538 struct sirfsoc_spi *sspi;
539
540 if (!spi->max_speed_hz)
541 return -EINVAL;
542
543 sspi = spi_master_get_devdata(spi->master);
544
545 if (!spi->bits_per_word)
546 spi->bits_per_word = 8;
547
548 return spi_sirfsoc_setup_transfer(spi, NULL);
549}
550
fd4a319b 551static int spi_sirfsoc_probe(struct platform_device *pdev)
1cc2df9d
ZS		 552{
553 struct sirfsoc_spi *sspi;
554 struct spi_master *master;
555 struct resource *mem_res;
556 int num_cs, cs_gpio, irq;
de39f5fa
BS		 557 u32 rx_dma_ch, tx_dma_ch;
558 dma_cap_mask_t dma_cap_mask;
1cc2df9d
ZS		 559 int i;
560 int ret;
561
562 ret = of_property_read_u32(pdev->dev.of_node,
563 "sirf,spi-num-chipselects", &num_cs);
564 if (ret < 0) {
565 dev_err(&pdev->dev, "Unable to get chip select number\n");
566 goto err_cs;
567 }
568
de39f5fa
BS		 569 ret = of_property_read_u32(pdev->dev.of_node,
570 "sirf,spi-dma-rx-channel", &rx_dma_ch);
571 if (ret < 0) {
572 dev_err(&pdev->dev, "Unable to get rx dma channel\n");
573 goto err_cs;
574 }
575
576 ret = of_property_read_u32(pdev->dev.of_node,
577 "sirf,spi-dma-tx-channel", &tx_dma_ch);
578 if (ret < 0) {
579 dev_err(&pdev->dev, "Unable to get tx dma channel\n");
580 goto err_cs;
581 }
582
1cc2df9d
ZS		 583 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
584 if (!master) {
585 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
586 return -ENOMEM;
587 }
588 platform_set_drvdata(pdev, master);
589 sspi = spi_master_get_devdata(master);
590
591 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
592 if (!mem_res) {
593 dev_err(&pdev->dev, "Unable to get IO resource\n");
594 ret = -ENODEV;
595 goto free_master;
596 }
597 master->num_chipselect = num_cs;
598
599 for (i = 0; i < master->num_chipselect; i++) {
600 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
601 if (cs_gpio < 0) {
602 dev_err(&pdev->dev, "can't get cs gpio from DT\n");
603 ret = -ENODEV;
604 goto free_master;
605 }
606
607 sspi->chipselect[i] = cs_gpio;
608 if (cs_gpio == 0)
609 continue; /* use cs from spi controller */
610
611 ret = gpio_request(cs_gpio, DRIVER_NAME);
612 if (ret) {
613 while (i > 0) {
614 i--;
615 if (sspi->chipselect[i] > 0)
616 gpio_free(sspi->chipselect[i]);
617 }
618 dev_err(&pdev->dev, "fail to request cs gpios\n");
619 goto free_master;
620 }
621 }
622
b0ee5605
TR		 623 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
624 if (IS_ERR(sspi->base)) {
625 ret = PTR_ERR(sspi->base);
1cc2df9d
ZS		 626 goto free_master;
627 }
628
629 irq = platform_get_irq(pdev, 0);
630 if (irq < 0) {
631 ret = -ENXIO;
632 goto free_master;
633 }
634 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
635 DRIVER_NAME, sspi);
636 if (ret)
637 goto free_master;
638
639 sspi->bitbang.master = spi_master_get(master);
640 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
641 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
642 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
643 sspi->bitbang.master->setup = spi_sirfsoc_setup;
644 master->bus_num = pdev->id;
94b1f0df 645 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
24778be2
SW		 646 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
647 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
1cc2df9d
ZS		 648 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
649
de39f5fa
BS		 650 /* request DMA channels */
651 dma_cap_zero(dma_cap_mask);
652 dma_cap_set(DMA_INTERLEAVE, dma_cap_mask);
653
654 sspi->rx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
655 (void *)rx_dma_ch);
656 if (!sspi->rx_chan) {
657 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
658 goto free_master;
659 }
660 sspi->tx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
661 (void *)tx_dma_ch);
662 if (!sspi->tx_chan) {
663 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
664 goto free_rx_dma;
665 }
666
1cc2df9d
ZS		 667 sspi->clk = clk_get(&pdev->dev, NULL);
668 if (IS_ERR(sspi->clk)) {
de39f5fa
BS		 669 ret = PTR_ERR(sspi->clk);
670 goto free_tx_dma;
1cc2df9d 671 }
e5118cd2 672 clk_prepare_enable(sspi->clk);
1cc2df9d
ZS		 673 sspi->ctrl_freq = clk_get_rate(sspi->clk);
674
de39f5fa
BS		 675 init_completion(&sspi->rx_done);
676 init_completion(&sspi->tx_done);
1cc2df9d 677
1cc2df9d
ZS		 678 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
679 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
680 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
681 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
682 /* We are not using dummy delay between command and data */
683 writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
684
de39f5fa
BS		 685 sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
686 if (!sspi->dummypage)
687 goto free_clk;
688
1cc2df9d
ZS		 689 ret = spi_bitbang_start(&sspi->bitbang);
690 if (ret)
de39f5fa 691 goto free_dummypage;
1cc2df9d
ZS		 692
693 dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
694
695 return 0;
de39f5fa
BS		 696free_dummypage:
697 kfree(sspi->dummypage);
1cc2df9d 698free_clk:
e5118cd2 699 clk_disable_unprepare(sspi->clk);
1cc2df9d 700 clk_put(sspi->clk);
de39f5fa
BS		 701free_tx_dma:
702 dma_release_channel(sspi->tx_chan);
703free_rx_dma:
704 dma_release_channel(sspi->rx_chan);
1cc2df9d
ZS		 705free_master:
706 spi_master_put(master);
707err_cs:
708 return ret;
709}
710
fd4a319b 711static int spi_sirfsoc_remove(struct platform_device *pdev)
1cc2df9d
ZS		 712{
713 struct spi_master *master;
714 struct sirfsoc_spi *sspi;
715 int i;
716
717 master = platform_get_drvdata(pdev);
718 sspi = spi_master_get_devdata(master);
719
720 spi_bitbang_stop(&sspi->bitbang);
721 for (i = 0; i < master->num_chipselect; i++) {
722 if (sspi->chipselect[i] > 0)
723 gpio_free(sspi->chipselect[i]);
724 }
de39f5fa 725 kfree(sspi->dummypage);
e5118cd2 726 clk_disable_unprepare(sspi->clk);
1cc2df9d 727 clk_put(sspi->clk);
de39f5fa
BS		 728 dma_release_channel(sspi->rx_chan);
729 dma_release_channel(sspi->tx_chan);
1cc2df9d
ZS		 730 spi_master_put(master);
731 return 0;
732}
733
734#ifdef CONFIG_PM
735static int spi_sirfsoc_suspend(struct device *dev)
736{
737 struct platform_device *pdev = to_platform_device(dev);
738 struct spi_master *master = platform_get_drvdata(pdev);
739 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
740
741 clk_disable(sspi->clk);
742 return 0;
743}
744
745static int spi_sirfsoc_resume(struct device *dev)
746{
747 struct platform_device *pdev = to_platform_device(dev);
748 struct spi_master *master = platform_get_drvdata(pdev);
749 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
750
751 clk_enable(sspi->clk);
752 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
753 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
754 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
755 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
756
757 return 0;
758}
759
760static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
761 .suspend = spi_sirfsoc_suspend,
762 .resume = spi_sirfsoc_resume,
763};
764#endif
765
766static const struct of_device_id spi_sirfsoc_of_match[] = {
767 { .compatible = "sirf,prima2-spi", },
f3b8a8ec 768 { .compatible = "sirf,marco-spi", },
1cc2df9d
ZS		 769 {}
770};
3af4ed70 771MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
1cc2df9d
ZS		 772
773static struct platform_driver spi_sirfsoc_driver = {
774 .driver = {
775 .name = DRIVER_NAME,
776 .owner = THIS_MODULE,
777#ifdef CONFIG_PM
778 .pm = &spi_sirfsoc_pm_ops,
779#endif
780 .of_match_table = spi_sirfsoc_of_match,
781 },
782 .probe = spi_sirfsoc_probe,
fd4a319b 783 .remove = spi_sirfsoc_remove,
1cc2df9d
ZS		 784};
785module_platform_driver(spi_sirfsoc_driver);
786
787MODULE_DESCRIPTION("SiRF SoC SPI master driver");
788MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
789 "Barry Song <Baohua.Song@csr.com>");
790MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)