[linux-2.6-block.git] / drivers / spi / spi-sh.c

// SPDX-License-Identifier: GPL-2.0
/*
 * SH SPI bus driver
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 *
 * Based on pxa2xx_spi.c:
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>

#define SPI_SH_TBR		0x00
#define SPI_SH_RBR		0x00
#define SPI_SH_CR1		0x08
#define SPI_SH_CR2		0x10
#define SPI_SH_CR3		0x18
#define SPI_SH_CR4		0x20
#define SPI_SH_CR5		0x28

/* CR1 */
#define SPI_SH_TBE		0x80
#define SPI_SH_TBF		0x40
#define SPI_SH_RBE		0x20
#define SPI_SH_RBF		0x10
#define SPI_SH_PFONRD		0x08
#define SPI_SH_SSDB		0x04
#define SPI_SH_SSD		0x02
#define SPI_SH_SSA		0x01

/* CR2 */
#define SPI_SH_RSTF		0x80
#define SPI_SH_LOOPBK		0x40
#define SPI_SH_CPOL		0x20
#define SPI_SH_CPHA		0x10
#define SPI_SH_L1M0		0x08

/* CR3 */
#define SPI_SH_MAX_BYTE		0xFF

/* CR4 */
#define SPI_SH_TBEI		0x80
#define SPI_SH_TBFI		0x40
#define SPI_SH_RBEI		0x20
#define SPI_SH_RBFI		0x10
#define SPI_SH_WPABRT		0x04
#define SPI_SH_SSS		0x01

/* CR8 */
#define SPI_SH_P1L0		0x80
#define SPI_SH_PP1L0		0x40
#define SPI_SH_MUXI		0x20
#define SPI_SH_MUXIRQ		0x10

#define SPI_SH_FIFO_SIZE	32
#define SPI_SH_SEND_TIMEOUT	(3 * HZ)
#define SPI_SH_RECEIVE_TIMEOUT	(HZ >> 3)

#undef DEBUG

struct spi_sh_data {
	void __iomem *addr;
	int irq;
	struct spi_controller *host;
	unsigned long cr1;
	wait_queue_head_t wait;
	int width;
};

static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
			     unsigned long offset)
{
	if (ss->width == 8)
		iowrite8(data, ss->addr + (offset >> 2));
	else if (ss->width == 32)
		iowrite32(data, ss->addr + offset);
}

static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
{
	if (ss->width == 8)
		return ioread8(ss->addr + (offset >> 2));
	else if (ss->width == 32)
		return ioread32(ss->addr + offset);
	else
		return 0;
}

static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
				unsigned long offset)
{
	unsigned long tmp;

	tmp = spi_sh_read(ss, offset);
	tmp |= val;
	spi_sh_write(ss, tmp, offset);
}

static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
				unsigned long offset)
{
	unsigned long tmp;

	tmp = spi_sh_read(ss, offset);
	tmp &= ~val;
	spi_sh_write(ss, tmp, offset);
}

static void clear_fifo(struct spi_sh_data *ss)
{
	spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
	spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
}

static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
{
	int timeout = 100000;

	while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
		udelay(10);
		if (timeout-- < 0)
			return -ETIMEDOUT;
	}
	return 0;
}

static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
{
	int timeout = 100000;

	while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
		udelay(10);
		if (timeout-- < 0)
			return -ETIMEDOUT;
	}
	return 0;
}

static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
			struct spi_transfer *t)
{
	int i, retval = 0;
	int remain = t->len;
	int cur_len;
	unsigned char *data;
	long ret;

	if (t->len)
		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);

	data = (unsigned char *)t->tx_buf;
	while (remain > 0) {
		cur_len = min(SPI_SH_FIFO_SIZE, remain);
		for (i = 0; i < cur_len &&
				!(spi_sh_read(ss, SPI_SH_CR4) &
							SPI_SH_WPABRT) &&
				!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
				i++)
			spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);

		if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
			/* Abort SPI operation */
			spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
			retval = -EIO;
			break;
		}

		cur_len = i;

		remain -= cur_len;
		data += cur_len;

		if (remain > 0) {
			ss->cr1 &= ~SPI_SH_TBE;
			spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
			ret = wait_event_interruptible_timeout(ss->wait,
						 ss->cr1 & SPI_SH_TBE,
						 SPI_SH_SEND_TIMEOUT);
			if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
				printk(KERN_ERR "%s: timeout\n", __func__);
				return -ETIMEDOUT;
			}
		}
	}

	if (list_is_last(&t->transfer_list, &mesg->transfers)) {
		spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
		spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);

		ss->cr1 &= ~SPI_SH_TBE;
		spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
		ret = wait_event_interruptible_timeout(ss->wait,
					 ss->cr1 & SPI_SH_TBE,
					 SPI_SH_SEND_TIMEOUT);
		if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
			printk(KERN_ERR "%s: timeout\n", __func__);
			return -ETIMEDOUT;
		}
	}

	return retval;
}

static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
			  struct spi_transfer *t)
{
	int i;
	int remain = t->len;
	int cur_len;
	unsigned char *data;
	long ret;

	if (t->len > SPI_SH_MAX_BYTE)
		spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
	else
		spi_sh_write(ss, t->len, SPI_SH_CR3);

	spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);

	spi_sh_wait_write_buffer_empty(ss);

	data = (unsigned char *)t->rx_buf;
	while (remain > 0) {
		if (remain >= SPI_SH_FIFO_SIZE) {
			ss->cr1 &= ~SPI_SH_RBF;
			spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
			ret = wait_event_interruptible_timeout(ss->wait,
						 ss->cr1 & SPI_SH_RBF,
						 SPI_SH_RECEIVE_TIMEOUT);
			if (ret == 0 &&
			    spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
				printk(KERN_ERR "%s: timeout\n", __func__);
				return -ETIMEDOUT;
			}
		}

		cur_len = min(SPI_SH_FIFO_SIZE, remain);
		for (i = 0; i < cur_len; i++) {
			if (spi_sh_wait_receive_buffer(ss))
				break;
			data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
		}

		remain -= cur_len;
		data += cur_len;
	}

	/* deassert CS when SPI is receiving. */
	if (t->len > SPI_SH_MAX_BYTE) {
		clear_fifo(ss);
		spi_sh_write(ss, 1, SPI_SH_CR3);
	} else {
		spi_sh_write(ss, 0, SPI_SH_CR3);
	}

	return 0;
}

static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
					struct spi_message *mesg)
{
	struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
	struct spi_transfer *t;
	int ret;

	pr_debug("%s: enter\n", __func__);

	spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);

	list_for_each_entry(t, &mesg->transfers, transfer_list) {
		pr_debug("tx_buf = %p, rx_buf = %p\n",
			 t->tx_buf, t->rx_buf);
		pr_debug("len = %d, delay.value = %d\n",
			 t->len, t->delay.value);

		if (t->tx_buf) {
			ret = spi_sh_send(ss, mesg, t);
			if (ret < 0)
				goto error;
		}
		if (t->rx_buf) {
			ret = spi_sh_receive(ss, mesg, t);
			if (ret < 0)
				goto error;
		}
		mesg->actual_length += t->len;
	}

	mesg->status = 0;
	spi_finalize_current_message(ctlr);

	clear_fifo(ss);
	spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
	udelay(100);

	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
			 SPI_SH_CR1);

	clear_fifo(ss);

	return 0;

 error:
	mesg->status = ret;
	spi_finalize_current_message(ctlr);
	if (mesg->complete)
		mesg->complete(mesg->context);

	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
			 SPI_SH_CR1);
	clear_fifo(ss);

	return ret;
}

static int spi_sh_setup(struct spi_device *spi)
{
	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);

	pr_debug("%s: enter\n", __func__);

	spi_sh_write(ss, 0xfe, SPI_SH_CR1);	/* SPI sycle stop */
	spi_sh_write(ss, 0x00, SPI_SH_CR1);	/* CR1 init */
	spi_sh_write(ss, 0x00, SPI_SH_CR3);	/* CR3 init */

	clear_fifo(ss);

	/* 1/8 clock */
	spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
	udelay(10);

	return 0;
}

static void spi_sh_cleanup(struct spi_device *spi)
{
	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);

	pr_debug("%s: enter\n", __func__);

	spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
			 SPI_SH_CR1);
}

static irqreturn_t spi_sh_irq(int irq, void *_ss)
{
	struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
	unsigned long cr1;

	cr1 = spi_sh_read(ss, SPI_SH_CR1);
	if (cr1 & SPI_SH_TBE)
		ss->cr1 |= SPI_SH_TBE;
	if (cr1 & SPI_SH_TBF)
		ss->cr1 |= SPI_SH_TBF;
	if (cr1 & SPI_SH_RBE)
		ss->cr1 |= SPI_SH_RBE;
	if (cr1 & SPI_SH_RBF)
		ss->cr1 |= SPI_SH_RBF;

	if (ss->cr1) {
		spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
		wake_up(&ss->wait);
	}

	return IRQ_HANDLED;
}

static void spi_sh_remove(struct platform_device *pdev)
{
	struct spi_sh_data *ss = platform_get_drvdata(pdev);

	spi_unregister_controller(ss->host);
	free_irq(ss->irq, ss);
}

static int spi_sh_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct spi_controller *host;
	struct spi_sh_data *ss;
	int ret, irq;

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(res == NULL)) {
		dev_err(&pdev->dev, "invalid resource\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	host = devm_spi_alloc_host(&pdev->dev, sizeof(struct spi_sh_data));
	if (host == NULL) {
		dev_err(&pdev->dev, "devm_spi_alloc_host error.\n");
		return -ENOMEM;
	}

	ss = spi_controller_get_devdata(host);
	platform_set_drvdata(pdev, ss);

	switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
	case IORESOURCE_MEM_8BIT:
		ss->width = 8;
		break;
	case IORESOURCE_MEM_32BIT:
		ss->width = 32;
		break;
	default:
		dev_err(&pdev->dev, "No support width\n");
		return -ENODEV;
	}
	ss->irq = irq;
	ss->host = host;
	ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (ss->addr == NULL) {
		dev_err(&pdev->dev, "ioremap error.\n");
		return -ENOMEM;
	}
	init_waitqueue_head(&ss->wait);

	ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
	if (ret < 0) {
		dev_err(&pdev->dev, "request_irq error\n");
		return ret;
	}

	host->num_chipselect = 2;
	host->bus_num = pdev->id;
	host->setup = spi_sh_setup;
	host->transfer_one_message = spi_sh_transfer_one_message;
	host->cleanup = spi_sh_cleanup;

	ret = spi_register_controller(host);
	if (ret < 0) {
		printk(KERN_ERR "spi_register_controller error.\n");
		goto error3;
	}

	return 0;

 error3:
	free_irq(irq, ss);
	return ret;
}

static struct platform_driver spi_sh_driver = {
	.probe = spi_sh_probe,
	.remove_new = spi_sh_remove,
	.driver = {
		.name = "sh_spi",
	},
};
module_platform_driver(spi_sh_driver);

MODULE_DESCRIPTION("SH SPI bus driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Yoshihiro Shimoda");
MODULE_ALIAS("platform:sh_spi");
Commit	Line	Data
9135bac3	1	// SPDX-License-Identifier: GPL-2.0
5c05dd07 YS	2	/*
	3	* SH SPI bus driver
	4	*
	5	* Copyright (C) 2011 Renesas Solutions Corp.
	6	*
	7	* Based on pxa2xx_spi.c:
	8	* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
5c05dd07 YS	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
	14	#include <linux/errno.h>
	15	#include <linux/timer.h>
	16	#include <linux/delay.h>
	17	#include <linux/list.h>
	18	#include <linux/workqueue.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/io.h>
	22	#include <linux/spi/spi.h>
	23
	24	#define SPI_SH_TBR 0x00
	25	#define SPI_SH_RBR 0x00
	26	#define SPI_SH_CR1 0x08
	27	#define SPI_SH_CR2 0x10
	28	#define SPI_SH_CR3 0x18
	29	#define SPI_SH_CR4 0x20
	30	#define SPI_SH_CR5 0x28
	31
	32	/* CR1 */
	33	#define SPI_SH_TBE 0x80
	34	#define SPI_SH_TBF 0x40
	35	#define SPI_SH_RBE 0x20
	36	#define SPI_SH_RBF 0x10
	37	#define SPI_SH_PFONRD 0x08
	38	#define SPI_SH_SSDB 0x04
	39	#define SPI_SH_SSD 0x02
	40	#define SPI_SH_SSA 0x01
	41
	42	/* CR2 */
	43	#define SPI_SH_RSTF 0x80
	44	#define SPI_SH_LOOPBK 0x40
	45	#define SPI_SH_CPOL 0x20
	46	#define SPI_SH_CPHA 0x10
	47	#define SPI_SH_L1M0 0x08
	48
	49	/* CR3 */
	50	#define SPI_SH_MAX_BYTE 0xFF
	51
	52	/* CR4 */
	53	#define SPI_SH_TBEI 0x80
	54	#define SPI_SH_TBFI 0x40
	55	#define SPI_SH_RBEI 0x20
	56	#define SPI_SH_RBFI 0x10
	57	#define SPI_SH_WPABRT 0x04
	58	#define SPI_SH_SSS 0x01
	59
	60	/* CR8 */
	61	#define SPI_SH_P1L0 0x80
	62	#define SPI_SH_PP1L0 0x40
	63	#define SPI_SH_MUXI 0x20
	64	#define SPI_SH_MUXIRQ 0x10
	65
	66	#define SPI_SH_FIFO_SIZE 32
	67	#define SPI_SH_SEND_TIMEOUT (3 * HZ)
	68	#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
	69
	70	#undef DEBUG
	71
	72	struct spi_sh_data {
73	void __iomem *addr;
74	int irq;
0ec6a150	75	struct spi_controller *host;
5c05dd07 YS	76	unsigned long cr1;
5c05dd07 YS	77	wait_queue_head_t wait;
0eb8880f	78	int width;
5c05dd07 YS	79	};
	80
	81	static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
	82	unsigned long offset)
	83	{
0eb8880f SY	84	if (ss->width == 8)
	85	iowrite8(data, ss->addr + (offset >> 2));
	86	else if (ss->width == 32)
	87	iowrite32(data, ss->addr + offset);
5c05dd07 YS	88	}
	89
	90	static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
	91	{
0eb8880f SY	92	if (ss->width == 8)
	93	return ioread8(ss->addr + (offset >> 2));
	94	else if (ss->width == 32)
	95	return ioread32(ss->addr + offset);
	96	else
	97	return 0;
5c05dd07 YS	98	}
	99
	100	static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
	101	unsigned long offset)
	102	{
	103	unsigned long tmp;
	104
	105	tmp = spi_sh_read(ss, offset);
	106	tmp \|= val;
	107	spi_sh_write(ss, tmp, offset);
	108	}
	109
	110	static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
	111	unsigned long offset)
	112	{
	113	unsigned long tmp;
	114
	115	tmp = spi_sh_read(ss, offset);
	116	tmp &= ~val;
	117	spi_sh_write(ss, tmp, offset);
	118	}
	119
	120	static void clear_fifo(struct spi_sh_data *ss)
	121	{
	122	spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
	123	spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
	124	}
	125
	126	static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
	127	{
	128	int timeout = 100000;
	129
	130	while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
	131	udelay(10);
	132	if (timeout-- < 0)
	133	return -ETIMEDOUT;
	134	}
	135	return 0;
	136	}
	137
	138	static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
	139	{
	140	int timeout = 100000;
	141
	142	while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
	143	udelay(10);
	144	if (timeout-- < 0)
	145	return -ETIMEDOUT;
	146	}
	147	return 0;
	148	}
	149
	150	static int spi_sh_send(struct spi_sh_data ss, struct spi_message mesg,
	151	struct spi_transfer *t)
	152	{
	153	int i, retval = 0;
	154	int remain = t->len;
	155	int cur_len;
	156	unsigned char *data;
5c05dd07 YS	157	long ret;
	158
	159	if (t->len)
	160	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
	161
	162	data = (unsigned char *)t->tx_buf;
	163	while (remain > 0) {
	164	cur_len = min(SPI_SH_FIFO_SIZE, remain);
	165	for (i = 0; i < cur_len &&
	166	!(spi_sh_read(ss, SPI_SH_CR4) &
	167	SPI_SH_WPABRT) &&
	168	!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
	169	i++)
	170	spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
	171
	172	if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
	173	/* Abort SPI operation */
	174	spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
	175	retval = -EIO;
	176	break;
	177	}
	178
	179	cur_len = i;
	180
	181	remain -= cur_len;
	182	data += cur_len;
	183
	184	if (remain > 0) {
	185	ss->cr1 &= ~SPI_SH_TBE;
	186	spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
	187	ret = wait_event_interruptible_timeout(ss->wait,
	188	ss->cr1 & SPI_SH_TBE,
	189	SPI_SH_SEND_TIMEOUT);
	190	if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
	191	printk(KERN_ERR "%s: timeout\n", __func__);
	192	return -ETIMEDOUT;
	193	}
	194	}
	195	}
	196
	197	if (list_is_last(&t->transfer_list, &mesg->transfers)) {
909e709c	198	spi_sh_clear_bit(ss, SPI_SH_SSD \| SPI_SH_SSDB, SPI_SH_CR1);
5c05dd07 YS	199	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
	200
	201	ss->cr1 &= ~SPI_SH_TBE;
	202	spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
	203	ret = wait_event_interruptible_timeout(ss->wait,
	204	ss->cr1 & SPI_SH_TBE,
	205	SPI_SH_SEND_TIMEOUT);
	206	if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
	207	printk(KERN_ERR "%s: timeout\n", __func__);
	208	return -ETIMEDOUT;
	209	}
	210	}
	211
	212	return retval;
	213	}
	214
	215	static int spi_sh_receive(struct spi_sh_data ss, struct spi_message mesg,
	216	struct spi_transfer *t)
	217	{
	218	int i;
	219	int remain = t->len;
	220	int cur_len;
	221	unsigned char *data;
5c05dd07 YS	222	long ret;
	223
	224	if (t->len > SPI_SH_MAX_BYTE)
	225	spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
	226	else
	227	spi_sh_write(ss, t->len, SPI_SH_CR3);
	228
909e709c	229	spi_sh_clear_bit(ss, SPI_SH_SSD \| SPI_SH_SSDB, SPI_SH_CR1);
5c05dd07 YS	230	spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
	231
	232	spi_sh_wait_write_buffer_empty(ss);
	233
	234	data = (unsigned char *)t->rx_buf;
	235	while (remain > 0) {
	236	if (remain >= SPI_SH_FIFO_SIZE) {
	237	ss->cr1 &= ~SPI_SH_RBF;
	238	spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
	239	ret = wait_event_interruptible_timeout(ss->wait,
	240	ss->cr1 & SPI_SH_RBF,
	241	SPI_SH_RECEIVE_TIMEOUT);
	242	if (ret == 0 &&
	243	spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
	244	printk(KERN_ERR "%s: timeout\n", __func__);
	245	return -ETIMEDOUT;
	246	}
	247	}
	248
	249	cur_len = min(SPI_SH_FIFO_SIZE, remain);
	250	for (i = 0; i < cur_len; i++) {
	251	if (spi_sh_wait_receive_buffer(ss))
	252	break;
	253	data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
	254	}
	255
	256	remain -= cur_len;
	257	data += cur_len;
	258	}
	259
	260	/* deassert CS when SPI is receiving. */
	261	if (t->len > SPI_SH_MAX_BYTE) {
	262	clear_fifo(ss);
	263	spi_sh_write(ss, 1, SPI_SH_CR3);
	264	} else {
	265	spi_sh_write(ss, 0, SPI_SH_CR3);
	266	}
	267
	268	return 0;
	269	}
	270
e2185072 MB	271	static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
e2185072 MB	272	struct spi_message *mesg)
5c05dd07	273	{
e2185072	274	struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
5c05dd07	275	struct spi_transfer *t;
5c05dd07 YS	276	int ret;
	277
	278	pr_debug("%s: enter\n", __func__);
	279
e2185072	280	spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
5c05dd07	281
e2185072 MB	282	list_for_each_entry(t, &mesg->transfers, transfer_list) {
	283	pr_debug("tx_buf = %p, rx_buf = %p\n",
	284	t->tx_buf, t->rx_buf);
	285	pr_debug("len = %d, delay.value = %d\n",
	286	t->len, t->delay.value);
	287
	288	if (t->tx_buf) {
	289	ret = spi_sh_send(ss, mesg, t);
	290	if (ret < 0)
	291	goto error;
	292	}
	293	if (t->rx_buf) {
	294	ret = spi_sh_receive(ss, mesg, t);
	295	if (ret < 0)
	296	goto error;
	297	}
	298	mesg->actual_length += t->len;
5c05dd07 YS	299	}
5c05dd07 YS	300
e2185072 MB	301	mesg->status = 0;
	302	spi_finalize_current_message(ctlr);
	303
5c05dd07 YS	304	clear_fifo(ss);
	305	spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
	306	udelay(100);
	307
	308	spi_sh_clear_bit(ss, SPI_SH_SSA \| SPI_SH_SSDB \| SPI_SH_SSD,
	309	SPI_SH_CR1);
	310
	311	clear_fifo(ss);
	312
e2185072	313	return 0;
5c05dd07 YS	314
	315	error:
	316	mesg->status = ret;
e2185072	317	spi_finalize_current_message(ctlr);
0a6d3879 AL	318	if (mesg->complete)
0a6d3879 AL	319	mesg->complete(mesg->context);
5c05dd07 YS	320
	321	spi_sh_clear_bit(ss, SPI_SH_SSA \| SPI_SH_SSDB \| SPI_SH_SSD,
	322	SPI_SH_CR1);
	323	clear_fifo(ss);
	324
e2185072	325	return ret;
5c05dd07 YS	326	}
	327
	328	static int spi_sh_setup(struct spi_device *spi)
	329	{
0ec6a150	330	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
5c05dd07	331
5c05dd07 YS	332	pr_debug("%s: enter\n", __func__);
	333
	334	spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
	335	spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
	336	spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
	337
	338	clear_fifo(ss);
	339
	340	/* 1/8 clock */
	341	spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) \| 0x07, SPI_SH_CR2);
	342	udelay(10);
	343
	344	return 0;
	345	}
	346
5c05dd07 YS	347	static void spi_sh_cleanup(struct spi_device *spi)
5c05dd07 YS	348	{
0ec6a150	349	struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
5c05dd07 YS	350
	351	pr_debug("%s: enter\n", __func__);
	352
	353	spi_sh_clear_bit(ss, SPI_SH_SSA \| SPI_SH_SSDB \| SPI_SH_SSD,
	354	SPI_SH_CR1);
	355	}
	356
	357	static irqreturn_t spi_sh_irq(int irq, void *_ss)
	358	{
	359	struct spi_sh_data ss = (struct spi_sh_data )_ss;
	360	unsigned long cr1;
	361
	362	cr1 = spi_sh_read(ss, SPI_SH_CR1);
	363	if (cr1 & SPI_SH_TBE)
	364	ss->cr1 \|= SPI_SH_TBE;
	365	if (cr1 & SPI_SH_TBF)
	366	ss->cr1 \|= SPI_SH_TBF;
	367	if (cr1 & SPI_SH_RBE)
	368	ss->cr1 \|= SPI_SH_RBE;
	369	if (cr1 & SPI_SH_RBF)
	370	ss->cr1 \|= SPI_SH_RBF;
	371
	372	if (ss->cr1) {
	373	spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
	374	wake_up(&ss->wait);
	375	}
	376
	377	return IRQ_HANDLED;
	378	}
	379
dee2e255	380	static void spi_sh_remove(struct platform_device *pdev)
5c05dd07	381	{
24b5a82c	382	struct spi_sh_data *ss = platform_get_drvdata(pdev);
5c05dd07	383
0ec6a150	384	spi_unregister_controller(ss->host);
5c05dd07	385	free_irq(ss->irq, ss);
5c05dd07 YS	386	}
5c05dd07 YS	387
fd4a319b	388	static int spi_sh_probe(struct platform_device *pdev)
5c05dd07 YS	389	{
5c05dd07 YS	390	struct resource *res;
0ec6a150	391	struct spi_controller *host;
5c05dd07 YS	392	struct spi_sh_data *ss;
	393	int ret, irq;
	394
	395	/* get base addr */
	396	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	397	if (unlikely(res == NULL)) {
	398	dev_err(&pdev->dev, "invalid resource\n");
	399	return -EINVAL;
	400	}
	401
	402	irq = platform_get_irq(pdev, 0);
6b8ac10e	403	if (irq < 0)
345fef75	404	return irq;
5c05dd07	405
0ec6a150 YY	406	host = devm_spi_alloc_host(&pdev->dev, sizeof(struct spi_sh_data));
	407	if (host == NULL) {
	408	dev_err(&pdev->dev, "devm_spi_alloc_host error.\n");
5c05dd07 YS	409	return -ENOMEM;
	410	}
	411
0ec6a150	412	ss = spi_controller_get_devdata(host);
24b5a82c	413	platform_set_drvdata(pdev, ss);
5c05dd07	414
0eb8880f SY	415	switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
	416	case IORESOURCE_MEM_8BIT:
	417	ss->width = 8;
	418	break;
	419	case IORESOURCE_MEM_32BIT:
	420	ss->width = 32;
	421	break;
	422	default:
	423	dev_err(&pdev->dev, "No support width\n");
e77df3ec	424	return -ENODEV;
0eb8880f	425	}
5c05dd07	426	ss->irq = irq;
0ec6a150	427	ss->host = host;
e9d42d15	428	ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
5c05dd07 YS	429	if (ss->addr == NULL) {
5c05dd07 YS	430	dev_err(&pdev->dev, "ioremap error.\n");
e77df3ec	431	return -ENOMEM;
5c05dd07	432	}
5c05dd07	433	init_waitqueue_head(&ss->wait);
5c05dd07	434
38ada214	435	ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
5c05dd07 YS	436	if (ret < 0) {
5c05dd07 YS	437	dev_err(&pdev->dev, "request_irq error\n");
e77df3ec	438	return ret;
5c05dd07 YS	439	}
5c05dd07 YS	440
0ec6a150 YY	441	host->num_chipselect = 2;
	442	host->bus_num = pdev->id;
	443	host->setup = spi_sh_setup;
	444	host->transfer_one_message = spi_sh_transfer_one_message;
	445	host->cleanup = spi_sh_cleanup;
5c05dd07	446
0ec6a150	447	ret = spi_register_controller(host);
5c05dd07	448	if (ret < 0) {
0ec6a150	449	printk(KERN_ERR "spi_register_controller error.\n");
e9d42d15	450	goto error3;
5c05dd07 YS	451	}
	452
	453	return 0;
	454
5c05dd07	455	error3:
e9d42d15	456	free_irq(irq, ss);
5c05dd07 YS	457	return ret;
	458	}
	459
	460	static struct platform_driver spi_sh_driver = {
	461	.probe = spi_sh_probe,
dee2e255	462	.remove_new = spi_sh_remove,
5c05dd07 YS	463	.driver = {
5c05dd07 YS	464	.name = "sh_spi",
5c05dd07 YS	465	},
5c05dd07 YS	466	};
940ab889	467	module_platform_driver(spi_sh_driver);
5c05dd07 YS	468
5c05dd07 YS	469	MODULE_DESCRIPTION("SH SPI bus driver");
9135bac3	470	MODULE_LICENSE("GPL v2");
5c05dd07 YS	471	MODULE_AUTHOR("Yoshihiro Shimoda");
5c05dd07 YS	472	MODULE_ALIAS("platform:sh_spi");