Commit | Line | Data |
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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
cf9e4784 HN |
5 | * Copyright (C) 2014 Renesas Electronics Corporation |
6 | * Copyright (C) 2014-2017 Glider bvba | |
8051effc MD |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
e2dbf5eb GL |
14 | #include <linux/bitmap.h> |
15 | #include <linux/clk.h> | |
16 | #include <linux/completion.h> | |
8051effc | 17 | #include <linux/delay.h> |
b0d0ce8b GU |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/dmaengine.h> | |
e2dbf5eb GL |
20 | #include <linux/err.h> |
21 | #include <linux/gpio.h> | |
8051effc | 22 | #include <linux/interrupt.h> |
e2dbf5eb GL |
23 | #include <linux/io.h> |
24 | #include <linux/kernel.h> | |
d7614de4 | 25 | #include <linux/module.h> |
cf9c86ef | 26 | #include <linux/of.h> |
50a7e23f | 27 | #include <linux/of_device.h> |
8051effc | 28 | #include <linux/platform_device.h> |
8051effc | 29 | #include <linux/pm_runtime.h> |
b0d0ce8b | 30 | #include <linux/sh_dma.h> |
8051effc | 31 | |
e2dbf5eb | 32 | #include <linux/spi/sh_msiof.h> |
8051effc | 33 | #include <linux/spi/spi.h> |
8051effc | 34 | |
8051effc MD |
35 | #include <asm/unaligned.h> |
36 | ||
50a7e23f GU |
37 | struct sh_msiof_chipdata { |
38 | u16 tx_fifo_size; | |
39 | u16 rx_fifo_size; | |
beb74bb0 | 40 | u16 master_flags; |
61a8dec5 | 41 | u16 min_div; |
50a7e23f GU |
42 | }; |
43 | ||
8051effc | 44 | struct sh_msiof_spi_priv { |
b0d0ce8b | 45 | struct spi_master *master; |
8051effc MD |
46 | void __iomem *mapbase; |
47 | struct clk *clk; | |
48 | struct platform_device *pdev; | |
49 | struct sh_msiof_spi_info *info; | |
50 | struct completion done; | |
fe78d0b7 KM |
51 | unsigned int tx_fifo_size; |
52 | unsigned int rx_fifo_size; | |
61a8dec5 | 53 | unsigned int min_div; |
b0d0ce8b GU |
54 | void *tx_dma_page; |
55 | void *rx_dma_page; | |
56 | dma_addr_t tx_dma_addr; | |
57 | dma_addr_t rx_dma_addr; | |
7ff0b53c GU |
58 | bool native_cs_inited; |
59 | bool native_cs_high; | |
cf9e4784 | 60 | bool slave_aborted; |
8051effc MD |
61 | }; |
62 | ||
9cce882b GU |
63 | #define MAX_SS 3 /* Maximum number of native chip selects */ |
64 | ||
01cfef57 GU |
65 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
66 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
67 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
68 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
69 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
70 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
71 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
72 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
73 | #define CTR 0x28 /* Control Register */ | |
74 | #define FCTR 0x30 /* FIFO Control Register */ | |
75 | #define STR 0x40 /* Status Register */ | |
76 | #define IER 0x44 /* Interrupt Enable Register */ | |
77 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
78 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
79 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
80 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
81 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
82 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
83 | ||
84 | /* TMDR1 and RMDR1 */ | |
85 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
86 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
87 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
88 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
89 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
90 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
3110628d YS |
91 | #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ |
92 | #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ | |
6d40530e | 93 | #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ |
01cfef57 GU |
94 | #define MDR1_FLD_SHIFT 2 |
95 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
96 | /* TMDR1 */ | |
97 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
9cce882b GU |
98 | #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */ |
99 | #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ | |
01cfef57 GU |
100 | |
101 | /* TMDR2 and RMDR2 */ | |
102 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
103 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
104 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
105 | ||
106 | /* TSCR and RSCR */ | |
107 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
108 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
109 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
110 | #define SCR_BRDV_DIV_2 0x0000 | |
111 | #define SCR_BRDV_DIV_4 0x0001 | |
112 | #define SCR_BRDV_DIV_8 0x0002 | |
113 | #define SCR_BRDV_DIV_16 0x0003 | |
114 | #define SCR_BRDV_DIV_32 0x0004 | |
115 | #define SCR_BRDV_DIV_1 0x0007 | |
116 | ||
117 | /* CTR */ | |
118 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
119 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
120 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
121 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
122 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
123 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
124 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
125 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
126 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
127 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
128 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
129 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
130 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
131 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
132 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
133 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
134 | ||
2e2b3687 GU |
135 | /* FCTR */ |
136 | #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ | |
137 | #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ | |
138 | #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ | |
139 | #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ | |
140 | #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ | |
141 | #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ | |
142 | #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ | |
143 | #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ | |
144 | #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ | |
145 | #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ | |
146 | #define FCTR_TFUA_SHIFT 20 | |
147 | #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) | |
148 | #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ | |
149 | #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ | |
150 | #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ | |
151 | #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ | |
152 | #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ | |
153 | #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ | |
154 | #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ | |
155 | #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ | |
156 | #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ | |
157 | #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ | |
158 | #define FCTR_RFUA_SHIFT 4 | |
159 | #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) | |
160 | ||
161 | /* STR */ | |
162 | #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ | |
163 | #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ | |
01cfef57 | 164 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ |
2e2b3687 GU |
165 | #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ |
166 | #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ | |
167 | #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ | |
168 | #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ | |
169 | #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ | |
01cfef57 | 170 | #define STR_REOF 0x00000080 /* Frame Reception End */ |
2e2b3687 GU |
171 | #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ |
172 | #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ | |
173 | #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ | |
174 | ||
175 | /* IER */ | |
176 | #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ | |
177 | #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ | |
178 | #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ | |
179 | #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ | |
180 | #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ | |
181 | #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ | |
182 | #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ | |
183 | #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ | |
184 | #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ | |
185 | #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ | |
186 | #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ | |
187 | #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ | |
188 | #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ | |
189 | #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ | |
01cfef57 | 190 | |
8051effc | 191 | |
e2dbf5eb | 192 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
193 | { |
194 | switch (reg_offs) { | |
195 | case TSCR: | |
196 | case RSCR: | |
197 | return ioread16(p->mapbase + reg_offs); | |
198 | default: | |
199 | return ioread32(p->mapbase + reg_offs); | |
200 | } | |
201 | } | |
202 | ||
203 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 204 | u32 value) |
8051effc MD |
205 | { |
206 | switch (reg_offs) { | |
207 | case TSCR: | |
208 | case RSCR: | |
209 | iowrite16(value, p->mapbase + reg_offs); | |
210 | break; | |
211 | default: | |
212 | iowrite32(value, p->mapbase + reg_offs); | |
213 | break; | |
214 | } | |
215 | } | |
216 | ||
217 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 218 | u32 clr, u32 set) |
8051effc | 219 | { |
e2dbf5eb GL |
220 | u32 mask = clr | set; |
221 | u32 data; | |
8051effc MD |
222 | int k; |
223 | ||
224 | data = sh_msiof_read(p, CTR); | |
225 | data &= ~clr; | |
226 | data |= set; | |
227 | sh_msiof_write(p, CTR, data); | |
228 | ||
229 | for (k = 100; k > 0; k--) { | |
230 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
231 | break; | |
232 | ||
233 | udelay(10); | |
234 | } | |
235 | ||
236 | return k > 0 ? 0 : -ETIMEDOUT; | |
237 | } | |
238 | ||
239 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
240 | { | |
241 | struct sh_msiof_spi_priv *p = data; | |
242 | ||
243 | /* just disable the interrupt and wake up */ | |
244 | sh_msiof_write(p, IER, 0); | |
245 | complete(&p->done); | |
246 | ||
247 | return IRQ_HANDLED; | |
248 | } | |
249 | ||
250 | static struct { | |
251 | unsigned short div; | |
65d5665b NI |
252 | unsigned short brdv; |
253 | } const sh_msiof_spi_div_table[] = { | |
254 | { 1, SCR_BRDV_DIV_1 }, | |
255 | { 2, SCR_BRDV_DIV_2 }, | |
256 | { 4, SCR_BRDV_DIV_4 }, | |
257 | { 8, SCR_BRDV_DIV_8 }, | |
258 | { 16, SCR_BRDV_DIV_16 }, | |
259 | { 32, SCR_BRDV_DIV_32 }, | |
8051effc MD |
260 | }; |
261 | ||
262 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 263 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
264 | { |
265 | unsigned long div = 1024; | |
65d5665b | 266 | u32 brps, scr; |
8051effc MD |
267 | size_t k; |
268 | ||
269 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 270 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc | 271 | |
61a8dec5 GU |
272 | div = max_t(unsigned long, div, p->min_div); |
273 | ||
65d5665b NI |
274 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) { |
275 | brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div); | |
c3ccf357 GU |
276 | /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ |
277 | if (sh_msiof_spi_div_table[k].div == 1 && brps > 2) | |
278 | continue; | |
65d5665b | 279 | if (brps <= 32) /* max of brdv is 32 */ |
8051effc MD |
280 | break; |
281 | } | |
282 | ||
65d5665b | 283 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); |
8051effc | 284 | |
65d5665b NI |
285 | scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); |
286 | sh_msiof_write(p, TSCR, scr); | |
a6802cc0 | 287 | if (!(p->master->flags & SPI_MASTER_MUST_TX)) |
65d5665b | 288 | sh_msiof_write(p, RSCR, scr); |
8051effc MD |
289 | } |
290 | ||
3110628d YS |
291 | static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) |
292 | { | |
293 | /* | |
294 | * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl | |
295 | * b'000 : 0 | |
296 | * b'001 : 100 | |
297 | * b'010 : 200 | |
298 | * b'011 (SYNCDL only) : 300 | |
299 | * b'101 : 50 | |
300 | * b'110 : 150 | |
301 | */ | |
302 | if (dtdl_or_syncdl % 100) | |
303 | return dtdl_or_syncdl / 100 + 5; | |
304 | else | |
305 | return dtdl_or_syncdl / 100; | |
306 | } | |
307 | ||
308 | static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) | |
309 | { | |
310 | u32 val; | |
311 | ||
312 | if (!p->info) | |
313 | return 0; | |
314 | ||
315 | /* check if DTDL and SYNCDL is allowed value */ | |
316 | if (p->info->dtdl > 200 || p->info->syncdl > 300) { | |
317 | dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); | |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* check if the sum of DTDL and SYNCDL becomes an integer value */ | |
322 | if ((p->info->dtdl + p->info->syncdl) % 100) { | |
323 | dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); | |
324 | return 0; | |
325 | } | |
326 | ||
327 | val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; | |
328 | val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; | |
329 | ||
330 | return val; | |
331 | } | |
332 | ||
9cce882b | 333 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, |
e2dbf5eb | 334 | u32 cpol, u32 cpha, |
50a77998 | 335 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 336 | { |
e2dbf5eb | 337 | u32 tmp; |
8051effc MD |
338 | int edge; |
339 | ||
340 | /* | |
e8708ef7 MP |
341 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
342 | * 0 0 10 10 1 1 | |
343 | * 0 1 10 10 0 0 | |
344 | * 1 0 11 11 0 0 | |
345 | * 1 1 11 11 1 1 | |
8051effc | 346 | */ |
01cfef57 GU |
347 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
348 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
349 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
3110628d | 350 | tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); |
9cce882b | 351 | if (spi_controller_is_slave(p->master)) { |
cf9e4784 | 352 | sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); |
9cce882b GU |
353 | } else { |
354 | sh_msiof_write(p, TMDR1, | |
355 | tmp | MDR1_TRMD | TMDR1_PCON | | |
356 | (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT); | |
357 | } | |
a6802cc0 | 358 | if (p->master->flags & SPI_MASTER_MUST_TX) { |
beb74bb0 GU |
359 | /* These bits are reserved if RX needs TX */ |
360 | tmp &= ~0x0000ffff; | |
361 | } | |
01cfef57 | 362 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 363 | |
01cfef57 GU |
364 | tmp = 0; |
365 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
366 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 367 | |
e2dbf5eb | 368 | edge = cpol ^ !cpha; |
8051effc | 369 | |
01cfef57 GU |
370 | tmp |= edge << CTR_TEDG_SHIFT; |
371 | tmp |= edge << CTR_REDG_SHIFT; | |
372 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
373 | sh_msiof_write(p, CTR, tmp); |
374 | } | |
375 | ||
376 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
377 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 378 | u32 bits, u32 words) |
8051effc | 379 | { |
01cfef57 | 380 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 381 | |
a6802cc0 | 382 | if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
383 | sh_msiof_write(p, TMDR2, dr2); |
384 | else | |
01cfef57 | 385 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
386 | |
387 | if (rx_buf) | |
388 | sh_msiof_write(p, RMDR2, dr2); | |
8051effc MD |
389 | } |
390 | ||
391 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
392 | { | |
393 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
394 | } | |
395 | ||
396 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
397 | const void *tx_buf, int words, int fs) | |
398 | { | |
e2dbf5eb | 399 | const u8 *buf_8 = tx_buf; |
8051effc MD |
400 | int k; |
401 | ||
402 | for (k = 0; k < words; k++) | |
403 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
404 | } | |
405 | ||
406 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
407 | const void *tx_buf, int words, int fs) | |
408 | { | |
e2dbf5eb | 409 | const u16 *buf_16 = tx_buf; |
8051effc MD |
410 | int k; |
411 | ||
412 | for (k = 0; k < words; k++) | |
413 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
414 | } | |
415 | ||
416 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
417 | const void *tx_buf, int words, int fs) | |
418 | { | |
e2dbf5eb | 419 | const u16 *buf_16 = tx_buf; |
8051effc MD |
420 | int k; |
421 | ||
422 | for (k = 0; k < words; k++) | |
423 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
424 | } | |
425 | ||
426 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
427 | const void *tx_buf, int words, int fs) | |
428 | { | |
e2dbf5eb | 429 | const u32 *buf_32 = tx_buf; |
8051effc MD |
430 | int k; |
431 | ||
432 | for (k = 0; k < words; k++) | |
433 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
434 | } | |
435 | ||
436 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
437 | const void *tx_buf, int words, int fs) | |
438 | { | |
e2dbf5eb | 439 | const u32 *buf_32 = tx_buf; |
8051effc MD |
440 | int k; |
441 | ||
442 | for (k = 0; k < words; k++) | |
443 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
444 | } | |
445 | ||
9dabb3f3 GL |
446 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
447 | const void *tx_buf, int words, int fs) | |
448 | { | |
449 | const u32 *buf_32 = tx_buf; | |
450 | int k; | |
451 | ||
452 | for (k = 0; k < words; k++) | |
453 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
454 | } | |
455 | ||
456 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
457 | const void *tx_buf, int words, int fs) | |
458 | { | |
459 | const u32 *buf_32 = tx_buf; | |
460 | int k; | |
461 | ||
462 | for (k = 0; k < words; k++) | |
463 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
464 | } | |
465 | ||
8051effc MD |
466 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
467 | void *rx_buf, int words, int fs) | |
468 | { | |
e2dbf5eb | 469 | u8 *buf_8 = rx_buf; |
8051effc MD |
470 | int k; |
471 | ||
472 | for (k = 0; k < words; k++) | |
473 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
474 | } | |
475 | ||
476 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
477 | void *rx_buf, int words, int fs) | |
478 | { | |
e2dbf5eb | 479 | u16 *buf_16 = rx_buf; |
8051effc MD |
480 | int k; |
481 | ||
482 | for (k = 0; k < words; k++) | |
483 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
484 | } | |
485 | ||
486 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
487 | void *rx_buf, int words, int fs) | |
488 | { | |
e2dbf5eb | 489 | u16 *buf_16 = rx_buf; |
8051effc MD |
490 | int k; |
491 | ||
492 | for (k = 0; k < words; k++) | |
493 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
494 | } | |
495 | ||
496 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
497 | void *rx_buf, int words, int fs) | |
498 | { | |
e2dbf5eb | 499 | u32 *buf_32 = rx_buf; |
8051effc MD |
500 | int k; |
501 | ||
502 | for (k = 0; k < words; k++) | |
503 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
504 | } | |
505 | ||
506 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
507 | void *rx_buf, int words, int fs) | |
508 | { | |
e2dbf5eb | 509 | u32 *buf_32 = rx_buf; |
8051effc MD |
510 | int k; |
511 | ||
512 | for (k = 0; k < words; k++) | |
513 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
514 | } | |
515 | ||
9dabb3f3 GL |
516 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
517 | void *rx_buf, int words, int fs) | |
518 | { | |
519 | u32 *buf_32 = rx_buf; | |
520 | int k; | |
521 | ||
522 | for (k = 0; k < words; k++) | |
523 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
524 | } | |
525 | ||
526 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
527 | void *rx_buf, int words, int fs) | |
528 | { | |
529 | u32 *buf_32 = rx_buf; | |
530 | int k; | |
531 | ||
532 | for (k = 0; k < words; k++) | |
533 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
534 | } | |
535 | ||
8d19534a | 536 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 537 | { |
8d19534a | 538 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 539 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
7ff0b53c | 540 | u32 clr, set, tmp; |
01576056 | 541 | |
8d19534a GU |
542 | if (!np) { |
543 | /* | |
544 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
545 | * if any. otherwise let HW control CS | |
546 | */ | |
547 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
548 | } | |
8051effc | 549 | |
7ff0b53c | 550 | if (spi->cs_gpio >= 0) { |
1bd6363b | 551 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); |
7ff0b53c GU |
552 | return 0; |
553 | } | |
8051effc | 554 | |
7ff0b53c GU |
555 | if (spi_controller_is_slave(p->master)) |
556 | return 0; | |
01576056 | 557 | |
7ff0b53c GU |
558 | if (p->native_cs_inited && |
559 | (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) | |
560 | return 0; | |
01576056 | 561 | |
7ff0b53c GU |
562 | /* Configure native chip select mode/polarity early */ |
563 | clr = MDR1_SYNCMD_MASK; | |
564 | set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI; | |
565 | if (spi->mode & SPI_CS_HIGH) | |
566 | clr |= BIT(MDR1_SYNCAC_SHIFT); | |
567 | else | |
568 | set |= BIT(MDR1_SYNCAC_SHIFT); | |
569 | pm_runtime_get_sync(&p->pdev->dev); | |
570 | tmp = sh_msiof_read(p, TMDR1) & ~clr; | |
571 | sh_msiof_write(p, TMDR1, tmp | set); | |
572 | pm_runtime_put(&p->pdev->dev); | |
573 | p->native_cs_high = spi->mode & SPI_CS_HIGH; | |
574 | p->native_cs_inited = true; | |
1bd6363b | 575 | return 0; |
8051effc MD |
576 | } |
577 | ||
c833ff73 GU |
578 | static int sh_msiof_prepare_message(struct spi_master *master, |
579 | struct spi_message *msg) | |
8051effc | 580 | { |
c833ff73 GU |
581 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
582 | const struct spi_device *spi = msg->spi; | |
8051effc | 583 | |
c833ff73 | 584 | /* Configure pins before asserting CS */ |
9cce882b GU |
585 | sh_msiof_spi_set_pin_regs(p, spi->chip_select, |
586 | !!(spi->mode & SPI_CPOL), | |
c833ff73 GU |
587 | !!(spi->mode & SPI_CPHA), |
588 | !!(spi->mode & SPI_3WIRE), | |
589 | !!(spi->mode & SPI_LSB_FIRST), | |
590 | !!(spi->mode & SPI_CS_HIGH)); | |
591 | return 0; | |
8051effc MD |
592 | } |
593 | ||
76c02e71 GU |
594 | static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) |
595 | { | |
cf9e4784 HN |
596 | bool slave = spi_controller_is_slave(p->master); |
597 | int ret = 0; | |
76c02e71 GU |
598 | |
599 | /* setup clock and rx/tx signals */ | |
cf9e4784 HN |
600 | if (!slave) |
601 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
76c02e71 GU |
602 | if (rx_buf && !ret) |
603 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
604 | if (!ret) | |
605 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
606 | ||
607 | /* start by setting frame bit */ | |
cf9e4784 | 608 | if (!ret && !slave) |
76c02e71 GU |
609 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
614 | static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) | |
615 | { | |
cf9e4784 HN |
616 | bool slave = spi_controller_is_slave(p->master); |
617 | int ret = 0; | |
76c02e71 GU |
618 | |
619 | /* shut down frame, rx/tx and clock signals */ | |
cf9e4784 HN |
620 | if (!slave) |
621 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
76c02e71 GU |
622 | if (!ret) |
623 | ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
624 | if (rx_buf && !ret) | |
625 | ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
cf9e4784 | 626 | if (!ret && !slave) |
76c02e71 GU |
627 | ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
cf9e4784 HN |
632 | static int sh_msiof_slave_abort(struct spi_master *master) |
633 | { | |
634 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
635 | ||
636 | p->slave_aborted = true; | |
637 | complete(&p->done); | |
638 | return 0; | |
639 | } | |
640 | ||
641 | static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p) | |
642 | { | |
643 | if (spi_controller_is_slave(p->master)) { | |
644 | if (wait_for_completion_interruptible(&p->done) || | |
645 | p->slave_aborted) { | |
646 | dev_dbg(&p->pdev->dev, "interrupted\n"); | |
647 | return -EINTR; | |
648 | } | |
649 | } else { | |
650 | if (!wait_for_completion_timeout(&p->done, HZ)) { | |
651 | dev_err(&p->pdev->dev, "timeout\n"); | |
652 | return -ETIMEDOUT; | |
653 | } | |
654 | } | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
8051effc MD |
659 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
660 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
661 | const void *, int, int), | |
662 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
663 | void *, int, int), | |
664 | const void *tx_buf, void *rx_buf, | |
665 | int words, int bits) | |
666 | { | |
667 | int fifo_shift; | |
668 | int ret; | |
669 | ||
670 | /* limit maximum word transfer to rx/tx fifo size */ | |
671 | if (tx_buf) | |
672 | words = min_t(int, words, p->tx_fifo_size); | |
673 | if (rx_buf) | |
674 | words = min_t(int, words, p->rx_fifo_size); | |
675 | ||
676 | /* the fifo contents need shifting */ | |
677 | fifo_shift = 32 - bits; | |
678 | ||
b0d0ce8b GU |
679 | /* default FIFO watermarks for PIO */ |
680 | sh_msiof_write(p, FCTR, 0); | |
681 | ||
8051effc MD |
682 | /* setup msiof transfer mode registers */ |
683 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
b0d0ce8b | 684 | sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); |
8051effc MD |
685 | |
686 | /* write tx fifo */ | |
687 | if (tx_buf) | |
688 | tx_fifo(p, tx_buf, words, fifo_shift); | |
689 | ||
16735d02 | 690 | reinit_completion(&p->done); |
cf9e4784 | 691 | p->slave_aborted = false; |
76c02e71 GU |
692 | |
693 | ret = sh_msiof_spi_start(p, rx_buf); | |
8051effc MD |
694 | if (ret) { |
695 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
75b82e23 | 696 | goto stop_ier; |
8051effc MD |
697 | } |
698 | ||
699 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
cf9e4784 HN |
700 | ret = sh_msiof_wait_for_completion(p); |
701 | if (ret) | |
75b82e23 | 702 | goto stop_reset; |
8051effc MD |
703 | |
704 | /* read rx fifo */ | |
705 | if (rx_buf) | |
706 | rx_fifo(p, rx_buf, words, fifo_shift); | |
707 | ||
708 | /* clear status bits */ | |
709 | sh_msiof_reset_str(p); | |
710 | ||
76c02e71 | 711 | ret = sh_msiof_spi_stop(p, rx_buf); |
8051effc MD |
712 | if (ret) { |
713 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
75b82e23 | 714 | return ret; |
8051effc MD |
715 | } |
716 | ||
717 | return words; | |
718 | ||
75b82e23 GU |
719 | stop_reset: |
720 | sh_msiof_reset_str(p); | |
721 | sh_msiof_spi_stop(p, rx_buf); | |
722 | stop_ier: | |
8051effc MD |
723 | sh_msiof_write(p, IER, 0); |
724 | return ret; | |
725 | } | |
726 | ||
b0d0ce8b GU |
727 | static void sh_msiof_dma_complete(void *arg) |
728 | { | |
729 | struct sh_msiof_spi_priv *p = arg; | |
730 | ||
731 | sh_msiof_write(p, IER, 0); | |
732 | complete(&p->done); | |
733 | } | |
734 | ||
735 | static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, | |
736 | void *rx, unsigned int len) | |
737 | { | |
738 | u32 ier_bits = 0; | |
739 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; | |
740 | dma_cookie_t cookie; | |
741 | int ret; | |
742 | ||
3e81b592 | 743 | /* First prepare and submit the DMA request(s), as this may fail */ |
b0d0ce8b GU |
744 | if (rx) { |
745 | ier_bits |= IER_RDREQE | IER_RDMAE; | |
746 | desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, | |
747 | p->rx_dma_addr, len, DMA_FROM_DEVICE, | |
748 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
a5e7c719 GU |
749 | if (!desc_rx) |
750 | return -EAGAIN; | |
b0d0ce8b | 751 | |
b0d0ce8b GU |
752 | desc_rx->callback = sh_msiof_dma_complete; |
753 | desc_rx->callback_param = p; | |
754 | cookie = dmaengine_submit(desc_rx); | |
a5e7c719 GU |
755 | if (dma_submit_error(cookie)) |
756 | return cookie; | |
b0d0ce8b GU |
757 | } |
758 | ||
759 | if (tx) { | |
3e81b592 GU |
760 | ier_bits |= IER_TDREQE | IER_TDMAE; |
761 | dma_sync_single_for_device(p->master->dma_tx->device->dev, | |
762 | p->tx_dma_addr, len, DMA_TO_DEVICE); | |
763 | desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, | |
764 | p->tx_dma_addr, len, DMA_TO_DEVICE, | |
765 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
766 | if (!desc_tx) { | |
767 | ret = -EAGAIN; | |
768 | goto no_dma_tx; | |
769 | } | |
770 | ||
b0d0ce8b GU |
771 | if (rx) { |
772 | /* No callback */ | |
773 | desc_tx->callback = NULL; | |
774 | } else { | |
775 | desc_tx->callback = sh_msiof_dma_complete; | |
776 | desc_tx->callback_param = p; | |
777 | } | |
778 | cookie = dmaengine_submit(desc_tx); | |
779 | if (dma_submit_error(cookie)) { | |
780 | ret = cookie; | |
3e81b592 | 781 | goto no_dma_tx; |
b0d0ce8b | 782 | } |
b0d0ce8b GU |
783 | } |
784 | ||
3e81b592 GU |
785 | /* 1 stage FIFO watermarks for DMA */ |
786 | sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); | |
787 | ||
788 | /* setup msiof transfer mode registers (32-bit words) */ | |
789 | sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); | |
790 | ||
791 | sh_msiof_write(p, IER, ier_bits); | |
792 | ||
793 | reinit_completion(&p->done); | |
cf9e4784 | 794 | p->slave_aborted = false; |
3e81b592 GU |
795 | |
796 | /* Now start DMA */ | |
3e81b592 | 797 | if (rx) |
7a9f957b GU |
798 | dma_async_issue_pending(p->master->dma_rx); |
799 | if (tx) | |
3e81b592 GU |
800 | dma_async_issue_pending(p->master->dma_tx); |
801 | ||
b0d0ce8b GU |
802 | ret = sh_msiof_spi_start(p, rx); |
803 | if (ret) { | |
804 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
3e81b592 | 805 | goto stop_dma; |
b0d0ce8b GU |
806 | } |
807 | ||
808 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
cf9e4784 HN |
809 | ret = sh_msiof_wait_for_completion(p); |
810 | if (ret) | |
b0d0ce8b | 811 | goto stop_reset; |
b0d0ce8b GU |
812 | |
813 | /* clear status bits */ | |
814 | sh_msiof_reset_str(p); | |
815 | ||
816 | ret = sh_msiof_spi_stop(p, rx); | |
817 | if (ret) { | |
818 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
819 | return ret; | |
820 | } | |
821 | ||
822 | if (rx) | |
5dabcf2f GU |
823 | dma_sync_single_for_cpu(p->master->dma_rx->device->dev, |
824 | p->rx_dma_addr, len, | |
b0d0ce8b GU |
825 | DMA_FROM_DEVICE); |
826 | ||
827 | return 0; | |
828 | ||
829 | stop_reset: | |
830 | sh_msiof_reset_str(p); | |
831 | sh_msiof_spi_stop(p, rx); | |
3e81b592 | 832 | stop_dma: |
b0d0ce8b GU |
833 | if (tx) |
834 | dmaengine_terminate_all(p->master->dma_tx); | |
3e81b592 | 835 | no_dma_tx: |
b0d0ce8b GU |
836 | if (rx) |
837 | dmaengine_terminate_all(p->master->dma_rx); | |
b0d0ce8b GU |
838 | sh_msiof_write(p, IER, 0); |
839 | return ret; | |
840 | } | |
841 | ||
842 | static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) | |
843 | { | |
844 | /* src or dst can be unaligned, but not both */ | |
845 | if ((unsigned long)src & 3) { | |
846 | while (words--) { | |
847 | *dst++ = swab32(get_unaligned(src)); | |
848 | src++; | |
849 | } | |
850 | } else if ((unsigned long)dst & 3) { | |
851 | while (words--) { | |
852 | put_unaligned(swab32(*src++), dst); | |
853 | dst++; | |
854 | } | |
855 | } else { | |
856 | while (words--) | |
857 | *dst++ = swab32(*src++); | |
858 | } | |
859 | } | |
860 | ||
861 | static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) | |
862 | { | |
863 | /* src or dst can be unaligned, but not both */ | |
864 | if ((unsigned long)src & 3) { | |
865 | while (words--) { | |
866 | *dst++ = swahw32(get_unaligned(src)); | |
867 | src++; | |
868 | } | |
869 | } else if ((unsigned long)dst & 3) { | |
870 | while (words--) { | |
871 | put_unaligned(swahw32(*src++), dst); | |
872 | dst++; | |
873 | } | |
874 | } else { | |
875 | while (words--) | |
876 | *dst++ = swahw32(*src++); | |
877 | } | |
878 | } | |
879 | ||
880 | static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) | |
881 | { | |
882 | memcpy(dst, src, words * 4); | |
883 | } | |
884 | ||
1bd6363b GU |
885 | static int sh_msiof_transfer_one(struct spi_master *master, |
886 | struct spi_device *spi, | |
887 | struct spi_transfer *t) | |
8051effc | 888 | { |
1bd6363b | 889 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
b0d0ce8b | 890 | void (*copy32)(u32 *, const u32 *, unsigned int); |
8051effc MD |
891 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
892 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
0312d591 GU |
893 | const void *tx_buf = t->tx_buf; |
894 | void *rx_buf = t->rx_buf; | |
895 | unsigned int len = t->len; | |
896 | unsigned int bits = t->bits_per_word; | |
897 | unsigned int bytes_per_word; | |
898 | unsigned int words; | |
8051effc | 899 | int n; |
9dabb3f3 | 900 | bool swab; |
b0d0ce8b GU |
901 | int ret; |
902 | ||
903 | /* setup clocks (clock already enabled in chipselect()) */ | |
cf9e4784 HN |
904 | if (!spi_controller_is_slave(p->master)) |
905 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); | |
b0d0ce8b GU |
906 | |
907 | while (master->dma_tx && len > 15) { | |
908 | /* | |
909 | * DMA supports 32-bit words only, hence pack 8-bit and 16-bit | |
910 | * words, with byte resp. word swapping. | |
911 | */ | |
fe78d0b7 KM |
912 | unsigned int l = 0; |
913 | ||
914 | if (tx_buf) | |
915 | l = min(len, p->tx_fifo_size * 4); | |
916 | if (rx_buf) | |
917 | l = min(len, p->rx_fifo_size * 4); | |
b0d0ce8b GU |
918 | |
919 | if (bits <= 8) { | |
920 | if (l & 3) | |
921 | break; | |
922 | copy32 = copy_bswap32; | |
923 | } else if (bits <= 16) { | |
36735783 | 924 | if (l & 3) |
b0d0ce8b GU |
925 | break; |
926 | copy32 = copy_wswap32; | |
927 | } else { | |
928 | copy32 = copy_plain32; | |
929 | } | |
930 | ||
931 | if (tx_buf) | |
932 | copy32(p->tx_dma_page, tx_buf, l / 4); | |
8051effc | 933 | |
b0d0ce8b | 934 | ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); |
279d2378 | 935 | if (ret == -EAGAIN) { |
5d8e614f GU |
936 | dev_warn_once(&p->pdev->dev, |
937 | "DMA not available, falling back to PIO\n"); | |
279d2378 GU |
938 | break; |
939 | } | |
b0d0ce8b GU |
940 | if (ret) |
941 | return ret; | |
942 | ||
943 | if (rx_buf) { | |
944 | copy32(rx_buf, p->rx_dma_page, l / 4); | |
945 | rx_buf += l; | |
946 | } | |
947 | if (tx_buf) | |
948 | tx_buf += l; | |
949 | ||
950 | len -= l; | |
951 | if (!len) | |
952 | return 0; | |
953 | } | |
8051effc | 954 | |
0312d591 | 955 | if (bits <= 8 && len > 15 && !(len & 3)) { |
9dabb3f3 GL |
956 | bits = 32; |
957 | swab = true; | |
958 | } else { | |
959 | swab = false; | |
960 | } | |
961 | ||
8051effc MD |
962 | /* setup bytes per word and fifo read/write functions */ |
963 | if (bits <= 8) { | |
964 | bytes_per_word = 1; | |
965 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
966 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
967 | } else if (bits <= 16) { | |
968 | bytes_per_word = 2; | |
0312d591 | 969 | if ((unsigned long)tx_buf & 0x01) |
8051effc MD |
970 | tx_fifo = sh_msiof_spi_write_fifo_16u; |
971 | else | |
972 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
973 | ||
0312d591 | 974 | if ((unsigned long)rx_buf & 0x01) |
8051effc MD |
975 | rx_fifo = sh_msiof_spi_read_fifo_16u; |
976 | else | |
977 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
978 | } else if (swab) { |
979 | bytes_per_word = 4; | |
0312d591 | 980 | if ((unsigned long)tx_buf & 0x03) |
9dabb3f3 GL |
981 | tx_fifo = sh_msiof_spi_write_fifo_s32u; |
982 | else | |
983 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
984 | ||
0312d591 | 985 | if ((unsigned long)rx_buf & 0x03) |
9dabb3f3 GL |
986 | rx_fifo = sh_msiof_spi_read_fifo_s32u; |
987 | else | |
988 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
989 | } else { |
990 | bytes_per_word = 4; | |
0312d591 | 991 | if ((unsigned long)tx_buf & 0x03) |
8051effc MD |
992 | tx_fifo = sh_msiof_spi_write_fifo_32u; |
993 | else | |
994 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
995 | ||
0312d591 | 996 | if ((unsigned long)rx_buf & 0x03) |
8051effc MD |
997 | rx_fifo = sh_msiof_spi_read_fifo_32u; |
998 | else | |
999 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
1000 | } | |
1001 | ||
8051effc | 1002 | /* transfer in fifo sized chunks */ |
0312d591 GU |
1003 | words = len / bytes_per_word; |
1004 | ||
1005 | while (words > 0) { | |
1006 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, | |
8051effc MD |
1007 | words, bits); |
1008 | if (n < 0) | |
75b82e23 | 1009 | return n; |
8051effc | 1010 | |
0312d591 GU |
1011 | if (tx_buf) |
1012 | tx_buf += n * bytes_per_word; | |
1013 | if (rx_buf) | |
1014 | rx_buf += n * bytes_per_word; | |
8051effc MD |
1015 | words -= n; |
1016 | } | |
1017 | ||
8051effc MD |
1018 | return 0; |
1019 | } | |
1020 | ||
50a7e23f GU |
1021 | static const struct sh_msiof_chipdata sh_data = { |
1022 | .tx_fifo_size = 64, | |
1023 | .rx_fifo_size = 64, | |
beb74bb0 | 1024 | .master_flags = 0, |
61a8dec5 GU |
1025 | .min_div = 1, |
1026 | }; | |
1027 | ||
1028 | static const struct sh_msiof_chipdata rcar_gen2_data = { | |
1029 | .tx_fifo_size = 64, | |
1030 | .rx_fifo_size = 64, | |
1031 | .master_flags = SPI_MASTER_MUST_TX, | |
1032 | .min_div = 1, | |
beb74bb0 GU |
1033 | }; |
1034 | ||
61a8dec5 | 1035 | static const struct sh_msiof_chipdata rcar_gen3_data = { |
beb74bb0 | 1036 | .tx_fifo_size = 64, |
fe78d0b7 | 1037 | .rx_fifo_size = 64, |
beb74bb0 | 1038 | .master_flags = SPI_MASTER_MUST_TX, |
61a8dec5 | 1039 | .min_div = 2, |
50a7e23f GU |
1040 | }; |
1041 | ||
1042 | static const struct of_device_id sh_msiof_match[] = { | |
50a7e23f | 1043 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, |
bdacfc7b FC |
1044 | { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, |
1045 | { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, | |
61a8dec5 GU |
1046 | { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, |
1047 | { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, | |
1048 | { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, | |
1049 | { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, | |
1050 | { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, | |
1051 | { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, | |
1052 | { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, | |
1053 | { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, | |
264c3e8d | 1054 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ |
50a7e23f GU |
1055 | {}, |
1056 | }; | |
1057 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
1058 | ||
cf9c86ef BH |
1059 | #ifdef CONFIG_OF |
1060 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
1061 | { | |
1062 | struct sh_msiof_spi_info *info; | |
1063 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 1064 | u32 num_cs = 1; |
cf9c86ef BH |
1065 | |
1066 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 1067 | if (!info) |
cf9c86ef | 1068 | return NULL; |
cf9c86ef | 1069 | |
cf9e4784 HN |
1070 | info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE |
1071 | : MSIOF_SPI_MASTER; | |
1072 | ||
cf9c86ef | 1073 | /* Parse the MSIOF properties */ |
cf9e4784 HN |
1074 | if (info->mode == MSIOF_SPI_MASTER) |
1075 | of_property_read_u32(np, "num-cs", &num_cs); | |
cf9c86ef BH |
1076 | of_property_read_u32(np, "renesas,tx-fifo-size", |
1077 | &info->tx_fifo_override); | |
1078 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
1079 | &info->rx_fifo_override); | |
3110628d YS |
1080 | of_property_read_u32(np, "renesas,dtdl", &info->dtdl); |
1081 | of_property_read_u32(np, "renesas,syncdl", &info->syncdl); | |
cf9c86ef BH |
1082 | |
1083 | info->num_chipselect = num_cs; | |
1084 | ||
1085 | return info; | |
1086 | } | |
1087 | #else | |
1088 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
1089 | { | |
1090 | return NULL; | |
1091 | } | |
1092 | #endif | |
1093 | ||
b0d0ce8b GU |
1094 | static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, |
1095 | enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) | |
1096 | { | |
1097 | dma_cap_mask_t mask; | |
1098 | struct dma_chan *chan; | |
1099 | struct dma_slave_config cfg; | |
1100 | int ret; | |
1101 | ||
1102 | dma_cap_zero(mask); | |
1103 | dma_cap_set(DMA_SLAVE, mask); | |
1104 | ||
a6be4de6 GU |
1105 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
1106 | (void *)(unsigned long)id, dev, | |
1107 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
b0d0ce8b | 1108 | if (!chan) { |
a6be4de6 | 1109 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
b0d0ce8b GU |
1110 | return NULL; |
1111 | } | |
1112 | ||
1113 | memset(&cfg, 0, sizeof(cfg)); | |
b0d0ce8b | 1114 | cfg.direction = dir; |
52fba2b8 | 1115 | if (dir == DMA_MEM_TO_DEV) { |
b0d0ce8b | 1116 | cfg.dst_addr = port_addr; |
52fba2b8 GU |
1117 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1118 | } else { | |
b0d0ce8b | 1119 | cfg.src_addr = port_addr; |
52fba2b8 GU |
1120 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1121 | } | |
b0d0ce8b GU |
1122 | |
1123 | ret = dmaengine_slave_config(chan, &cfg); | |
1124 | if (ret) { | |
1125 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
1126 | dma_release_channel(chan); | |
1127 | return NULL; | |
1128 | } | |
1129 | ||
1130 | return chan; | |
1131 | } | |
1132 | ||
1133 | static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) | |
1134 | { | |
1135 | struct platform_device *pdev = p->pdev; | |
1136 | struct device *dev = &pdev->dev; | |
1137 | const struct sh_msiof_spi_info *info = dev_get_platdata(dev); | |
a6be4de6 | 1138 | unsigned int dma_tx_id, dma_rx_id; |
b0d0ce8b GU |
1139 | const struct resource *res; |
1140 | struct spi_master *master; | |
5dabcf2f | 1141 | struct device *tx_dev, *rx_dev; |
b0d0ce8b | 1142 | |
a6be4de6 GU |
1143 | if (dev->of_node) { |
1144 | /* In the OF case we will get the slave IDs from the DT */ | |
1145 | dma_tx_id = 0; | |
1146 | dma_rx_id = 0; | |
1147 | } else if (info && info->dma_tx_id && info->dma_rx_id) { | |
1148 | dma_tx_id = info->dma_tx_id; | |
1149 | dma_rx_id = info->dma_rx_id; | |
1150 | } else { | |
1151 | /* The driver assumes no error */ | |
1152 | return 0; | |
1153 | } | |
b0d0ce8b GU |
1154 | |
1155 | /* The DMA engine uses the second register set, if present */ | |
1156 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1157 | if (!res) | |
1158 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1159 | ||
1160 | master = p->master; | |
1161 | master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, | |
a6be4de6 | 1162 | dma_tx_id, |
b0d0ce8b GU |
1163 | res->start + TFDR); |
1164 | if (!master->dma_tx) | |
1165 | return -ENODEV; | |
1166 | ||
1167 | master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, | |
a6be4de6 | 1168 | dma_rx_id, |
b0d0ce8b GU |
1169 | res->start + RFDR); |
1170 | if (!master->dma_rx) | |
1171 | goto free_tx_chan; | |
1172 | ||
1173 | p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1174 | if (!p->tx_dma_page) | |
1175 | goto free_rx_chan; | |
1176 | ||
1177 | p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1178 | if (!p->rx_dma_page) | |
1179 | goto free_tx_page; | |
1180 | ||
5dabcf2f GU |
1181 | tx_dev = master->dma_tx->device->dev; |
1182 | p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1183 | DMA_TO_DEVICE); |
5dabcf2f | 1184 | if (dma_mapping_error(tx_dev, p->tx_dma_addr)) |
b0d0ce8b GU |
1185 | goto free_rx_page; |
1186 | ||
5dabcf2f GU |
1187 | rx_dev = master->dma_rx->device->dev; |
1188 | p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1189 | DMA_FROM_DEVICE); |
5dabcf2f | 1190 | if (dma_mapping_error(rx_dev, p->rx_dma_addr)) |
b0d0ce8b GU |
1191 | goto unmap_tx_page; |
1192 | ||
1193 | dev_info(dev, "DMA available"); | |
1194 | return 0; | |
1195 | ||
1196 | unmap_tx_page: | |
5dabcf2f | 1197 | dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); |
b0d0ce8b GU |
1198 | free_rx_page: |
1199 | free_page((unsigned long)p->rx_dma_page); | |
1200 | free_tx_page: | |
1201 | free_page((unsigned long)p->tx_dma_page); | |
1202 | free_rx_chan: | |
1203 | dma_release_channel(master->dma_rx); | |
1204 | free_tx_chan: | |
1205 | dma_release_channel(master->dma_tx); | |
1206 | master->dma_tx = NULL; | |
1207 | return -ENODEV; | |
1208 | } | |
1209 | ||
1210 | static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) | |
1211 | { | |
1212 | struct spi_master *master = p->master; | |
b0d0ce8b GU |
1213 | |
1214 | if (!master->dma_tx) | |
1215 | return; | |
1216 | ||
5dabcf2f GU |
1217 | dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, |
1218 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1219 | dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, | |
1220 | PAGE_SIZE, DMA_TO_DEVICE); | |
b0d0ce8b GU |
1221 | free_page((unsigned long)p->rx_dma_page); |
1222 | free_page((unsigned long)p->tx_dma_page); | |
1223 | dma_release_channel(master->dma_rx); | |
1224 | dma_release_channel(master->dma_tx); | |
1225 | } | |
1226 | ||
8051effc MD |
1227 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
1228 | { | |
1229 | struct resource *r; | |
1230 | struct spi_master *master; | |
a6802cc0 | 1231 | const struct sh_msiof_chipdata *chipdata; |
cf9e4784 | 1232 | struct sh_msiof_spi_info *info; |
8051effc | 1233 | struct sh_msiof_spi_priv *p; |
8051effc MD |
1234 | int i; |
1235 | int ret; | |
1236 | ||
ecb1596a GU |
1237 | chipdata = of_device_get_match_data(&pdev->dev); |
1238 | if (chipdata) { | |
cf9e4784 | 1239 | info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f | 1240 | } else { |
a6802cc0 | 1241 | chipdata = (const void *)pdev->id_entry->driver_data; |
cf9e4784 | 1242 | info = dev_get_platdata(&pdev->dev); |
50a7e23f | 1243 | } |
cf9c86ef | 1244 | |
cf9e4784 | 1245 | if (!info) { |
cf9c86ef | 1246 | dev_err(&pdev->dev, "failed to obtain device info\n"); |
cf9e4784 | 1247 | return -ENXIO; |
cf9c86ef BH |
1248 | } |
1249 | ||
cf9e4784 HN |
1250 | if (info->mode == MSIOF_SPI_SLAVE) |
1251 | master = spi_alloc_slave(&pdev->dev, | |
1252 | sizeof(struct sh_msiof_spi_priv)); | |
1253 | else | |
1254 | master = spi_alloc_master(&pdev->dev, | |
1255 | sizeof(struct sh_msiof_spi_priv)); | |
1256 | if (master == NULL) | |
1257 | return -ENOMEM; | |
1258 | ||
1259 | p = spi_master_get_devdata(master); | |
1260 | ||
1261 | platform_set_drvdata(pdev, p); | |
1262 | p->master = master; | |
1263 | p->info = info; | |
61a8dec5 | 1264 | p->min_div = chipdata->min_div; |
cf9e4784 | 1265 | |
8051effc MD |
1266 | init_completion(&p->done); |
1267 | ||
b4dd05de | 1268 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 1269 | if (IS_ERR(p->clk)) { |
078b6ead | 1270 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
1271 | ret = PTR_ERR(p->clk); |
1272 | goto err1; | |
1273 | } | |
1274 | ||
8051effc | 1275 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
1276 | if (i < 0) { |
1277 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 1278 | ret = -ENOENT; |
b4dd05de | 1279 | goto err1; |
8051effc | 1280 | } |
b4dd05de LP |
1281 | |
1282 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1283 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
1284 | if (IS_ERR(p->mapbase)) { | |
1285 | ret = PTR_ERR(p->mapbase); | |
1286 | goto err1; | |
8051effc MD |
1287 | } |
1288 | ||
b4dd05de LP |
1289 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
1290 | dev_name(&pdev->dev), p); | |
8051effc MD |
1291 | if (ret) { |
1292 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 1293 | goto err1; |
8051effc MD |
1294 | } |
1295 | ||
1296 | p->pdev = pdev; | |
1297 | pm_runtime_enable(&pdev->dev); | |
1298 | ||
8051effc | 1299 | /* Platform data may override FIFO sizes */ |
a6802cc0 GU |
1300 | p->tx_fifo_size = chipdata->tx_fifo_size; |
1301 | p->rx_fifo_size = chipdata->rx_fifo_size; | |
8051effc MD |
1302 | if (p->info->tx_fifo_override) |
1303 | p->tx_fifo_size = p->info->tx_fifo_override; | |
1304 | if (p->info->rx_fifo_override) | |
1305 | p->rx_fifo_size = p->info->rx_fifo_override; | |
1306 | ||
1bd6363b | 1307 | /* init master code */ |
8051effc MD |
1308 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1309 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
a6802cc0 | 1310 | master->flags = chipdata->master_flags; |
8051effc | 1311 | master->bus_num = pdev->id; |
f7c05e83 | 1312 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 1313 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 1314 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 1315 | master->prepare_message = sh_msiof_prepare_message; |
cf9e4784 | 1316 | master->slave_abort = sh_msiof_slave_abort; |
2416289c | 1317 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 1318 | master->auto_runtime_pm = true; |
1bd6363b | 1319 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 1320 | |
b0d0ce8b GU |
1321 | ret = sh_msiof_request_dma(p); |
1322 | if (ret < 0) | |
1323 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
1324 | ||
1bd6363b GU |
1325 | ret = devm_spi_register_master(&pdev->dev, master); |
1326 | if (ret < 0) { | |
1327 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
1328 | goto err2; | |
1329 | } | |
8051effc | 1330 | |
1bd6363b | 1331 | return 0; |
8051effc | 1332 | |
1bd6363b | 1333 | err2: |
b0d0ce8b | 1334 | sh_msiof_release_dma(p); |
8051effc | 1335 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
1336 | err1: |
1337 | spi_master_put(master); | |
8051effc MD |
1338 | return ret; |
1339 | } | |
1340 | ||
1341 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
1342 | { | |
b0d0ce8b GU |
1343 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); |
1344 | ||
1345 | sh_msiof_release_dma(p); | |
1bd6363b | 1346 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 1347 | return 0; |
8051effc MD |
1348 | } |
1349 | ||
3789c852 | 1350 | static const struct platform_device_id spi_driver_ids[] = { |
50a7e23f | 1351 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, |
cf9c86ef BH |
1352 | {}, |
1353 | }; | |
50a7e23f | 1354 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 1355 | |
8051effc MD |
1356 | static struct platform_driver sh_msiof_spi_drv = { |
1357 | .probe = sh_msiof_spi_probe, | |
1358 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 1359 | .id_table = spi_driver_ids, |
8051effc MD |
1360 | .driver = { |
1361 | .name = "spi_sh_msiof", | |
691ee4ed | 1362 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
1363 | }, |
1364 | }; | |
940ab889 | 1365 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
1366 | |
1367 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
1368 | MODULE_AUTHOR("Magnus Damm"); | |
1369 | MODULE_LICENSE("GPL v2"); | |
1370 | MODULE_ALIAS("platform:spi_sh_msiof"); |