Commit | Line | Data |
---|---|---|
8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
50a7e23f | 24 | #include <linux/of_device.h> |
8051effc | 25 | #include <linux/platform_device.h> |
8051effc | 26 | #include <linux/pm_runtime.h> |
8051effc | 27 | |
e2dbf5eb | 28 | #include <linux/spi/sh_msiof.h> |
8051effc | 29 | #include <linux/spi/spi.h> |
8051effc | 30 | |
8051effc MD |
31 | #include <asm/unaligned.h> |
32 | ||
50a7e23f GU |
33 | |
34 | struct sh_msiof_chipdata { | |
35 | u16 tx_fifo_size; | |
36 | u16 rx_fifo_size; | |
beb74bb0 | 37 | u16 master_flags; |
50a7e23f GU |
38 | }; |
39 | ||
8051effc | 40 | struct sh_msiof_spi_priv { |
8051effc MD |
41 | void __iomem *mapbase; |
42 | struct clk *clk; | |
43 | struct platform_device *pdev; | |
50a7e23f | 44 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
45 | struct sh_msiof_spi_info *info; |
46 | struct completion done; | |
8051effc MD |
47 | int tx_fifo_size; |
48 | int rx_fifo_size; | |
49 | }; | |
50 | ||
01cfef57 GU |
51 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
52 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
53 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
54 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
55 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
56 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
57 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
58 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
59 | #define CTR 0x28 /* Control Register */ | |
60 | #define FCTR 0x30 /* FIFO Control Register */ | |
61 | #define STR 0x40 /* Status Register */ | |
62 | #define IER 0x44 /* Interrupt Enable Register */ | |
63 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
64 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
65 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
66 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
67 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
68 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
69 | ||
70 | /* TMDR1 and RMDR1 */ | |
71 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
72 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
73 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
74 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
75 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
76 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
77 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
78 | #define MDR1_FLD_SHIFT 2 | |
79 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
80 | /* TMDR1 */ | |
81 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
82 | ||
83 | /* TMDR2 and RMDR2 */ | |
84 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
85 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
86 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
87 | ||
88 | /* TSCR and RSCR */ | |
89 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
90 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
91 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
92 | #define SCR_BRDV_DIV_2 0x0000 | |
93 | #define SCR_BRDV_DIV_4 0x0001 | |
94 | #define SCR_BRDV_DIV_8 0x0002 | |
95 | #define SCR_BRDV_DIV_16 0x0003 | |
96 | #define SCR_BRDV_DIV_32 0x0004 | |
97 | #define SCR_BRDV_DIV_1 0x0007 | |
98 | ||
99 | /* CTR */ | |
100 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
101 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
102 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
103 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
104 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
105 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
106 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
107 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
108 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
109 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
110 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
111 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
112 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
113 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
114 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
115 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
116 | ||
117 | /* STR and IER */ | |
118 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ | |
119 | #define STR_REOF 0x00000080 /* Frame Reception End */ | |
120 | ||
121 | ||
e2dbf5eb | 122 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
123 | { |
124 | switch (reg_offs) { | |
125 | case TSCR: | |
126 | case RSCR: | |
127 | return ioread16(p->mapbase + reg_offs); | |
128 | default: | |
129 | return ioread32(p->mapbase + reg_offs); | |
130 | } | |
131 | } | |
132 | ||
133 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 134 | u32 value) |
8051effc MD |
135 | { |
136 | switch (reg_offs) { | |
137 | case TSCR: | |
138 | case RSCR: | |
139 | iowrite16(value, p->mapbase + reg_offs); | |
140 | break; | |
141 | default: | |
142 | iowrite32(value, p->mapbase + reg_offs); | |
143 | break; | |
144 | } | |
145 | } | |
146 | ||
147 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 148 | u32 clr, u32 set) |
8051effc | 149 | { |
e2dbf5eb GL |
150 | u32 mask = clr | set; |
151 | u32 data; | |
8051effc MD |
152 | int k; |
153 | ||
154 | data = sh_msiof_read(p, CTR); | |
155 | data &= ~clr; | |
156 | data |= set; | |
157 | sh_msiof_write(p, CTR, data); | |
158 | ||
159 | for (k = 100; k > 0; k--) { | |
160 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
161 | break; | |
162 | ||
163 | udelay(10); | |
164 | } | |
165 | ||
166 | return k > 0 ? 0 : -ETIMEDOUT; | |
167 | } | |
168 | ||
169 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
170 | { | |
171 | struct sh_msiof_spi_priv *p = data; | |
172 | ||
173 | /* just disable the interrupt and wake up */ | |
174 | sh_msiof_write(p, IER, 0); | |
175 | complete(&p->done); | |
176 | ||
177 | return IRQ_HANDLED; | |
178 | } | |
179 | ||
180 | static struct { | |
181 | unsigned short div; | |
182 | unsigned short scr; | |
183 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
184 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
185 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
186 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
187 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
188 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
189 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
190 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
191 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
192 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
193 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
194 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
195 | }; |
196 | ||
197 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 198 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
199 | { |
200 | unsigned long div = 1024; | |
201 | size_t k; | |
202 | ||
203 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 204 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
205 | |
206 | /* TODO: make more fine grained */ | |
207 | ||
208 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
209 | if (sh_msiof_spi_clk_table[k].div >= div) | |
210 | break; | |
211 | } | |
212 | ||
213 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
214 | ||
215 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
216 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
217 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
218 | } |
219 | ||
220 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 221 | u32 cpol, u32 cpha, |
50a77998 | 222 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 223 | { |
e2dbf5eb | 224 | u32 tmp; |
8051effc MD |
225 | int edge; |
226 | ||
227 | /* | |
e8708ef7 MP |
228 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
229 | * 0 0 10 10 1 1 | |
230 | * 0 1 10 10 0 0 | |
231 | * 1 0 11 11 0 0 | |
232 | * 1 1 11 11 1 1 | |
8051effc | 233 | */ |
8051effc | 234 | sh_msiof_write(p, FCTR, 0); |
50a77998 | 235 | |
01cfef57 GU |
236 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
237 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
238 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
239 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
240 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
241 | /* These bits are reserved if RX needs TX */ | |
242 | tmp &= ~0x0000ffff; | |
243 | } | |
01cfef57 | 244 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 245 | |
01cfef57 GU |
246 | tmp = 0; |
247 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
248 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 249 | |
e2dbf5eb | 250 | edge = cpol ^ !cpha; |
8051effc | 251 | |
01cfef57 GU |
252 | tmp |= edge << CTR_TEDG_SHIFT; |
253 | tmp |= edge << CTR_REDG_SHIFT; | |
254 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
255 | sh_msiof_write(p, CTR, tmp); |
256 | } | |
257 | ||
258 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
259 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 260 | u32 bits, u32 words) |
8051effc | 261 | { |
01cfef57 | 262 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 263 | |
beb74bb0 | 264 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
265 | sh_msiof_write(p, TMDR2, dr2); |
266 | else | |
01cfef57 | 267 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
268 | |
269 | if (rx_buf) | |
270 | sh_msiof_write(p, RMDR2, dr2); | |
271 | ||
272 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
273 | } | |
274 | ||
275 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
276 | { | |
277 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
278 | } | |
279 | ||
280 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
281 | const void *tx_buf, int words, int fs) | |
282 | { | |
e2dbf5eb | 283 | const u8 *buf_8 = tx_buf; |
8051effc MD |
284 | int k; |
285 | ||
286 | for (k = 0; k < words; k++) | |
287 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
288 | } | |
289 | ||
290 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
291 | const void *tx_buf, int words, int fs) | |
292 | { | |
e2dbf5eb | 293 | const u16 *buf_16 = tx_buf; |
8051effc MD |
294 | int k; |
295 | ||
296 | for (k = 0; k < words; k++) | |
297 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
298 | } | |
299 | ||
300 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
301 | const void *tx_buf, int words, int fs) | |
302 | { | |
e2dbf5eb | 303 | const u16 *buf_16 = tx_buf; |
8051effc MD |
304 | int k; |
305 | ||
306 | for (k = 0; k < words; k++) | |
307 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
308 | } | |
309 | ||
310 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
311 | const void *tx_buf, int words, int fs) | |
312 | { | |
e2dbf5eb | 313 | const u32 *buf_32 = tx_buf; |
8051effc MD |
314 | int k; |
315 | ||
316 | for (k = 0; k < words; k++) | |
317 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
318 | } | |
319 | ||
320 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
321 | const void *tx_buf, int words, int fs) | |
322 | { | |
e2dbf5eb | 323 | const u32 *buf_32 = tx_buf; |
8051effc MD |
324 | int k; |
325 | ||
326 | for (k = 0; k < words; k++) | |
327 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
328 | } | |
329 | ||
9dabb3f3 GL |
330 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
331 | const void *tx_buf, int words, int fs) | |
332 | { | |
333 | const u32 *buf_32 = tx_buf; | |
334 | int k; | |
335 | ||
336 | for (k = 0; k < words; k++) | |
337 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
338 | } | |
339 | ||
340 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
341 | const void *tx_buf, int words, int fs) | |
342 | { | |
343 | const u32 *buf_32 = tx_buf; | |
344 | int k; | |
345 | ||
346 | for (k = 0; k < words; k++) | |
347 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
348 | } | |
349 | ||
8051effc MD |
350 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
351 | void *rx_buf, int words, int fs) | |
352 | { | |
e2dbf5eb | 353 | u8 *buf_8 = rx_buf; |
8051effc MD |
354 | int k; |
355 | ||
356 | for (k = 0; k < words; k++) | |
357 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
358 | } | |
359 | ||
360 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
361 | void *rx_buf, int words, int fs) | |
362 | { | |
e2dbf5eb | 363 | u16 *buf_16 = rx_buf; |
8051effc MD |
364 | int k; |
365 | ||
366 | for (k = 0; k < words; k++) | |
367 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
368 | } | |
369 | ||
370 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
371 | void *rx_buf, int words, int fs) | |
372 | { | |
e2dbf5eb | 373 | u16 *buf_16 = rx_buf; |
8051effc MD |
374 | int k; |
375 | ||
376 | for (k = 0; k < words; k++) | |
377 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
378 | } | |
379 | ||
380 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
381 | void *rx_buf, int words, int fs) | |
382 | { | |
e2dbf5eb | 383 | u32 *buf_32 = rx_buf; |
8051effc MD |
384 | int k; |
385 | ||
386 | for (k = 0; k < words; k++) | |
387 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
388 | } | |
389 | ||
390 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
391 | void *rx_buf, int words, int fs) | |
392 | { | |
e2dbf5eb | 393 | u32 *buf_32 = rx_buf; |
8051effc MD |
394 | int k; |
395 | ||
396 | for (k = 0; k < words; k++) | |
397 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
398 | } | |
399 | ||
9dabb3f3 GL |
400 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
401 | void *rx_buf, int words, int fs) | |
402 | { | |
403 | u32 *buf_32 = rx_buf; | |
404 | int k; | |
405 | ||
406 | for (k = 0; k < words; k++) | |
407 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
408 | } | |
409 | ||
410 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
411 | void *rx_buf, int words, int fs) | |
412 | { | |
413 | u32 *buf_32 = rx_buf; | |
414 | int k; | |
415 | ||
416 | for (k = 0; k < words; k++) | |
417 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
418 | } | |
419 | ||
8051effc MD |
420 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
421 | { | |
422 | int bits; | |
423 | ||
424 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
425 | if (!bits) |
426 | bits = spi->bits_per_word; | |
8051effc MD |
427 | return bits; |
428 | } | |
429 | ||
6a85fc5a | 430 | static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) |
8051effc | 431 | { |
6a85fc5a | 432 | u32 hz; |
8051effc MD |
433 | |
434 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
435 | if (!hz) |
436 | hz = spi->max_speed_hz; | |
8051effc MD |
437 | return hz; |
438 | } | |
439 | ||
8d19534a GU |
440 | static int sh_msiof_spi_setup(struct spi_device *spi) |
441 | { | |
442 | struct device_node *np = spi->master->dev.of_node; | |
c833ff73 | 443 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8d19534a GU |
444 | |
445 | if (!np) { | |
446 | /* | |
447 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
448 | * if any. otherwise let HW control CS | |
449 | */ | |
450 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
451 | } | |
452 | ||
c833ff73 GU |
453 | /* Configure pins before deasserting CS */ |
454 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
455 | !!(spi->mode & SPI_CPHA), | |
456 | !!(spi->mode & SPI_3WIRE), | |
457 | !!(spi->mode & SPI_LSB_FIRST), | |
458 | !!(spi->mode & SPI_CS_HIGH)); | |
459 | ||
1bd6363b GU |
460 | if (spi->cs_gpio >= 0) |
461 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
462 | ||
463 | return 0; | |
8d19534a GU |
464 | } |
465 | ||
c833ff73 GU |
466 | static int sh_msiof_prepare_message(struct spi_master *master, |
467 | struct spi_message *msg) | |
468 | { | |
469 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
470 | const struct spi_device *spi = msg->spi; | |
471 | ||
472 | pm_runtime_get_sync(&p->pdev->dev); | |
473 | clk_enable(p->clk); | |
474 | ||
475 | /* Configure pins before asserting CS */ | |
476 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
477 | !!(spi->mode & SPI_CPHA), | |
478 | !!(spi->mode & SPI_3WIRE), | |
479 | !!(spi->mode & SPI_LSB_FIRST), | |
480 | !!(spi->mode & SPI_CS_HIGH)); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int sh_msiof_unprepare_message(struct spi_master *master, | |
485 | struct spi_message *msg) | |
486 | { | |
487 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
488 | ||
489 | clk_disable(p->clk); | |
490 | pm_runtime_put(&p->pdev->dev); | |
491 | return 0; | |
492 | } | |
493 | ||
8051effc MD |
494 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
495 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
496 | const void *, int, int), | |
497 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
498 | void *, int, int), | |
499 | const void *tx_buf, void *rx_buf, | |
500 | int words, int bits) | |
501 | { | |
502 | int fifo_shift; | |
503 | int ret; | |
504 | ||
505 | /* limit maximum word transfer to rx/tx fifo size */ | |
506 | if (tx_buf) | |
507 | words = min_t(int, words, p->tx_fifo_size); | |
508 | if (rx_buf) | |
509 | words = min_t(int, words, p->rx_fifo_size); | |
510 | ||
511 | /* the fifo contents need shifting */ | |
512 | fifo_shift = 32 - bits; | |
513 | ||
514 | /* setup msiof transfer mode registers */ | |
515 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
516 | ||
517 | /* write tx fifo */ | |
518 | if (tx_buf) | |
519 | tx_fifo(p, tx_buf, words, fifo_shift); | |
520 | ||
521 | /* setup clock and rx/tx signals */ | |
522 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
523 | if (rx_buf) | |
524 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
525 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
526 | ||
527 | /* start by setting frame bit */ | |
16735d02 | 528 | reinit_completion(&p->done); |
8051effc MD |
529 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
530 | if (ret) { | |
531 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
532 | goto err; | |
533 | } | |
534 | ||
535 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
536 | wait_for_completion(&p->done); | |
537 | ||
538 | /* read rx fifo */ | |
539 | if (rx_buf) | |
540 | rx_fifo(p, rx_buf, words, fifo_shift); | |
541 | ||
542 | /* clear status bits */ | |
543 | sh_msiof_reset_str(p); | |
544 | ||
a669c11a | 545 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
546 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
547 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
548 | if (rx_buf) | |
549 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
550 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
551 | if (ret) { | |
552 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
553 | goto err; | |
554 | } | |
555 | ||
556 | return words; | |
557 | ||
558 | err: | |
559 | sh_msiof_write(p, IER, 0); | |
560 | return ret; | |
561 | } | |
562 | ||
1bd6363b GU |
563 | static int sh_msiof_transfer_one(struct spi_master *master, |
564 | struct spi_device *spi, | |
565 | struct spi_transfer *t) | |
8051effc | 566 | { |
1bd6363b | 567 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
8051effc MD |
568 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
569 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
570 | int bits; | |
571 | int bytes_per_word; | |
572 | int bytes_done; | |
573 | int words; | |
574 | int n; | |
9dabb3f3 | 575 | bool swab; |
8051effc MD |
576 | |
577 | bits = sh_msiof_spi_bits(spi, t); | |
578 | ||
9dabb3f3 GL |
579 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
580 | bits = 32; | |
581 | swab = true; | |
582 | } else { | |
583 | swab = false; | |
584 | } | |
585 | ||
8051effc MD |
586 | /* setup bytes per word and fifo read/write functions */ |
587 | if (bits <= 8) { | |
588 | bytes_per_word = 1; | |
589 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
590 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
591 | } else if (bits <= 16) { | |
592 | bytes_per_word = 2; | |
593 | if ((unsigned long)t->tx_buf & 0x01) | |
594 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
595 | else | |
596 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
597 | ||
598 | if ((unsigned long)t->rx_buf & 0x01) | |
599 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
600 | else | |
601 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
602 | } else if (swab) { |
603 | bytes_per_word = 4; | |
604 | if ((unsigned long)t->tx_buf & 0x03) | |
605 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
606 | else | |
607 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
608 | ||
609 | if ((unsigned long)t->rx_buf & 0x03) | |
610 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
611 | else | |
612 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
613 | } else { |
614 | bytes_per_word = 4; | |
615 | if ((unsigned long)t->tx_buf & 0x03) | |
616 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
617 | else | |
618 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
619 | ||
620 | if ((unsigned long)t->rx_buf & 0x03) | |
621 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
622 | else | |
623 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
624 | } | |
625 | ||
626 | /* setup clocks (clock already enabled in chipselect()) */ | |
627 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
628 | sh_msiof_spi_hz(spi, t)); | |
629 | ||
630 | /* transfer in fifo sized chunks */ | |
631 | words = t->len / bytes_per_word; | |
632 | bytes_done = 0; | |
633 | ||
634 | while (bytes_done < t->len) { | |
8a6afb9a GL |
635 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
636 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 637 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
638 | tx_buf, |
639 | rx_buf, | |
8051effc MD |
640 | words, bits); |
641 | if (n < 0) | |
642 | break; | |
643 | ||
644 | bytes_done += n * bytes_per_word; | |
645 | words -= n; | |
646 | } | |
647 | ||
8051effc MD |
648 | return 0; |
649 | } | |
650 | ||
50a7e23f GU |
651 | static const struct sh_msiof_chipdata sh_data = { |
652 | .tx_fifo_size = 64, | |
653 | .rx_fifo_size = 64, | |
beb74bb0 GU |
654 | .master_flags = 0, |
655 | }; | |
656 | ||
657 | static const struct sh_msiof_chipdata r8a779x_data = { | |
658 | .tx_fifo_size = 64, | |
659 | .rx_fifo_size = 256, | |
660 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
661 | }; |
662 | ||
663 | static const struct of_device_id sh_msiof_match[] = { | |
664 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
665 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
666 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
667 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
668 | {}, |
669 | }; | |
670 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
671 | ||
cf9c86ef BH |
672 | #ifdef CONFIG_OF |
673 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
674 | { | |
675 | struct sh_msiof_spi_info *info; | |
676 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 677 | u32 num_cs = 1; |
cf9c86ef BH |
678 | |
679 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
680 | if (!info) { | |
681 | dev_err(dev, "failed to allocate setup data\n"); | |
682 | return NULL; | |
683 | } | |
684 | ||
685 | /* Parse the MSIOF properties */ | |
686 | of_property_read_u32(np, "num-cs", &num_cs); | |
687 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
688 | &info->tx_fifo_override); | |
689 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
690 | &info->rx_fifo_override); | |
691 | ||
692 | info->num_chipselect = num_cs; | |
693 | ||
694 | return info; | |
695 | } | |
696 | #else | |
697 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
698 | { | |
699 | return NULL; | |
700 | } | |
701 | #endif | |
702 | ||
8051effc MD |
703 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
704 | { | |
705 | struct resource *r; | |
706 | struct spi_master *master; | |
50a7e23f | 707 | const struct of_device_id *of_id; |
8051effc | 708 | struct sh_msiof_spi_priv *p; |
8051effc MD |
709 | int i; |
710 | int ret; | |
711 | ||
712 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
713 | if (master == NULL) { | |
714 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 715 | return -ENOMEM; |
8051effc MD |
716 | } |
717 | ||
718 | p = spi_master_get_devdata(master); | |
719 | ||
720 | platform_set_drvdata(pdev, p); | |
50a7e23f GU |
721 | |
722 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
723 | if (of_id) { | |
724 | p->chipdata = of_id->data; | |
cf9c86ef | 725 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
726 | } else { |
727 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 728 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 729 | } |
cf9c86ef BH |
730 | |
731 | if (!p->info) { | |
732 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
733 | ret = -ENXIO; | |
734 | goto err1; | |
735 | } | |
736 | ||
8051effc MD |
737 | init_completion(&p->done); |
738 | ||
b4dd05de | 739 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 740 | if (IS_ERR(p->clk)) { |
078b6ead | 741 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
742 | ret = PTR_ERR(p->clk); |
743 | goto err1; | |
744 | } | |
745 | ||
8051effc | 746 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
747 | if (i < 0) { |
748 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 749 | ret = -ENOENT; |
b4dd05de | 750 | goto err1; |
8051effc | 751 | } |
b4dd05de LP |
752 | |
753 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
754 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
755 | if (IS_ERR(p->mapbase)) { | |
756 | ret = PTR_ERR(p->mapbase); | |
757 | goto err1; | |
8051effc MD |
758 | } |
759 | ||
b4dd05de LP |
760 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
761 | dev_name(&pdev->dev), p); | |
8051effc MD |
762 | if (ret) { |
763 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 764 | goto err1; |
8051effc MD |
765 | } |
766 | ||
5c32d29f LP |
767 | ret = clk_prepare(p->clk); |
768 | if (ret < 0) { | |
769 | dev_err(&pdev->dev, "unable to prepare clock\n"); | |
770 | goto err1; | |
8051effc MD |
771 | } |
772 | ||
773 | p->pdev = pdev; | |
774 | pm_runtime_enable(&pdev->dev); | |
775 | ||
8051effc | 776 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
777 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
778 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
779 | if (p->info->tx_fifo_override) |
780 | p->tx_fifo_size = p->info->tx_fifo_override; | |
781 | if (p->info->rx_fifo_override) | |
782 | p->rx_fifo_size = p->info->rx_fifo_override; | |
783 | ||
1bd6363b | 784 | /* init master code */ |
8051effc MD |
785 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
786 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 787 | master->flags = p->chipdata->master_flags; |
8051effc | 788 | master->bus_num = pdev->id; |
f7c05e83 | 789 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 790 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 791 | master->setup = sh_msiof_spi_setup; |
c833ff73 GU |
792 | master->prepare_message = sh_msiof_prepare_message; |
793 | master->unprepare_message = sh_msiof_unprepare_message; | |
2416289c | 794 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
1bd6363b | 795 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 796 | |
1bd6363b GU |
797 | ret = devm_spi_register_master(&pdev->dev, master); |
798 | if (ret < 0) { | |
799 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
800 | goto err2; | |
801 | } | |
8051effc | 802 | |
1bd6363b | 803 | return 0; |
8051effc | 804 | |
1bd6363b | 805 | err2: |
8051effc | 806 | pm_runtime_disable(&pdev->dev); |
5c32d29f | 807 | clk_unprepare(p->clk); |
8051effc MD |
808 | err1: |
809 | spi_master_put(master); | |
8051effc MD |
810 | return ret; |
811 | } | |
812 | ||
813 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
814 | { | |
815 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
8051effc | 816 | |
1bd6363b GU |
817 | pm_runtime_disable(&pdev->dev); |
818 | clk_unprepare(p->clk); | |
819 | return 0; | |
8051effc MD |
820 | } |
821 | ||
50a7e23f GU |
822 | static struct platform_device_id spi_driver_ids[] = { |
823 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
824 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
825 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
826 | {}, |
827 | }; | |
50a7e23f | 828 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 829 | |
8051effc MD |
830 | static struct platform_driver sh_msiof_spi_drv = { |
831 | .probe = sh_msiof_spi_probe, | |
832 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 833 | .id_table = spi_driver_ids, |
8051effc MD |
834 | .driver = { |
835 | .name = "spi_sh_msiof", | |
836 | .owner = THIS_MODULE, | |
691ee4ed | 837 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
838 | }, |
839 | }; | |
940ab889 | 840 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
841 | |
842 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
843 | MODULE_AUTHOR("Magnus Damm"); | |
844 | MODULE_LICENSE("GPL v2"); | |
845 | MODULE_ALIAS("platform:spi_sh_msiof"); |