Commit | Line | Data |
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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
8051effc | 18 | #include <linux/interrupt.h> |
e2dbf5eb GL |
19 | #include <linux/io.h> |
20 | #include <linux/kernel.h> | |
d7614de4 | 21 | #include <linux/module.h> |
cf9c86ef | 22 | #include <linux/of.h> |
50a7e23f | 23 | #include <linux/of_device.h> |
8051effc | 24 | #include <linux/platform_device.h> |
8051effc | 25 | #include <linux/pm_runtime.h> |
8051effc | 26 | |
e2dbf5eb | 27 | #include <linux/spi/sh_msiof.h> |
8051effc | 28 | #include <linux/spi/spi.h> |
8051effc | 29 | |
8051effc MD |
30 | #include <asm/unaligned.h> |
31 | ||
50a7e23f GU |
32 | |
33 | struct sh_msiof_chipdata { | |
34 | u16 tx_fifo_size; | |
35 | u16 rx_fifo_size; | |
beb74bb0 | 36 | u16 master_flags; |
50a7e23f GU |
37 | }; |
38 | ||
8051effc | 39 | struct sh_msiof_spi_priv { |
8051effc MD |
40 | void __iomem *mapbase; |
41 | struct clk *clk; | |
42 | struct platform_device *pdev; | |
50a7e23f | 43 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
44 | struct sh_msiof_spi_info *info; |
45 | struct completion done; | |
8051effc MD |
46 | int tx_fifo_size; |
47 | int rx_fifo_size; | |
48 | }; | |
49 | ||
01cfef57 GU |
50 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
51 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
52 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
53 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
54 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
55 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
56 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
57 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
58 | #define CTR 0x28 /* Control Register */ | |
59 | #define FCTR 0x30 /* FIFO Control Register */ | |
60 | #define STR 0x40 /* Status Register */ | |
61 | #define IER 0x44 /* Interrupt Enable Register */ | |
62 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
63 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
64 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
65 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
66 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
67 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
68 | ||
69 | /* TMDR1 and RMDR1 */ | |
70 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
71 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
72 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
73 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
74 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
75 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
76 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
77 | #define MDR1_FLD_SHIFT 2 | |
78 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
79 | /* TMDR1 */ | |
80 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
81 | ||
82 | /* TMDR2 and RMDR2 */ | |
83 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
84 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
85 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
86 | ||
87 | /* TSCR and RSCR */ | |
88 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
89 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
90 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
91 | #define SCR_BRDV_DIV_2 0x0000 | |
92 | #define SCR_BRDV_DIV_4 0x0001 | |
93 | #define SCR_BRDV_DIV_8 0x0002 | |
94 | #define SCR_BRDV_DIV_16 0x0003 | |
95 | #define SCR_BRDV_DIV_32 0x0004 | |
96 | #define SCR_BRDV_DIV_1 0x0007 | |
97 | ||
98 | /* CTR */ | |
99 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
100 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
101 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
102 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
103 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
104 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
105 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
106 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
107 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
108 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
109 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
110 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
111 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
112 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
113 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
114 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
115 | ||
2e2b3687 GU |
116 | /* FCTR */ |
117 | #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ | |
118 | #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ | |
119 | #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ | |
120 | #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ | |
121 | #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ | |
122 | #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ | |
123 | #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ | |
124 | #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ | |
125 | #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ | |
126 | #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ | |
127 | #define FCTR_TFUA_SHIFT 20 | |
128 | #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) | |
129 | #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ | |
130 | #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ | |
131 | #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ | |
132 | #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ | |
133 | #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ | |
134 | #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ | |
135 | #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ | |
136 | #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ | |
137 | #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ | |
138 | #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ | |
139 | #define FCTR_RFUA_SHIFT 4 | |
140 | #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) | |
141 | ||
142 | /* STR */ | |
143 | #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ | |
144 | #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ | |
01cfef57 | 145 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ |
2e2b3687 GU |
146 | #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ |
147 | #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ | |
148 | #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ | |
149 | #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ | |
150 | #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ | |
01cfef57 | 151 | #define STR_REOF 0x00000080 /* Frame Reception End */ |
2e2b3687 GU |
152 | #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ |
153 | #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ | |
154 | #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ | |
155 | ||
156 | /* IER */ | |
157 | #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ | |
158 | #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ | |
159 | #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ | |
160 | #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ | |
161 | #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ | |
162 | #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ | |
163 | #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ | |
164 | #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ | |
165 | #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ | |
166 | #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ | |
167 | #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ | |
168 | #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ | |
169 | #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ | |
170 | #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ | |
01cfef57 | 171 | |
8051effc | 172 | |
e2dbf5eb | 173 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
174 | { |
175 | switch (reg_offs) { | |
176 | case TSCR: | |
177 | case RSCR: | |
178 | return ioread16(p->mapbase + reg_offs); | |
179 | default: | |
180 | return ioread32(p->mapbase + reg_offs); | |
181 | } | |
182 | } | |
183 | ||
184 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 185 | u32 value) |
8051effc MD |
186 | { |
187 | switch (reg_offs) { | |
188 | case TSCR: | |
189 | case RSCR: | |
190 | iowrite16(value, p->mapbase + reg_offs); | |
191 | break; | |
192 | default: | |
193 | iowrite32(value, p->mapbase + reg_offs); | |
194 | break; | |
195 | } | |
196 | } | |
197 | ||
198 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 199 | u32 clr, u32 set) |
8051effc | 200 | { |
e2dbf5eb GL |
201 | u32 mask = clr | set; |
202 | u32 data; | |
8051effc MD |
203 | int k; |
204 | ||
205 | data = sh_msiof_read(p, CTR); | |
206 | data &= ~clr; | |
207 | data |= set; | |
208 | sh_msiof_write(p, CTR, data); | |
209 | ||
210 | for (k = 100; k > 0; k--) { | |
211 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
212 | break; | |
213 | ||
214 | udelay(10); | |
215 | } | |
216 | ||
217 | return k > 0 ? 0 : -ETIMEDOUT; | |
218 | } | |
219 | ||
220 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
221 | { | |
222 | struct sh_msiof_spi_priv *p = data; | |
223 | ||
224 | /* just disable the interrupt and wake up */ | |
225 | sh_msiof_write(p, IER, 0); | |
226 | complete(&p->done); | |
227 | ||
228 | return IRQ_HANDLED; | |
229 | } | |
230 | ||
231 | static struct { | |
232 | unsigned short div; | |
233 | unsigned short scr; | |
234 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
235 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
236 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
237 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
238 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
239 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
240 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
241 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
242 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
243 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
244 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
245 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
246 | }; |
247 | ||
248 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 249 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
250 | { |
251 | unsigned long div = 1024; | |
252 | size_t k; | |
253 | ||
254 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 255 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
256 | |
257 | /* TODO: make more fine grained */ | |
258 | ||
259 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
260 | if (sh_msiof_spi_clk_table[k].div >= div) | |
261 | break; | |
262 | } | |
263 | ||
264 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
265 | ||
266 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
267 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
268 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
269 | } |
270 | ||
271 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 272 | u32 cpol, u32 cpha, |
50a77998 | 273 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 274 | { |
e2dbf5eb | 275 | u32 tmp; |
8051effc MD |
276 | int edge; |
277 | ||
278 | /* | |
e8708ef7 MP |
279 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
280 | * 0 0 10 10 1 1 | |
281 | * 0 1 10 10 0 0 | |
282 | * 1 0 11 11 0 0 | |
283 | * 1 1 11 11 1 1 | |
8051effc | 284 | */ |
8051effc | 285 | sh_msiof_write(p, FCTR, 0); |
50a77998 | 286 | |
01cfef57 GU |
287 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
288 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
289 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
290 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
291 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
292 | /* These bits are reserved if RX needs TX */ | |
293 | tmp &= ~0x0000ffff; | |
294 | } | |
01cfef57 | 295 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 296 | |
01cfef57 GU |
297 | tmp = 0; |
298 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
299 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 300 | |
e2dbf5eb | 301 | edge = cpol ^ !cpha; |
8051effc | 302 | |
01cfef57 GU |
303 | tmp |= edge << CTR_TEDG_SHIFT; |
304 | tmp |= edge << CTR_REDG_SHIFT; | |
305 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
306 | sh_msiof_write(p, CTR, tmp); |
307 | } | |
308 | ||
309 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
310 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 311 | u32 bits, u32 words) |
8051effc | 312 | { |
01cfef57 | 313 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 314 | |
beb74bb0 | 315 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
316 | sh_msiof_write(p, TMDR2, dr2); |
317 | else | |
01cfef57 | 318 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
319 | |
320 | if (rx_buf) | |
321 | sh_msiof_write(p, RMDR2, dr2); | |
322 | ||
323 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
324 | } | |
325 | ||
326 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
327 | { | |
328 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
329 | } | |
330 | ||
331 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
332 | const void *tx_buf, int words, int fs) | |
333 | { | |
e2dbf5eb | 334 | const u8 *buf_8 = tx_buf; |
8051effc MD |
335 | int k; |
336 | ||
337 | for (k = 0; k < words; k++) | |
338 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
339 | } | |
340 | ||
341 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
342 | const void *tx_buf, int words, int fs) | |
343 | { | |
e2dbf5eb | 344 | const u16 *buf_16 = tx_buf; |
8051effc MD |
345 | int k; |
346 | ||
347 | for (k = 0; k < words; k++) | |
348 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
349 | } | |
350 | ||
351 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
352 | const void *tx_buf, int words, int fs) | |
353 | { | |
e2dbf5eb | 354 | const u16 *buf_16 = tx_buf; |
8051effc MD |
355 | int k; |
356 | ||
357 | for (k = 0; k < words; k++) | |
358 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
359 | } | |
360 | ||
361 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
362 | const void *tx_buf, int words, int fs) | |
363 | { | |
e2dbf5eb | 364 | const u32 *buf_32 = tx_buf; |
8051effc MD |
365 | int k; |
366 | ||
367 | for (k = 0; k < words; k++) | |
368 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
369 | } | |
370 | ||
371 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
372 | const void *tx_buf, int words, int fs) | |
373 | { | |
e2dbf5eb | 374 | const u32 *buf_32 = tx_buf; |
8051effc MD |
375 | int k; |
376 | ||
377 | for (k = 0; k < words; k++) | |
378 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
379 | } | |
380 | ||
9dabb3f3 GL |
381 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
382 | const void *tx_buf, int words, int fs) | |
383 | { | |
384 | const u32 *buf_32 = tx_buf; | |
385 | int k; | |
386 | ||
387 | for (k = 0; k < words; k++) | |
388 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
389 | } | |
390 | ||
391 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
392 | const void *tx_buf, int words, int fs) | |
393 | { | |
394 | const u32 *buf_32 = tx_buf; | |
395 | int k; | |
396 | ||
397 | for (k = 0; k < words; k++) | |
398 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
399 | } | |
400 | ||
8051effc MD |
401 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
402 | void *rx_buf, int words, int fs) | |
403 | { | |
e2dbf5eb | 404 | u8 *buf_8 = rx_buf; |
8051effc MD |
405 | int k; |
406 | ||
407 | for (k = 0; k < words; k++) | |
408 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
409 | } | |
410 | ||
411 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
412 | void *rx_buf, int words, int fs) | |
413 | { | |
e2dbf5eb | 414 | u16 *buf_16 = rx_buf; |
8051effc MD |
415 | int k; |
416 | ||
417 | for (k = 0; k < words; k++) | |
418 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
419 | } | |
420 | ||
421 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
422 | void *rx_buf, int words, int fs) | |
423 | { | |
e2dbf5eb | 424 | u16 *buf_16 = rx_buf; |
8051effc MD |
425 | int k; |
426 | ||
427 | for (k = 0; k < words; k++) | |
428 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
429 | } | |
430 | ||
431 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
432 | void *rx_buf, int words, int fs) | |
433 | { | |
e2dbf5eb | 434 | u32 *buf_32 = rx_buf; |
8051effc MD |
435 | int k; |
436 | ||
437 | for (k = 0; k < words; k++) | |
438 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
439 | } | |
440 | ||
441 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
442 | void *rx_buf, int words, int fs) | |
443 | { | |
e2dbf5eb | 444 | u32 *buf_32 = rx_buf; |
8051effc MD |
445 | int k; |
446 | ||
447 | for (k = 0; k < words; k++) | |
448 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
449 | } | |
450 | ||
9dabb3f3 GL |
451 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
452 | void *rx_buf, int words, int fs) | |
453 | { | |
454 | u32 *buf_32 = rx_buf; | |
455 | int k; | |
456 | ||
457 | for (k = 0; k < words; k++) | |
458 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
459 | } | |
460 | ||
461 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
462 | void *rx_buf, int words, int fs) | |
463 | { | |
464 | u32 *buf_32 = rx_buf; | |
465 | int k; | |
466 | ||
467 | for (k = 0; k < words; k++) | |
468 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
469 | } | |
470 | ||
8d19534a | 471 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 472 | { |
8d19534a | 473 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 474 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8051effc | 475 | |
8d19534a GU |
476 | if (!np) { |
477 | /* | |
478 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
479 | * if any. otherwise let HW control CS | |
480 | */ | |
481 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
482 | } | |
8051effc | 483 | |
c833ff73 GU |
484 | /* Configure pins before deasserting CS */ |
485 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
486 | !!(spi->mode & SPI_CPHA), | |
487 | !!(spi->mode & SPI_3WIRE), | |
488 | !!(spi->mode & SPI_LSB_FIRST), | |
489 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc | 490 | |
1bd6363b GU |
491 | if (spi->cs_gpio >= 0) |
492 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
8051effc | 493 | |
1bd6363b | 494 | return 0; |
8051effc MD |
495 | } |
496 | ||
c833ff73 GU |
497 | static int sh_msiof_prepare_message(struct spi_master *master, |
498 | struct spi_message *msg) | |
8051effc | 499 | { |
c833ff73 GU |
500 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
501 | const struct spi_device *spi = msg->spi; | |
8051effc | 502 | |
c833ff73 GU |
503 | /* Configure pins before asserting CS */ |
504 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
505 | !!(spi->mode & SPI_CPHA), | |
506 | !!(spi->mode & SPI_3WIRE), | |
507 | !!(spi->mode & SPI_LSB_FIRST), | |
508 | !!(spi->mode & SPI_CS_HIGH)); | |
509 | return 0; | |
8051effc MD |
510 | } |
511 | ||
76c02e71 GU |
512 | static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) |
513 | { | |
514 | int ret; | |
515 | ||
516 | /* setup clock and rx/tx signals */ | |
517 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
518 | if (rx_buf && !ret) | |
519 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
520 | if (!ret) | |
521 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
522 | ||
523 | /* start by setting frame bit */ | |
524 | if (!ret) | |
525 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); | |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
530 | static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) | |
531 | { | |
532 | int ret; | |
533 | ||
534 | /* shut down frame, rx/tx and clock signals */ | |
535 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
536 | if (!ret) | |
537 | ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
538 | if (rx_buf && !ret) | |
539 | ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
540 | if (!ret) | |
541 | ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
542 | ||
543 | return ret; | |
544 | } | |
545 | ||
8051effc MD |
546 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
547 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
548 | const void *, int, int), | |
549 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
550 | void *, int, int), | |
551 | const void *tx_buf, void *rx_buf, | |
552 | int words, int bits) | |
553 | { | |
554 | int fifo_shift; | |
555 | int ret; | |
556 | ||
557 | /* limit maximum word transfer to rx/tx fifo size */ | |
558 | if (tx_buf) | |
559 | words = min_t(int, words, p->tx_fifo_size); | |
560 | if (rx_buf) | |
561 | words = min_t(int, words, p->rx_fifo_size); | |
562 | ||
563 | /* the fifo contents need shifting */ | |
564 | fifo_shift = 32 - bits; | |
565 | ||
566 | /* setup msiof transfer mode registers */ | |
567 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
568 | ||
569 | /* write tx fifo */ | |
570 | if (tx_buf) | |
571 | tx_fifo(p, tx_buf, words, fifo_shift); | |
572 | ||
16735d02 | 573 | reinit_completion(&p->done); |
76c02e71 GU |
574 | |
575 | ret = sh_msiof_spi_start(p, rx_buf); | |
8051effc MD |
576 | if (ret) { |
577 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
75b82e23 | 578 | goto stop_ier; |
8051effc MD |
579 | } |
580 | ||
581 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
75b82e23 GU |
582 | ret = wait_for_completion_timeout(&p->done, HZ); |
583 | if (!ret) { | |
584 | dev_err(&p->pdev->dev, "PIO timeout\n"); | |
585 | ret = -ETIMEDOUT; | |
586 | goto stop_reset; | |
587 | } | |
8051effc MD |
588 | |
589 | /* read rx fifo */ | |
590 | if (rx_buf) | |
591 | rx_fifo(p, rx_buf, words, fifo_shift); | |
592 | ||
593 | /* clear status bits */ | |
594 | sh_msiof_reset_str(p); | |
595 | ||
76c02e71 | 596 | ret = sh_msiof_spi_stop(p, rx_buf); |
8051effc MD |
597 | if (ret) { |
598 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
75b82e23 | 599 | return ret; |
8051effc MD |
600 | } |
601 | ||
602 | return words; | |
603 | ||
75b82e23 GU |
604 | stop_reset: |
605 | sh_msiof_reset_str(p); | |
606 | sh_msiof_spi_stop(p, rx_buf); | |
607 | stop_ier: | |
8051effc MD |
608 | sh_msiof_write(p, IER, 0); |
609 | return ret; | |
610 | } | |
611 | ||
1bd6363b GU |
612 | static int sh_msiof_transfer_one(struct spi_master *master, |
613 | struct spi_device *spi, | |
614 | struct spi_transfer *t) | |
8051effc | 615 | { |
1bd6363b | 616 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
8051effc MD |
617 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
618 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
0312d591 GU |
619 | const void *tx_buf = t->tx_buf; |
620 | void *rx_buf = t->rx_buf; | |
621 | unsigned int len = t->len; | |
622 | unsigned int bits = t->bits_per_word; | |
623 | unsigned int bytes_per_word; | |
624 | unsigned int words; | |
8051effc | 625 | int n; |
9dabb3f3 | 626 | bool swab; |
8051effc | 627 | |
8051effc | 628 | |
0312d591 | 629 | if (bits <= 8 && len > 15 && !(len & 3)) { |
9dabb3f3 GL |
630 | bits = 32; |
631 | swab = true; | |
632 | } else { | |
633 | swab = false; | |
634 | } | |
635 | ||
8051effc MD |
636 | /* setup bytes per word and fifo read/write functions */ |
637 | if (bits <= 8) { | |
638 | bytes_per_word = 1; | |
639 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
640 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
641 | } else if (bits <= 16) { | |
642 | bytes_per_word = 2; | |
0312d591 | 643 | if ((unsigned long)tx_buf & 0x01) |
8051effc MD |
644 | tx_fifo = sh_msiof_spi_write_fifo_16u; |
645 | else | |
646 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
647 | ||
0312d591 | 648 | if ((unsigned long)rx_buf & 0x01) |
8051effc MD |
649 | rx_fifo = sh_msiof_spi_read_fifo_16u; |
650 | else | |
651 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
652 | } else if (swab) { |
653 | bytes_per_word = 4; | |
0312d591 | 654 | if ((unsigned long)tx_buf & 0x03) |
9dabb3f3 GL |
655 | tx_fifo = sh_msiof_spi_write_fifo_s32u; |
656 | else | |
657 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
658 | ||
0312d591 | 659 | if ((unsigned long)rx_buf & 0x03) |
9dabb3f3 GL |
660 | rx_fifo = sh_msiof_spi_read_fifo_s32u; |
661 | else | |
662 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
663 | } else { |
664 | bytes_per_word = 4; | |
0312d591 | 665 | if ((unsigned long)tx_buf & 0x03) |
8051effc MD |
666 | tx_fifo = sh_msiof_spi_write_fifo_32u; |
667 | else | |
668 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
669 | ||
0312d591 | 670 | if ((unsigned long)rx_buf & 0x03) |
8051effc MD |
671 | rx_fifo = sh_msiof_spi_read_fifo_32u; |
672 | else | |
673 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
674 | } | |
675 | ||
676 | /* setup clocks (clock already enabled in chipselect()) */ | |
b1415860 | 677 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); |
8051effc MD |
678 | |
679 | /* transfer in fifo sized chunks */ | |
0312d591 GU |
680 | words = len / bytes_per_word; |
681 | ||
682 | while (words > 0) { | |
683 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, | |
8051effc MD |
684 | words, bits); |
685 | if (n < 0) | |
75b82e23 | 686 | return n; |
8051effc | 687 | |
0312d591 GU |
688 | if (tx_buf) |
689 | tx_buf += n * bytes_per_word; | |
690 | if (rx_buf) | |
691 | rx_buf += n * bytes_per_word; | |
8051effc MD |
692 | words -= n; |
693 | } | |
694 | ||
8051effc MD |
695 | return 0; |
696 | } | |
697 | ||
50a7e23f GU |
698 | static const struct sh_msiof_chipdata sh_data = { |
699 | .tx_fifo_size = 64, | |
700 | .rx_fifo_size = 64, | |
beb74bb0 GU |
701 | .master_flags = 0, |
702 | }; | |
703 | ||
704 | static const struct sh_msiof_chipdata r8a779x_data = { | |
705 | .tx_fifo_size = 64, | |
706 | .rx_fifo_size = 256, | |
707 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
708 | }; |
709 | ||
710 | static const struct of_device_id sh_msiof_match[] = { | |
711 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
712 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
713 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
714 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
715 | {}, |
716 | }; | |
717 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
718 | ||
cf9c86ef BH |
719 | #ifdef CONFIG_OF |
720 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
721 | { | |
722 | struct sh_msiof_spi_info *info; | |
723 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 724 | u32 num_cs = 1; |
cf9c86ef BH |
725 | |
726 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 727 | if (!info) |
cf9c86ef | 728 | return NULL; |
cf9c86ef BH |
729 | |
730 | /* Parse the MSIOF properties */ | |
731 | of_property_read_u32(np, "num-cs", &num_cs); | |
732 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
733 | &info->tx_fifo_override); | |
734 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
735 | &info->rx_fifo_override); | |
736 | ||
737 | info->num_chipselect = num_cs; | |
738 | ||
739 | return info; | |
740 | } | |
741 | #else | |
742 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
743 | { | |
744 | return NULL; | |
745 | } | |
746 | #endif | |
747 | ||
8051effc MD |
748 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
749 | { | |
750 | struct resource *r; | |
751 | struct spi_master *master; | |
50a7e23f | 752 | const struct of_device_id *of_id; |
8051effc | 753 | struct sh_msiof_spi_priv *p; |
8051effc MD |
754 | int i; |
755 | int ret; | |
756 | ||
757 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
758 | if (master == NULL) { | |
759 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 760 | return -ENOMEM; |
8051effc MD |
761 | } |
762 | ||
763 | p = spi_master_get_devdata(master); | |
764 | ||
765 | platform_set_drvdata(pdev, p); | |
50a7e23f GU |
766 | |
767 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
768 | if (of_id) { | |
769 | p->chipdata = of_id->data; | |
cf9c86ef | 770 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
771 | } else { |
772 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 773 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 774 | } |
cf9c86ef BH |
775 | |
776 | if (!p->info) { | |
777 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
778 | ret = -ENXIO; | |
779 | goto err1; | |
780 | } | |
781 | ||
8051effc MD |
782 | init_completion(&p->done); |
783 | ||
b4dd05de | 784 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 785 | if (IS_ERR(p->clk)) { |
078b6ead | 786 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
787 | ret = PTR_ERR(p->clk); |
788 | goto err1; | |
789 | } | |
790 | ||
8051effc | 791 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
792 | if (i < 0) { |
793 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 794 | ret = -ENOENT; |
b4dd05de | 795 | goto err1; |
8051effc | 796 | } |
b4dd05de LP |
797 | |
798 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
799 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
800 | if (IS_ERR(p->mapbase)) { | |
801 | ret = PTR_ERR(p->mapbase); | |
802 | goto err1; | |
8051effc MD |
803 | } |
804 | ||
b4dd05de LP |
805 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
806 | dev_name(&pdev->dev), p); | |
8051effc MD |
807 | if (ret) { |
808 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 809 | goto err1; |
8051effc MD |
810 | } |
811 | ||
812 | p->pdev = pdev; | |
813 | pm_runtime_enable(&pdev->dev); | |
814 | ||
8051effc | 815 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
816 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
817 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
818 | if (p->info->tx_fifo_override) |
819 | p->tx_fifo_size = p->info->tx_fifo_override; | |
820 | if (p->info->rx_fifo_override) | |
821 | p->rx_fifo_size = p->info->rx_fifo_override; | |
822 | ||
1bd6363b | 823 | /* init master code */ |
8051effc MD |
824 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
825 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 826 | master->flags = p->chipdata->master_flags; |
8051effc | 827 | master->bus_num = pdev->id; |
f7c05e83 | 828 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 829 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 830 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 831 | master->prepare_message = sh_msiof_prepare_message; |
2416289c | 832 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 833 | master->auto_runtime_pm = true; |
1bd6363b | 834 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 835 | |
1bd6363b GU |
836 | ret = devm_spi_register_master(&pdev->dev, master); |
837 | if (ret < 0) { | |
838 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
839 | goto err2; | |
840 | } | |
8051effc | 841 | |
1bd6363b | 842 | return 0; |
8051effc | 843 | |
1bd6363b | 844 | err2: |
8051effc | 845 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
846 | err1: |
847 | spi_master_put(master); | |
8051effc MD |
848 | return ret; |
849 | } | |
850 | ||
851 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
852 | { | |
1bd6363b | 853 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 854 | return 0; |
8051effc MD |
855 | } |
856 | ||
50a7e23f GU |
857 | static struct platform_device_id spi_driver_ids[] = { |
858 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
859 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
860 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
861 | {}, |
862 | }; | |
50a7e23f | 863 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 864 | |
8051effc MD |
865 | static struct platform_driver sh_msiof_spi_drv = { |
866 | .probe = sh_msiof_spi_probe, | |
867 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 868 | .id_table = spi_driver_ids, |
8051effc MD |
869 | .driver = { |
870 | .name = "spi_sh_msiof", | |
871 | .owner = THIS_MODULE, | |
691ee4ed | 872 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
873 | }, |
874 | }; | |
940ab889 | 875 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
876 | |
877 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
878 | MODULE_AUTHOR("Magnus Damm"); | |
879 | MODULE_LICENSE("GPL v2"); | |
880 | MODULE_ALIAS("platform:spi_sh_msiof"); |