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d1c8bbd7 KM |
1 | /* |
2 | * SuperH HSPI bus driver | |
3 | * | |
4 | * Copyright (C) 2011 Kuninori Morimoto | |
5 | * | |
6 | * Based on spi-sh.c: | |
7 | * Based on pxa2xx_spi.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; version 2 of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
23 | * | |
24 | */ | |
49e599b8 KM |
25 | |
26 | #include <linux/clk.h> | |
d1c8bbd7 KM |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
29 | #include <linux/timer.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/list.h> | |
d1c8bbd7 KM |
32 | #include <linux/interrupt.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/pm_runtime.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/sh_hspi.h> | |
38 | ||
39 | #define SPCR 0x00 | |
40 | #define SPSR 0x04 | |
41 | #define SPSCR 0x08 | |
42 | #define SPTBR 0x0C | |
43 | #define SPRBR 0x10 | |
44 | #define SPCR2 0x14 | |
45 | ||
46 | /* SPSR */ | |
47 | #define RXFL (1 << 2) | |
48 | ||
d1c8bbd7 KM |
49 | struct hspi_priv { |
50 | void __iomem *addr; | |
51 | struct spi_master *master; | |
d1c8bbd7 | 52 | struct device *dev; |
49e599b8 | 53 | struct clk *clk; |
d1c8bbd7 KM |
54 | }; |
55 | ||
56 | /* | |
57 | * basic function | |
58 | */ | |
59 | static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) | |
60 | { | |
61 | iowrite32(val, hspi->addr + reg); | |
62 | } | |
63 | ||
64 | static u32 hspi_read(struct hspi_priv *hspi, int reg) | |
65 | { | |
66 | return ioread32(hspi->addr + reg); | |
67 | } | |
68 | ||
ce329305 PE |
69 | static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set) |
70 | { | |
71 | u32 val = hspi_read(hspi, reg); | |
72 | ||
73 | val &= ~mask; | |
74 | val |= set & mask; | |
75 | ||
76 | hspi_write(hspi, reg, val); | |
77 | } | |
78 | ||
d1c8bbd7 KM |
79 | /* |
80 | * transfer function | |
81 | */ | |
82 | static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) | |
83 | { | |
84 | int t = 256; | |
85 | ||
86 | while (t--) { | |
87 | if ((mask & hspi_read(hspi, SPSR)) == val) | |
88 | return 0; | |
89 | ||
bc2bfffc | 90 | udelay(10); |
d1c8bbd7 KM |
91 | } |
92 | ||
93 | dev_err(hspi->dev, "timeout\n"); | |
94 | return -ETIMEDOUT; | |
95 | } | |
96 | ||
ec139b67 KM |
97 | /* |
98 | * spi master function | |
99 | */ | |
d1c8bbd7 | 100 | |
ce329305 PE |
101 | #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0) |
102 | #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1) | |
103 | static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi) | |
104 | { | |
105 | hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6); | |
106 | } | |
107 | ||
49e599b8 KM |
108 | static void hspi_hw_setup(struct hspi_priv *hspi, |
109 | struct spi_message *msg, | |
110 | struct spi_transfer *t) | |
111 | { | |
112 | struct spi_device *spi = msg->spi; | |
113 | struct device *dev = hspi->dev; | |
49e599b8 KM |
114 | u32 spcr, idiv_clk; |
115 | u32 rate, best_rate, min, tmp; | |
116 | ||
49e599b8 KM |
117 | /* |
118 | * find best IDIV/CLKCx settings | |
119 | */ | |
120 | min = ~0; | |
121 | best_rate = 0; | |
122 | spcr = 0; | |
123 | for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) { | |
124 | rate = clk_get_rate(hspi->clk); | |
125 | ||
126 | /* IDIV calculation */ | |
127 | if (idiv_clk & (1 << 5)) | |
128 | rate /= 128; | |
129 | else | |
130 | rate /= 16; | |
131 | ||
132 | /* CLKCx calculation */ | |
a29c8ae7 | 133 | rate /= (((idiv_clk & 0x1F) + 1) * 2); |
49e599b8 KM |
134 | |
135 | /* save best settings */ | |
e428a420 | 136 | tmp = abs(t->speed_hz - rate); |
49e599b8 KM |
137 | if (tmp < min) { |
138 | min = tmp; | |
139 | spcr = idiv_clk; | |
140 | best_rate = rate; | |
141 | } | |
142 | } | |
143 | ||
144 | if (spi->mode & SPI_CPHA) | |
145 | spcr |= 1 << 7; | |
146 | if (spi->mode & SPI_CPOL) | |
147 | spcr |= 1 << 6; | |
148 | ||
e428a420 | 149 | dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate); |
49e599b8 KM |
150 | |
151 | hspi_write(hspi, SPCR, spcr); | |
152 | hspi_write(hspi, SPSR, 0x0); | |
ce329305 | 153 | hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */ |
49e599b8 KM |
154 | } |
155 | ||
ec139b67 KM |
156 | static int hspi_transfer_one_message(struct spi_master *master, |
157 | struct spi_message *msg) | |
158 | { | |
159 | struct hspi_priv *hspi = spi_master_get_devdata(master); | |
160 | struct spi_transfer *t; | |
bb9c5687 KM |
161 | u32 tx; |
162 | u32 rx; | |
163 | int ret, i; | |
ce329305 PE |
164 | unsigned int cs_change; |
165 | const int nsecs = 50; | |
d1c8bbd7 | 166 | |
ec139b67 | 167 | dev_dbg(hspi->dev, "%s\n", __func__); |
d1c8bbd7 | 168 | |
ce329305 | 169 | cs_change = 1; |
ec139b67 KM |
170 | ret = 0; |
171 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
ce329305 PE |
172 | |
173 | if (cs_change) { | |
174 | hspi_hw_setup(hspi, msg, t); | |
175 | hspi_hw_cs_enable(hspi); | |
176 | ndelay(nsecs); | |
177 | } | |
178 | cs_change = t->cs_change; | |
49e599b8 | 179 | |
bb9c5687 KM |
180 | for (i = 0; i < t->len; i++) { |
181 | ||
182 | /* wait remains */ | |
183 | ret = hspi_status_check_timeout(hspi, 0x1, 0); | |
ec139b67 | 184 | if (ret < 0) |
bb9c5687 KM |
185 | break; |
186 | ||
187 | tx = 0; | |
188 | if (t->tx_buf) | |
189 | tx = (u32)((u8 *)t->tx_buf)[i]; | |
190 | ||
191 | hspi_write(hspi, SPTBR, tx); | |
192 | ||
c6c07b4f | 193 | /* wait receive */ |
bb9c5687 | 194 | ret = hspi_status_check_timeout(hspi, 0x4, 0x4); |
ec139b67 | 195 | if (ret < 0) |
bb9c5687 KM |
196 | break; |
197 | ||
198 | rx = hspi_read(hspi, SPRBR); | |
199 | if (t->rx_buf) | |
200 | ((u8 *)t->rx_buf)[i] = (u8)rx; | |
201 | ||
d1c8bbd7 | 202 | } |
bb9c5687 | 203 | |
ec139b67 | 204 | msg->actual_length += t->len; |
ce329305 PE |
205 | |
206 | if (t->delay_usecs) | |
207 | udelay(t->delay_usecs); | |
208 | ||
209 | if (cs_change) { | |
210 | ndelay(nsecs); | |
211 | hspi_hw_cs_disable(hspi); | |
212 | ndelay(nsecs); | |
213 | } | |
d1c8bbd7 KM |
214 | } |
215 | ||
ec139b67 | 216 | msg->status = ret; |
ce329305 PE |
217 | if (!cs_change) { |
218 | ndelay(nsecs); | |
219 | hspi_hw_cs_disable(hspi); | |
220 | } | |
ec139b67 | 221 | spi_finalize_current_message(master); |
d1c8bbd7 | 222 | |
ec139b67 | 223 | return ret; |
d1c8bbd7 KM |
224 | } |
225 | ||
fd4a319b | 226 | static int hspi_probe(struct platform_device *pdev) |
d1c8bbd7 KM |
227 | { |
228 | struct resource *res; | |
229 | struct spi_master *master; | |
230 | struct hspi_priv *hspi; | |
49e599b8 | 231 | struct clk *clk; |
d1c8bbd7 KM |
232 | int ret; |
233 | ||
234 | /* get base addr */ | |
235 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
236 | if (!res) { | |
237 | dev_err(&pdev->dev, "invalid resource\n"); | |
238 | return -EINVAL; | |
239 | } | |
240 | ||
241 | master = spi_alloc_master(&pdev->dev, sizeof(*hspi)); | |
242 | if (!master) { | |
243 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
244 | return -ENOMEM; | |
245 | } | |
246 | ||
4a4dd7d8 | 247 | clk = clk_get(&pdev->dev, NULL); |
d3601e56 | 248 | if (IS_ERR(clk)) { |
4a4dd7d8 | 249 | dev_err(&pdev->dev, "couldn't get clock\n"); |
49e599b8 KM |
250 | ret = -EINVAL; |
251 | goto error0; | |
252 | } | |
253 | ||
d1c8bbd7 | 254 | hspi = spi_master_get_devdata(master); |
24b5a82c | 255 | platform_set_drvdata(pdev, hspi); |
d1c8bbd7 KM |
256 | |
257 | /* init hspi */ | |
258 | hspi->master = master; | |
259 | hspi->dev = &pdev->dev; | |
49e599b8 | 260 | hspi->clk = clk; |
d1c8bbd7 KM |
261 | hspi->addr = devm_ioremap(hspi->dev, |
262 | res->start, resource_size(res)); | |
263 | if (!hspi->addr) { | |
264 | dev_err(&pdev->dev, "ioremap error.\n"); | |
265 | ret = -ENOMEM; | |
266 | goto error1; | |
267 | } | |
d1c8bbd7 | 268 | |
268d7643 KM |
269 | pm_runtime_enable(&pdev->dev); |
270 | ||
d1c8bbd7 | 271 | master->bus_num = pdev->id; |
d1c8bbd7 | 272 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
e5f7825c | 273 | master->dev.of_node = pdev->dev.of_node; |
3e00a09d | 274 | master->auto_runtime_pm = true; |
ec139b67 | 275 | master->transfer_one_message = hspi_transfer_one_message; |
45221936 AL |
276 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
277 | ||
1c43f2ae | 278 | ret = devm_spi_register_master(&pdev->dev, master); |
d1c8bbd7 KM |
279 | if (ret < 0) { |
280 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
3abf0edd | 281 | goto error2; |
d1c8bbd7 KM |
282 | } |
283 | ||
d1c8bbd7 KM |
284 | return 0; |
285 | ||
3abf0edd GU |
286 | error2: |
287 | pm_runtime_disable(&pdev->dev); | |
d1c8bbd7 | 288 | error1: |
49e599b8 KM |
289 | clk_put(clk); |
290 | error0: | |
d1c8bbd7 KM |
291 | spi_master_put(master); |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
fd4a319b | 296 | static int hspi_remove(struct platform_device *pdev) |
d1c8bbd7 | 297 | { |
24b5a82c | 298 | struct hspi_priv *hspi = platform_get_drvdata(pdev); |
d1c8bbd7 KM |
299 | |
300 | pm_runtime_disable(&pdev->dev); | |
301 | ||
49e599b8 | 302 | clk_put(hspi->clk); |
d1c8bbd7 KM |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
e5f7825c KM |
307 | static struct of_device_id hspi_of_match[] = { |
308 | { .compatible = "renesas,hspi", }, | |
309 | { /* sentinel */ } | |
310 | }; | |
311 | MODULE_DEVICE_TABLE(of, hspi_of_match); | |
312 | ||
d1c8bbd7 KM |
313 | static struct platform_driver hspi_driver = { |
314 | .probe = hspi_probe, | |
fd4a319b | 315 | .remove = hspi_remove, |
d1c8bbd7 KM |
316 | .driver = { |
317 | .name = "sh-hspi", | |
318 | .owner = THIS_MODULE, | |
e5f7825c | 319 | .of_match_table = hspi_of_match, |
d1c8bbd7 KM |
320 | }, |
321 | }; | |
322 | module_platform_driver(hspi_driver); | |
323 | ||
324 | MODULE_DESCRIPTION("SuperH HSPI bus driver"); | |
325 | MODULE_LICENSE("GPL"); | |
326 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); | |
caedb997 | 327 | MODULE_ALIAS("platform:sh-hspi"); |