Commit | Line | Data |
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ca632f55 | 1 | /* |
230d42d4 JB |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
230d42d4 JB |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
c2573128 | 18 | #include <linux/interrupt.h> |
230d42d4 JB |
19 | #include <linux/delay.h> |
20 | #include <linux/clk.h> | |
21 | #include <linux/dma-mapping.h> | |
78843727 | 22 | #include <linux/dmaengine.h> |
230d42d4 | 23 | #include <linux/platform_device.h> |
b97b6621 | 24 | #include <linux/pm_runtime.h> |
230d42d4 | 25 | #include <linux/spi/spi.h> |
1c20c200 | 26 | #include <linux/gpio.h> |
2b908075 TA |
27 | #include <linux/of.h> |
28 | #include <linux/of_gpio.h> | |
230d42d4 | 29 | |
436d42c6 | 30 | #include <linux/platform_data/spi-s3c64xx.h> |
230d42d4 | 31 | |
bf77cba9 | 32 | #define MAX_SPI_PORTS 6 |
7e995556 | 33 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
bf77cba9 | 34 | #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) |
483867ee | 35 | #define AUTOSUSPEND_TIMEOUT 2000 |
a5238e36 | 36 | |
230d42d4 JB |
37 | /* Registers and bit-fields */ |
38 | ||
39 | #define S3C64XX_SPI_CH_CFG 0x00 | |
40 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
41 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
42 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
43 | #define S3C64XX_SPI_INT_EN 0x10 | |
44 | #define S3C64XX_SPI_STATUS 0x14 | |
45 | #define S3C64XX_SPI_TX_DATA 0x18 | |
46 | #define S3C64XX_SPI_RX_DATA 0x1C | |
47 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
48 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
49 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
50 | #define S3C64XX_SPI_FB_CLK 0x2C | |
51 | ||
52 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
53 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
54 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
55 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
56 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
57 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
58 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
59 | ||
60 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
61 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
62 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
75bf3361 | 63 | #define S3C64XX_SPI_PSR_MASK 0xff |
230d42d4 JB |
64 | |
65 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
66 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
67 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
69 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
70 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
71 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
72 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
73 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
74 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
75 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
76 | ||
77 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
78 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
bf77cba9 | 79 | #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) |
230d42d4 | 80 | |
230d42d4 JB |
81 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
82 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
83 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
84 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
85 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
86 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
87 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
88 | ||
89 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
90 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
91 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
92 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
93 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
94 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
95 | ||
96 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
97 | ||
98 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
99 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
100 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
101 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
102 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
103 | ||
104 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
105 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
106 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
107 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
108 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
109 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
110 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
111 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
112 | ||
113 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
114 | ||
a5238e36 TA |
115 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
116 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | |
117 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | |
118 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | |
119 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | |
120 | FIFO_LVL_MASK(i)) | |
230d42d4 JB |
121 | |
122 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
123 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
124 | ||
125 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
126 | ||
127 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
7e995556 | 128 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
230d42d4 | 129 | |
230d42d4 JB |
130 | #define RXBUSY (1<<2) |
131 | #define TXBUSY (1<<3) | |
132 | ||
82ab8cd7 | 133 | struct s3c64xx_spi_dma_data { |
78843727 | 134 | struct dma_chan *ch; |
c10356b9 | 135 | enum dma_transfer_direction direction; |
78843727 | 136 | unsigned int dmach; |
82ab8cd7 BK |
137 | }; |
138 | ||
a5238e36 TA |
139 | /** |
140 | * struct s3c64xx_spi_info - SPI Controller hardware info | |
141 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | |
142 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | |
143 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | |
144 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | |
145 | * @clk_from_cmu: True, if the controller does not include a clock mux and | |
146 | * prescaler unit. | |
147 | * | |
148 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | |
149 | * differ in some aspects such as the size of the fifo and spi bus clock | |
150 | * setup. Such differences are specified to the driver using this structure | |
151 | * which is provided as driver data to the driver. | |
152 | */ | |
153 | struct s3c64xx_spi_port_config { | |
154 | int fifo_lvl_mask[MAX_SPI_PORTS]; | |
155 | int rx_lvl_offset; | |
156 | int tx_st_done; | |
7e995556 | 157 | int quirks; |
a5238e36 TA |
158 | bool high_speed; |
159 | bool clk_from_cmu; | |
160 | }; | |
161 | ||
230d42d4 JB |
162 | /** |
163 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
164 | * @clk: Pointer to the spi clock. | |
b0d5d6e5 | 165 | * @src_clk: Pointer to the clock used to generate SPI signals. |
230d42d4 | 166 | * @master: Pointer to the SPI Protocol master. |
230d42d4 JB |
167 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
168 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
230d42d4 JB |
169 | * @lock: Controller specific lock. |
170 | * @state: Set of FLAGS to indicate status. | |
171 | * @rx_dmach: Controller's DMA channel for Rx. | |
172 | * @tx_dmach: Controller's DMA channel for Tx. | |
173 | * @sfr_start: BUS address of SPI controller regs. | |
174 | * @regs: Pointer to ioremap'ed controller registers. | |
c2573128 | 175 | * @irq: interrupt |
230d42d4 JB |
176 | * @xfer_completion: To indicate completion of xfer task. |
177 | * @cur_mode: Stores the active configuration of the controller. | |
178 | * @cur_bpw: Stores the active bits per word settings. | |
179 | * @cur_speed: Stores the active xfer clock speed. | |
180 | */ | |
181 | struct s3c64xx_spi_driver_data { | |
182 | void __iomem *regs; | |
183 | struct clk *clk; | |
b0d5d6e5 | 184 | struct clk *src_clk; |
230d42d4 JB |
185 | struct platform_device *pdev; |
186 | struct spi_master *master; | |
ad7de729 | 187 | struct s3c64xx_spi_info *cntrlr_info; |
230d42d4 | 188 | struct spi_device *tgl_spi; |
230d42d4 | 189 | spinlock_t lock; |
230d42d4 JB |
190 | unsigned long sfr_start; |
191 | struct completion xfer_completion; | |
192 | unsigned state; | |
193 | unsigned cur_mode, cur_bpw; | |
194 | unsigned cur_speed; | |
82ab8cd7 BK |
195 | struct s3c64xx_spi_dma_data rx_dma; |
196 | struct s3c64xx_spi_dma_data tx_dma; | |
a5238e36 TA |
197 | struct s3c64xx_spi_port_config *port_conf; |
198 | unsigned int port_id; | |
230d42d4 JB |
199 | }; |
200 | ||
230d42d4 JB |
201 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
202 | { | |
230d42d4 JB |
203 | void __iomem *regs = sdd->regs; |
204 | unsigned long loops; | |
205 | u32 val; | |
206 | ||
207 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
208 | ||
7d859ff4 KK |
209 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
210 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
211 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
212 | ||
230d42d4 JB |
213 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
214 | val |= S3C64XX_SPI_CH_SW_RST; | |
215 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
216 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
217 | ||
218 | /* Flush TxFIFO*/ | |
219 | loops = msecs_to_loops(1); | |
220 | do { | |
221 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 222 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
230d42d4 | 223 | |
be7852a8 MB |
224 | if (loops == 0) |
225 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
226 | ||
230d42d4 JB |
227 | /* Flush RxFIFO*/ |
228 | loops = msecs_to_loops(1); | |
229 | do { | |
230 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 231 | if (RX_FIFO_LVL(val, sdd)) |
230d42d4 JB |
232 | readl(regs + S3C64XX_SPI_RX_DATA); |
233 | else | |
234 | break; | |
235 | } while (loops--); | |
236 | ||
be7852a8 MB |
237 | if (loops == 0) |
238 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
239 | ||
230d42d4 JB |
240 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
241 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
242 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
243 | ||
244 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
245 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
246 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
230d42d4 JB |
247 | } |
248 | ||
82ab8cd7 | 249 | static void s3c64xx_spi_dmacb(void *data) |
39d3e807 | 250 | { |
82ab8cd7 BK |
251 | struct s3c64xx_spi_driver_data *sdd; |
252 | struct s3c64xx_spi_dma_data *dma = data; | |
39d3e807 BK |
253 | unsigned long flags; |
254 | ||
054ebcc4 | 255 | if (dma->direction == DMA_DEV_TO_MEM) |
82ab8cd7 BK |
256 | sdd = container_of(data, |
257 | struct s3c64xx_spi_driver_data, rx_dma); | |
258 | else | |
259 | sdd = container_of(data, | |
260 | struct s3c64xx_spi_driver_data, tx_dma); | |
261 | ||
39d3e807 BK |
262 | spin_lock_irqsave(&sdd->lock, flags); |
263 | ||
054ebcc4 | 264 | if (dma->direction == DMA_DEV_TO_MEM) { |
82ab8cd7 BK |
265 | sdd->state &= ~RXBUSY; |
266 | if (!(sdd->state & TXBUSY)) | |
267 | complete(&sdd->xfer_completion); | |
268 | } else { | |
269 | sdd->state &= ~TXBUSY; | |
270 | if (!(sdd->state & RXBUSY)) | |
271 | complete(&sdd->xfer_completion); | |
272 | } | |
39d3e807 BK |
273 | |
274 | spin_unlock_irqrestore(&sdd->lock, flags); | |
275 | } | |
276 | ||
78843727 | 277 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
6ad45a27 | 278 | struct sg_table *sgt) |
78843727 AB |
279 | { |
280 | struct s3c64xx_spi_driver_data *sdd; | |
281 | struct dma_slave_config config; | |
78843727 AB |
282 | struct dma_async_tx_descriptor *desc; |
283 | ||
b1a8e78d TF |
284 | memset(&config, 0, sizeof(config)); |
285 | ||
78843727 AB |
286 | if (dma->direction == DMA_DEV_TO_MEM) { |
287 | sdd = container_of((void *)dma, | |
288 | struct s3c64xx_spi_driver_data, rx_dma); | |
289 | config.direction = dma->direction; | |
290 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
291 | config.src_addr_width = sdd->cur_bpw / 8; | |
292 | config.src_maxburst = 1; | |
293 | dmaengine_slave_config(dma->ch, &config); | |
294 | } else { | |
295 | sdd = container_of((void *)dma, | |
296 | struct s3c64xx_spi_driver_data, tx_dma); | |
297 | config.direction = dma->direction; | |
298 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
299 | config.dst_addr_width = sdd->cur_bpw / 8; | |
300 | config.dst_maxburst = 1; | |
301 | dmaengine_slave_config(dma->ch, &config); | |
302 | } | |
303 | ||
6ad45a27 MB |
304 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, |
305 | dma->direction, DMA_PREP_INTERRUPT); | |
78843727 AB |
306 | |
307 | desc->callback = s3c64xx_spi_dmacb; | |
308 | desc->callback_param = dma; | |
309 | ||
310 | dmaengine_submit(desc); | |
311 | dma_async_issue_pending(dma->ch); | |
312 | } | |
313 | ||
314 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) | |
315 | { | |
316 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
317 | dma_filter_fn filter = sdd->cntrlr_info->filter; | |
318 | struct device *dev = &sdd->pdev->dev; | |
319 | dma_cap_mask_t mask; | |
fb9d044e | 320 | int ret; |
78843727 | 321 | |
c12f9643 MB |
322 | if (!is_polling(sdd)) { |
323 | dma_cap_zero(mask); | |
324 | dma_cap_set(DMA_SLAVE, mask); | |
325 | ||
326 | /* Acquire DMA channels */ | |
327 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, | |
0744ea2a | 328 | (void *)(long)sdd->rx_dma.dmach, dev, "rx"); |
c12f9643 MB |
329 | if (!sdd->rx_dma.ch) { |
330 | dev_err(dev, "Failed to get RX DMA channel\n"); | |
331 | ret = -EBUSY; | |
332 | goto out; | |
333 | } | |
3f295887 | 334 | spi->dma_rx = sdd->rx_dma.ch; |
fb9d044e | 335 | |
c12f9643 | 336 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
0744ea2a | 337 | (void *)(long)sdd->tx_dma.dmach, dev, "tx"); |
c12f9643 MB |
338 | if (!sdd->tx_dma.ch) { |
339 | dev_err(dev, "Failed to get TX DMA channel\n"); | |
340 | ret = -EBUSY; | |
341 | goto out_rx; | |
342 | } | |
3f295887 | 343 | spi->dma_tx = sdd->tx_dma.ch; |
fb9d044e MB |
344 | } |
345 | ||
78843727 | 346 | return 0; |
fb9d044e | 347 | |
fb9d044e MB |
348 | out_rx: |
349 | dma_release_channel(sdd->rx_dma.ch); | |
350 | out: | |
351 | return ret; | |
78843727 AB |
352 | } |
353 | ||
354 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | |
355 | { | |
356 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
357 | ||
358 | /* Free DMA channels */ | |
7e995556 G |
359 | if (!is_polling(sdd)) { |
360 | dma_release_channel(sdd->rx_dma.ch); | |
361 | dma_release_channel(sdd->tx_dma.ch); | |
362 | } | |
78843727 | 363 | |
78843727 AB |
364 | return 0; |
365 | } | |
366 | ||
3f295887 MB |
367 | static bool s3c64xx_spi_can_dma(struct spi_master *master, |
368 | struct spi_device *spi, | |
369 | struct spi_transfer *xfer) | |
370 | { | |
371 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
372 | ||
373 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
374 | } | |
375 | ||
230d42d4 JB |
376 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
377 | struct spi_device *spi, | |
378 | struct spi_transfer *xfer, int dma_mode) | |
379 | { | |
230d42d4 JB |
380 | void __iomem *regs = sdd->regs; |
381 | u32 modecfg, chcfg; | |
382 | ||
383 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
384 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
385 | ||
386 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
387 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
388 | ||
389 | if (dma_mode) { | |
390 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
391 | } else { | |
392 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
393 | * this helps setting PCKT_CNT value for generating clocks | |
394 | * as exactly needed. | |
395 | */ | |
396 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
397 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
398 | | S3C64XX_SPI_PACKET_CNT_EN, | |
399 | regs + S3C64XX_SPI_PACKET_CNT); | |
400 | } | |
401 | ||
402 | if (xfer->tx_buf != NULL) { | |
403 | sdd->state |= TXBUSY; | |
404 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
405 | if (dma_mode) { | |
406 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
6ad45a27 | 407 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); |
230d42d4 | 408 | } else { |
0c92ecf1 JB |
409 | switch (sdd->cur_bpw) { |
410 | case 32: | |
411 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
412 | xfer->tx_buf, xfer->len / 4); | |
413 | break; | |
414 | case 16: | |
415 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
416 | xfer->tx_buf, xfer->len / 2); | |
417 | break; | |
418 | default: | |
419 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
420 | xfer->tx_buf, xfer->len); | |
421 | break; | |
422 | } | |
230d42d4 JB |
423 | } |
424 | } | |
425 | ||
426 | if (xfer->rx_buf != NULL) { | |
427 | sdd->state |= RXBUSY; | |
428 | ||
a5238e36 | 429 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
230d42d4 JB |
430 | && !(sdd->cur_mode & SPI_CPHA)) |
431 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
432 | ||
433 | if (dma_mode) { | |
434 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
435 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
436 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
437 | | S3C64XX_SPI_PACKET_CNT_EN, | |
438 | regs + S3C64XX_SPI_PACKET_CNT); | |
6ad45a27 | 439 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); |
230d42d4 JB |
440 | } |
441 | } | |
442 | ||
443 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
444 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
445 | } | |
446 | ||
79617073 | 447 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
7e995556 G |
448 | int timeout_ms) |
449 | { | |
450 | void __iomem *regs = sdd->regs; | |
451 | unsigned long val = 1; | |
452 | u32 status; | |
453 | ||
454 | /* max fifo depth available */ | |
455 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
456 | ||
457 | if (timeout_ms) | |
458 | val = msecs_to_loops(timeout_ms); | |
459 | ||
460 | do { | |
461 | status = readl(regs + S3C64XX_SPI_STATUS); | |
462 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); | |
463 | ||
464 | /* return the actual received data length */ | |
465 | return RX_FIFO_LVL(status, sdd); | |
230d42d4 JB |
466 | } |
467 | ||
3700c6eb MB |
468 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
469 | struct spi_transfer *xfer) | |
230d42d4 | 470 | { |
230d42d4 JB |
471 | void __iomem *regs = sdd->regs; |
472 | unsigned long val; | |
3700c6eb | 473 | u32 status; |
230d42d4 JB |
474 | int ms; |
475 | ||
476 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
477 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
9d8f86b5 | 478 | ms += 10; /* some tolerance */ |
230d42d4 | 479 | |
3700c6eb MB |
480 | val = msecs_to_jiffies(ms) + 10; |
481 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
482 | ||
483 | /* | |
484 | * If the previous xfer was completed within timeout, then | |
485 | * proceed further else return -EIO. | |
486 | * DmaTx returns after simply writing data in the FIFO, | |
487 | * w/o waiting for real transmission on the bus to finish. | |
488 | * DmaRx returns only after Dma read data from FIFO which | |
489 | * needs bus transmission to finish, so we don't worry if | |
490 | * Xfer involved Rx(with or without Tx). | |
491 | */ | |
492 | if (val && !xfer->rx_buf) { | |
493 | val = msecs_to_loops(10); | |
494 | status = readl(regs + S3C64XX_SPI_STATUS); | |
495 | while ((TX_FIFO_LVL(status, sdd) | |
496 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | |
497 | && --val) { | |
498 | cpu_relax(); | |
c3f139b6 | 499 | status = readl(regs + S3C64XX_SPI_STATUS); |
3700c6eb MB |
500 | } |
501 | ||
230d42d4 JB |
502 | } |
503 | ||
3700c6eb MB |
504 | /* If timed out while checking rx/tx status return error */ |
505 | if (!val) | |
506 | return -EIO; | |
230d42d4 | 507 | |
3700c6eb MB |
508 | return 0; |
509 | } | |
7e995556 | 510 | |
3700c6eb MB |
511 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
512 | struct spi_transfer *xfer) | |
513 | { | |
514 | void __iomem *regs = sdd->regs; | |
515 | unsigned long val; | |
516 | u32 status; | |
517 | int loops; | |
518 | u32 cpy_len; | |
519 | u8 *buf; | |
520 | int ms; | |
230d42d4 | 521 | |
3700c6eb MB |
522 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
523 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
524 | ms += 10; /* some tolerance */ | |
7e995556 | 525 | |
3700c6eb MB |
526 | val = msecs_to_loops(ms); |
527 | do { | |
528 | status = readl(regs + S3C64XX_SPI_STATUS); | |
529 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | |
7e995556 | 530 | |
3700c6eb MB |
531 | |
532 | /* If it was only Tx */ | |
533 | if (!xfer->rx_buf) { | |
534 | sdd->state &= ~TXBUSY; | |
535 | return 0; | |
230d42d4 JB |
536 | } |
537 | ||
3700c6eb MB |
538 | /* |
539 | * If the receive length is bigger than the controller fifo | |
540 | * size, calculate the loops and read the fifo as many times. | |
541 | * loops = length / max fifo size (calculated by using the | |
542 | * fifo mask). | |
543 | * For any size less than the fifo size the below code is | |
544 | * executed atleast once. | |
545 | */ | |
546 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); | |
547 | buf = xfer->rx_buf; | |
548 | do { | |
549 | /* wait for data to be received in the fifo */ | |
550 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, | |
551 | (loops ? ms : 0)); | |
552 | ||
553 | switch (sdd->cur_bpw) { | |
554 | case 32: | |
555 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
556 | buf, cpy_len / 4); | |
557 | break; | |
558 | case 16: | |
559 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
560 | buf, cpy_len / 2); | |
561 | break; | |
562 | default: | |
563 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
564 | buf, cpy_len); | |
565 | break; | |
566 | } | |
567 | ||
568 | buf = buf + cpy_len; | |
569 | } while (loops--); | |
570 | sdd->state &= ~RXBUSY; | |
571 | ||
230d42d4 JB |
572 | return 0; |
573 | } | |
574 | ||
230d42d4 JB |
575 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
576 | { | |
230d42d4 JB |
577 | void __iomem *regs = sdd->regs; |
578 | u32 val; | |
579 | ||
580 | /* Disable Clock */ | |
a5238e36 | 581 | if (sdd->port_conf->clk_from_cmu) { |
9f667bff | 582 | clk_disable_unprepare(sdd->src_clk); |
b42a81ca JB |
583 | } else { |
584 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
585 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
586 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
587 | } | |
230d42d4 JB |
588 | |
589 | /* Set Polarity and Phase */ | |
590 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
591 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
592 | S3C64XX_SPI_CPOL_L | | |
593 | S3C64XX_SPI_CPHA_B); | |
594 | ||
595 | if (sdd->cur_mode & SPI_CPOL) | |
596 | val |= S3C64XX_SPI_CPOL_L; | |
597 | ||
598 | if (sdd->cur_mode & SPI_CPHA) | |
599 | val |= S3C64XX_SPI_CPHA_B; | |
600 | ||
601 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
602 | ||
603 | /* Set Channel & DMA Mode */ | |
604 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
605 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
606 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
607 | ||
608 | switch (sdd->cur_bpw) { | |
609 | case 32: | |
610 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
0c92ecf1 | 611 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
230d42d4 JB |
612 | break; |
613 | case 16: | |
614 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
0c92ecf1 | 615 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
230d42d4 JB |
616 | break; |
617 | default: | |
618 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
0c92ecf1 | 619 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
230d42d4 JB |
620 | break; |
621 | } | |
230d42d4 JB |
622 | |
623 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
624 | ||
a5238e36 | 625 | if (sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
626 | /* Configure Clock */ |
627 | /* There is half-multiplier before the SPI */ | |
628 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); | |
629 | /* Enable Clock */ | |
9f667bff | 630 | clk_prepare_enable(sdd->src_clk); |
b42a81ca JB |
631 | } else { |
632 | /* Configure Clock */ | |
633 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
634 | val &= ~S3C64XX_SPI_PSR_MASK; | |
635 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
636 | & S3C64XX_SPI_PSR_MASK); | |
637 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
638 | ||
639 | /* Enable Clock */ | |
640 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
641 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
642 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
643 | } | |
230d42d4 JB |
644 | } |
645 | ||
230d42d4 JB |
646 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
647 | ||
6bb9c0e3 MB |
648 | static int s3c64xx_spi_prepare_message(struct spi_master *master, |
649 | struct spi_message *msg) | |
230d42d4 | 650 | { |
ad2a99af | 651 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 JB |
652 | struct spi_device *spi = msg->spi; |
653 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
230d42d4 JB |
654 | |
655 | /* If Master's(controller) state differs from that needed by Slave */ | |
656 | if (sdd->cur_speed != spi->max_speed_hz | |
657 | || sdd->cur_mode != spi->mode | |
658 | || sdd->cur_bpw != spi->bits_per_word) { | |
659 | sdd->cur_bpw = spi->bits_per_word; | |
660 | sdd->cur_speed = spi->max_speed_hz; | |
661 | sdd->cur_mode = spi->mode; | |
662 | s3c64xx_spi_config(sdd); | |
663 | } | |
664 | ||
230d42d4 JB |
665 | /* Configure feedback delay */ |
666 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
667 | ||
6bb9c0e3 MB |
668 | return 0; |
669 | } | |
0c92ecf1 | 670 | |
0732a9d2 MB |
671 | static int s3c64xx_spi_transfer_one(struct spi_master *master, |
672 | struct spi_device *spi, | |
673 | struct spi_transfer *xfer) | |
6bb9c0e3 MB |
674 | { |
675 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
0732a9d2 | 676 | int status; |
6bb9c0e3 MB |
677 | u32 speed; |
678 | u8 bpw; | |
0732a9d2 MB |
679 | unsigned long flags; |
680 | int use_dma; | |
230d42d4 | 681 | |
3e83c194 | 682 | reinit_completion(&sdd->xfer_completion); |
230d42d4 | 683 | |
0732a9d2 MB |
684 | /* Only BPW and Speed may change across transfers */ |
685 | bpw = xfer->bits_per_word; | |
88d4a744 | 686 | speed = xfer->speed_hz; |
230d42d4 | 687 | |
0732a9d2 MB |
688 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
689 | sdd->cur_bpw = bpw; | |
690 | sdd->cur_speed = speed; | |
691 | s3c64xx_spi_config(sdd); | |
692 | } | |
230d42d4 | 693 | |
0732a9d2 MB |
694 | /* Polling method for xfers not bigger than FIFO capacity */ |
695 | use_dma = 0; | |
696 | if (!is_polling(sdd) && | |
697 | (sdd->rx_dma.ch && sdd->tx_dma.ch && | |
698 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) | |
699 | use_dma = 1; | |
230d42d4 | 700 | |
0732a9d2 | 701 | spin_lock_irqsave(&sdd->lock, flags); |
230d42d4 | 702 | |
0732a9d2 MB |
703 | /* Pending only which is to be done */ |
704 | sdd->state &= ~RXBUSY; | |
705 | sdd->state &= ~TXBUSY; | |
230d42d4 | 706 | |
0732a9d2 | 707 | enable_datapath(sdd, spi, xfer, use_dma); |
230d42d4 | 708 | |
0732a9d2 | 709 | /* Start the signals */ |
bf77cba9 PV |
710 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
711 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
712 | else | |
713 | writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL) | |
714 | | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2, | |
715 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
230d42d4 | 716 | |
0732a9d2 | 717 | spin_unlock_irqrestore(&sdd->lock, flags); |
230d42d4 | 718 | |
3700c6eb MB |
719 | if (use_dma) |
720 | status = wait_for_dma(sdd, xfer); | |
721 | else | |
722 | status = wait_for_pio(sdd, xfer); | |
0732a9d2 MB |
723 | |
724 | if (status) { | |
725 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
726 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | |
727 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
728 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
729 | xfer->len); | |
730 | ||
731 | if (use_dma) { | |
732 | if (xfer->tx_buf != NULL | |
733 | && (sdd->state & TXBUSY)) | |
1b5e1b69 | 734 | dmaengine_terminate_all(sdd->tx_dma.ch); |
0732a9d2 MB |
735 | if (xfer->rx_buf != NULL |
736 | && (sdd->state & RXBUSY)) | |
1b5e1b69 | 737 | dmaengine_terminate_all(sdd->rx_dma.ch); |
230d42d4 | 738 | } |
8c09daa1 | 739 | } else { |
230d42d4 JB |
740 | flush_fifo(sdd); |
741 | } | |
742 | ||
0732a9d2 | 743 | return status; |
230d42d4 | 744 | } |
230d42d4 | 745 | |
2b908075 | 746 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
2b908075 TA |
747 | struct spi_device *spi) |
748 | { | |
749 | struct s3c64xx_spi_csinfo *cs; | |
4732cc63 | 750 | struct device_node *slave_np, *data_np = NULL; |
2b908075 TA |
751 | u32 fb_delay = 0; |
752 | ||
753 | slave_np = spi->dev.of_node; | |
754 | if (!slave_np) { | |
755 | dev_err(&spi->dev, "device node not found\n"); | |
756 | return ERR_PTR(-EINVAL); | |
757 | } | |
758 | ||
06455bbc | 759 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
2b908075 TA |
760 | if (!data_np) { |
761 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | |
762 | return ERR_PTR(-EINVAL); | |
763 | } | |
764 | ||
765 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | |
766 | if (!cs) { | |
06455bbc | 767 | of_node_put(data_np); |
2b908075 TA |
768 | return ERR_PTR(-ENOMEM); |
769 | } | |
770 | ||
2b908075 TA |
771 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); |
772 | cs->fb_delay = fb_delay; | |
06455bbc | 773 | of_node_put(data_np); |
2b908075 TA |
774 | return cs; |
775 | } | |
776 | ||
230d42d4 JB |
777 | /* |
778 | * Here we only check the validity of requested configuration | |
779 | * and save the configuration in a local data-structure. | |
780 | * The controller is actually configured only just before we | |
781 | * get a message to transfer. | |
782 | */ | |
783 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
784 | { | |
785 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
786 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 787 | struct s3c64xx_spi_info *sci; |
2b908075 | 788 | int err; |
230d42d4 | 789 | |
2b908075 | 790 | sdd = spi_master_get_devdata(spi->master); |
306972ce | 791 | if (spi->dev.of_node) { |
5c725b34 | 792 | cs = s3c64xx_get_slave_ctrldata(spi); |
2b908075 | 793 | spi->controller_data = cs; |
306972ce NKC |
794 | } else if (cs) { |
795 | /* On non-DT platforms the SPI core will set spi->cs_gpio | |
796 | * to -ENOENT. The GPIO pin used to drive the chip select | |
797 | * is defined by using platform data so spi->cs_gpio value | |
798 | * has to be override to have the proper GPIO pin number. | |
799 | */ | |
800 | spi->cs_gpio = cs->line; | |
2b908075 TA |
801 | } |
802 | ||
803 | if (IS_ERR_OR_NULL(cs)) { | |
230d42d4 JB |
804 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
805 | return -ENODEV; | |
806 | } | |
807 | ||
0149871c | 808 | if (!spi_get_ctldata(spi)) { |
306972ce NKC |
809 | if (gpio_is_valid(spi->cs_gpio)) { |
810 | err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, | |
811 | dev_name(&spi->dev)); | |
812 | if (err) { | |
813 | dev_err(&spi->dev, | |
814 | "Failed to get /CS gpio [%d]: %d\n", | |
815 | spi->cs_gpio, err); | |
816 | goto err_gpio_req; | |
817 | } | |
1c20c200 | 818 | } |
1c20c200 | 819 | |
3146beec | 820 | spi_set_ctldata(spi, cs); |
230d42d4 JB |
821 | } |
822 | ||
230d42d4 | 823 | sci = sdd->cntrlr_info; |
230d42d4 | 824 | |
b97b6621 MB |
825 | pm_runtime_get_sync(&sdd->pdev->dev); |
826 | ||
230d42d4 | 827 | /* Check if we can provide the requested rate */ |
a5238e36 | 828 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
829 | u32 psr, speed; |
830 | ||
831 | /* Max possible */ | |
832 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
833 | ||
834 | if (spi->max_speed_hz > speed) | |
835 | spi->max_speed_hz = speed; | |
836 | ||
837 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
838 | psr &= S3C64XX_SPI_PSR_MASK; | |
839 | if (psr == S3C64XX_SPI_PSR_MASK) | |
840 | psr--; | |
841 | ||
842 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
843 | if (spi->max_speed_hz < speed) { | |
844 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
845 | psr++; | |
846 | } else { | |
847 | err = -EINVAL; | |
848 | goto setup_exit; | |
849 | } | |
850 | } | |
230d42d4 | 851 | |
b42a81ca | 852 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
2b908075 | 853 | if (spi->max_speed_hz >= speed) { |
b42a81ca | 854 | spi->max_speed_hz = speed; |
2b908075 | 855 | } else { |
e1b0f0df MB |
856 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
857 | spi->max_speed_hz); | |
230d42d4 | 858 | err = -EINVAL; |
2b908075 TA |
859 | goto setup_exit; |
860 | } | |
230d42d4 JB |
861 | } |
862 | ||
483867ee HK |
863 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
864 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
bf77cba9 PV |
865 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
866 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
2b908075 | 867 | return 0; |
b97b6621 | 868 | |
230d42d4 | 869 | setup_exit: |
483867ee HK |
870 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
871 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
230d42d4 | 872 | /* setup() returns with device de-selected */ |
bf77cba9 PV |
873 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
874 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
230d42d4 | 875 | |
306972ce NKC |
876 | if (gpio_is_valid(spi->cs_gpio)) |
877 | gpio_free(spi->cs_gpio); | |
2b908075 TA |
878 | spi_set_ctldata(spi, NULL); |
879 | ||
880 | err_gpio_req: | |
5bee3b94 SN |
881 | if (spi->dev.of_node) |
882 | kfree(cs); | |
2b908075 | 883 | |
230d42d4 JB |
884 | return err; |
885 | } | |
886 | ||
1c20c200 TA |
887 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
888 | { | |
889 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | |
890 | ||
306972ce | 891 | if (gpio_is_valid(spi->cs_gpio)) { |
dd97e268 | 892 | gpio_free(spi->cs_gpio); |
2b908075 TA |
893 | if (spi->dev.of_node) |
894 | kfree(cs); | |
306972ce NKC |
895 | else { |
896 | /* On non-DT platforms, the SPI core sets | |
897 | * spi->cs_gpio to -ENOENT and .setup() | |
898 | * overrides it with the GPIO pin value | |
899 | * passed using platform data. | |
900 | */ | |
901 | spi->cs_gpio = -ENOENT; | |
902 | } | |
2b908075 | 903 | } |
306972ce | 904 | |
1c20c200 TA |
905 | spi_set_ctldata(spi, NULL); |
906 | } | |
907 | ||
c2573128 MB |
908 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
909 | { | |
910 | struct s3c64xx_spi_driver_data *sdd = data; | |
911 | struct spi_master *spi = sdd->master; | |
375981f2 | 912 | unsigned int val, clr = 0; |
c2573128 | 913 | |
375981f2 | 914 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
c2573128 | 915 | |
375981f2 G |
916 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
917 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; | |
c2573128 | 918 | dev_err(&spi->dev, "RX overrun\n"); |
375981f2 G |
919 | } |
920 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { | |
921 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; | |
c2573128 | 922 | dev_err(&spi->dev, "RX underrun\n"); |
375981f2 G |
923 | } |
924 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { | |
925 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; | |
c2573128 | 926 | dev_err(&spi->dev, "TX overrun\n"); |
375981f2 G |
927 | } |
928 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { | |
929 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
c2573128 | 930 | dev_err(&spi->dev, "TX underrun\n"); |
375981f2 G |
931 | } |
932 | ||
933 | /* Clear the pending irq by setting and then clearing it */ | |
934 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
935 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
c2573128 MB |
936 | |
937 | return IRQ_HANDLED; | |
938 | } | |
939 | ||
230d42d4 JB |
940 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
941 | { | |
ad7de729 | 942 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
943 | void __iomem *regs = sdd->regs; |
944 | unsigned int val; | |
945 | ||
946 | sdd->cur_speed = 0; | |
947 | ||
bf77cba9 PV |
948 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
949 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
230d42d4 JB |
950 | |
951 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
952 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
953 | ||
a5238e36 | 954 | if (!sdd->port_conf->clk_from_cmu) |
b42a81ca | 955 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
230d42d4 JB |
956 | regs + S3C64XX_SPI_CLK_CFG); |
957 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
958 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
959 | ||
375981f2 G |
960 | /* Clear any irq pending bits, should set and clear the bits */ |
961 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
962 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
963 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
964 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
965 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); | |
966 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); | |
230d42d4 JB |
967 | |
968 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
969 | ||
970 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
971 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
972 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
973 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
974 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
975 | ||
976 | flush_fifo(sdd); | |
977 | } | |
978 | ||
2b908075 | 979 | #ifdef CONFIG_OF |
75bf3361 | 980 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
2b908075 TA |
981 | { |
982 | struct s3c64xx_spi_info *sci; | |
983 | u32 temp; | |
984 | ||
985 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | |
1273eb05 | 986 | if (!sci) |
2b908075 | 987 | return ERR_PTR(-ENOMEM); |
2b908075 TA |
988 | |
989 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | |
75bf3361 | 990 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
2b908075 TA |
991 | sci->src_clk_nr = 0; |
992 | } else { | |
993 | sci->src_clk_nr = temp; | |
994 | } | |
995 | ||
996 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | |
75bf3361 | 997 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
2b908075 TA |
998 | sci->num_cs = 1; |
999 | } else { | |
1000 | sci->num_cs = temp; | |
1001 | } | |
1002 | ||
1003 | return sci; | |
1004 | } | |
1005 | #else | |
1006 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1007 | { | |
8074cf06 | 1008 | return dev_get_platdata(dev); |
2b908075 | 1009 | } |
2b908075 TA |
1010 | #endif |
1011 | ||
1012 | static const struct of_device_id s3c64xx_spi_dt_match[]; | |
1013 | ||
a5238e36 TA |
1014 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
1015 | struct platform_device *pdev) | |
1016 | { | |
2b908075 TA |
1017 | #ifdef CONFIG_OF |
1018 | if (pdev->dev.of_node) { | |
1019 | const struct of_device_id *match; | |
1020 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | |
1021 | return (struct s3c64xx_spi_port_config *)match->data; | |
1022 | } | |
1023 | #endif | |
a5238e36 TA |
1024 | return (struct s3c64xx_spi_port_config *) |
1025 | platform_get_device_id(pdev)->driver_data; | |
1026 | } | |
1027 | ||
2deff8d6 | 1028 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
230d42d4 | 1029 | { |
2b908075 | 1030 | struct resource *mem_res; |
b5be04d3 | 1031 | struct resource *res; |
230d42d4 | 1032 | struct s3c64xx_spi_driver_data *sdd; |
8074cf06 | 1033 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); |
230d42d4 | 1034 | struct spi_master *master; |
c2573128 | 1035 | int ret, irq; |
a24d850b | 1036 | char clk_name[16]; |
230d42d4 | 1037 | |
2b908075 TA |
1038 | if (!sci && pdev->dev.of_node) { |
1039 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | |
1040 | if (IS_ERR(sci)) | |
1041 | return PTR_ERR(sci); | |
230d42d4 JB |
1042 | } |
1043 | ||
2b908075 | 1044 | if (!sci) { |
230d42d4 JB |
1045 | dev_err(&pdev->dev, "platform_data missing!\n"); |
1046 | return -ENODEV; | |
1047 | } | |
1048 | ||
230d42d4 JB |
1049 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1050 | if (mem_res == NULL) { | |
1051 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1052 | return -ENXIO; | |
1053 | } | |
1054 | ||
c2573128 MB |
1055 | irq = platform_get_irq(pdev, 0); |
1056 | if (irq < 0) { | |
1057 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1058 | return irq; | |
1059 | } | |
1060 | ||
230d42d4 JB |
1061 | master = spi_alloc_master(&pdev->dev, |
1062 | sizeof(struct s3c64xx_spi_driver_data)); | |
1063 | if (master == NULL) { | |
1064 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1065 | return -ENOMEM; | |
1066 | } | |
1067 | ||
230d42d4 JB |
1068 | platform_set_drvdata(pdev, master); |
1069 | ||
1070 | sdd = spi_master_get_devdata(master); | |
a5238e36 | 1071 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
230d42d4 JB |
1072 | sdd->master = master; |
1073 | sdd->cntrlr_info = sci; | |
1074 | sdd->pdev = pdev; | |
1075 | sdd->sfr_start = mem_res->start; | |
2b908075 TA |
1076 | if (pdev->dev.of_node) { |
1077 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | |
1078 | if (ret < 0) { | |
75bf3361 JH |
1079 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
1080 | ret); | |
2b908075 TA |
1081 | goto err0; |
1082 | } | |
1083 | sdd->port_id = ret; | |
1084 | } else { | |
1085 | sdd->port_id = pdev->id; | |
1086 | } | |
230d42d4 JB |
1087 | |
1088 | sdd->cur_bpw = 8; | |
1089 | ||
b5be04d3 PV |
1090 | if (!sdd->pdev->dev.of_node) { |
1091 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1092 | if (!res) { | |
db0606ec | 1093 | dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); |
7e995556 G |
1094 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
1095 | } else | |
1096 | sdd->tx_dma.dmach = res->start; | |
b5be04d3 PV |
1097 | |
1098 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1099 | if (!res) { | |
db0606ec | 1100 | dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); |
7e995556 G |
1101 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
1102 | } else | |
1103 | sdd->rx_dma.dmach = res->start; | |
b5be04d3 | 1104 | } |
2b908075 | 1105 | |
b5be04d3 PV |
1106 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
1107 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; | |
2b908075 TA |
1108 | |
1109 | master->dev.of_node = pdev->dev.of_node; | |
a5238e36 | 1110 | master->bus_num = sdd->port_id; |
230d42d4 | 1111 | master->setup = s3c64xx_spi_setup; |
1c20c200 | 1112 | master->cleanup = s3c64xx_spi_cleanup; |
ad2a99af | 1113 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
6bb9c0e3 | 1114 | master->prepare_message = s3c64xx_spi_prepare_message; |
0732a9d2 | 1115 | master->transfer_one = s3c64xx_spi_transfer_one; |
ad2a99af | 1116 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
230d42d4 JB |
1117 | master->num_chipselect = sci->num_cs; |
1118 | master->dma_alignment = 8; | |
24778be2 SW |
1119 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
1120 | SPI_BPW_MASK(8); | |
230d42d4 JB |
1121 | /* the spi->mode bits understood by this driver: */ |
1122 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
fc0f81b7 | 1123 | master->auto_runtime_pm = true; |
3f295887 MB |
1124 | if (!is_polling(sdd)) |
1125 | master->can_dma = s3c64xx_spi_can_dma; | |
230d42d4 | 1126 | |
b0ee5605 TR |
1127 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
1128 | if (IS_ERR(sdd->regs)) { | |
1129 | ret = PTR_ERR(sdd->regs); | |
4eb77006 | 1130 | goto err0; |
230d42d4 JB |
1131 | } |
1132 | ||
00ab5392 | 1133 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
230d42d4 JB |
1134 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1135 | ret = -EBUSY; | |
4eb77006 | 1136 | goto err0; |
230d42d4 JB |
1137 | } |
1138 | ||
1139 | /* Setup clocks */ | |
4eb77006 | 1140 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
230d42d4 JB |
1141 | if (IS_ERR(sdd->clk)) { |
1142 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1143 | ret = PTR_ERR(sdd->clk); | |
00ab5392 | 1144 | goto err0; |
230d42d4 JB |
1145 | } |
1146 | ||
9f667bff | 1147 | if (clk_prepare_enable(sdd->clk)) { |
230d42d4 JB |
1148 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
1149 | ret = -EBUSY; | |
00ab5392 | 1150 | goto err0; |
230d42d4 JB |
1151 | } |
1152 | ||
a24d850b | 1153 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
4eb77006 | 1154 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
b0d5d6e5 | 1155 | if (IS_ERR(sdd->src_clk)) { |
230d42d4 | 1156 | dev_err(&pdev->dev, |
a24d850b | 1157 | "Unable to acquire clock '%s'\n", clk_name); |
b0d5d6e5 | 1158 | ret = PTR_ERR(sdd->src_clk); |
4eb77006 | 1159 | goto err2; |
230d42d4 JB |
1160 | } |
1161 | ||
9f667bff | 1162 | if (clk_prepare_enable(sdd->src_clk)) { |
a24d850b | 1163 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
230d42d4 | 1164 | ret = -EBUSY; |
4eb77006 | 1165 | goto err2; |
230d42d4 JB |
1166 | } |
1167 | ||
483867ee HK |
1168 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); |
1169 | pm_runtime_use_autosuspend(&pdev->dev); | |
1170 | pm_runtime_set_active(&pdev->dev); | |
1171 | pm_runtime_enable(&pdev->dev); | |
1172 | pm_runtime_get_sync(&pdev->dev); | |
1173 | ||
230d42d4 | 1174 | /* Setup Deufult Mode */ |
a5238e36 | 1175 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 JB |
1176 | |
1177 | spin_lock_init(&sdd->lock); | |
1178 | init_completion(&sdd->xfer_completion); | |
230d42d4 | 1179 | |
4eb77006 JH |
1180 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
1181 | "spi-s3c64xx", sdd); | |
c2573128 MB |
1182 | if (ret != 0) { |
1183 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1184 | irq, ret); | |
4eb77006 | 1185 | goto err3; |
c2573128 MB |
1186 | } |
1187 | ||
1188 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1189 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1190 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1191 | ||
91800f0e MB |
1192 | ret = devm_spi_register_master(&pdev->dev, master); |
1193 | if (ret != 0) { | |
1194 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); | |
483867ee | 1195 | goto err3; |
230d42d4 JB |
1196 | } |
1197 | ||
75bf3361 | 1198 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
a5238e36 | 1199 | sdd->port_id, master->num_chipselect); |
ed425dcf MS |
1200 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%d, Tx-%d]\n", |
1201 | mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1, | |
82ab8cd7 | 1202 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
230d42d4 | 1203 | |
483867ee HK |
1204 | pm_runtime_mark_last_busy(&pdev->dev); |
1205 | pm_runtime_put_autosuspend(&pdev->dev); | |
1206 | ||
230d42d4 JB |
1207 | return 0; |
1208 | ||
483867ee HK |
1209 | err3: |
1210 | pm_runtime_put_noidle(&pdev->dev); | |
3c863792 HK |
1211 | pm_runtime_disable(&pdev->dev); |
1212 | pm_runtime_set_suspended(&pdev->dev); | |
483867ee | 1213 | |
9f667bff | 1214 | clk_disable_unprepare(sdd->src_clk); |
4eb77006 | 1215 | err2: |
9f667bff | 1216 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1217 | err0: |
230d42d4 JB |
1218 | spi_master_put(master); |
1219 | ||
1220 | return ret; | |
1221 | } | |
1222 | ||
1223 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1224 | { | |
1225 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
1226 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
230d42d4 | 1227 | |
8ebe9d16 | 1228 | pm_runtime_get_sync(&pdev->dev); |
b97b6621 | 1229 | |
c2573128 MB |
1230 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1231 | ||
9f667bff | 1232 | clk_disable_unprepare(sdd->src_clk); |
230d42d4 | 1233 | |
9f667bff | 1234 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1235 | |
8ebe9d16 HK |
1236 | pm_runtime_put_noidle(&pdev->dev); |
1237 | pm_runtime_disable(&pdev->dev); | |
1238 | pm_runtime_set_suspended(&pdev->dev); | |
1239 | ||
230d42d4 JB |
1240 | return 0; |
1241 | } | |
1242 | ||
997230d0 | 1243 | #ifdef CONFIG_PM_SLEEP |
e25d0bf9 | 1244 | static int s3c64xx_spi_suspend(struct device *dev) |
230d42d4 | 1245 | { |
9a2a5245 | 1246 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1247 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1248 | |
347de6ba KK |
1249 | int ret = spi_master_suspend(master); |
1250 | if (ret) | |
1251 | return ret; | |
230d42d4 | 1252 | |
4fcd9b9e HK |
1253 | ret = pm_runtime_force_suspend(dev); |
1254 | if (ret < 0) | |
1255 | return ret; | |
230d42d4 JB |
1256 | |
1257 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
e25d0bf9 | 1262 | static int s3c64xx_spi_resume(struct device *dev) |
230d42d4 | 1263 | { |
9a2a5245 | 1264 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1265 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
ad7de729 | 1266 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
4fcd9b9e | 1267 | int ret; |
230d42d4 | 1268 | |
00ab5392 | 1269 | if (sci->cfg_gpio) |
2b908075 | 1270 | sci->cfg_gpio(); |
230d42d4 | 1271 | |
4fcd9b9e HK |
1272 | ret = pm_runtime_force_resume(dev); |
1273 | if (ret < 0) | |
1274 | return ret; | |
230d42d4 | 1275 | |
a5238e36 | 1276 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 | 1277 | |
347de6ba | 1278 | return spi_master_resume(master); |
230d42d4 | 1279 | } |
997230d0 | 1280 | #endif /* CONFIG_PM_SLEEP */ |
230d42d4 | 1281 | |
ec833050 | 1282 | #ifdef CONFIG_PM |
b97b6621 MB |
1283 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
1284 | { | |
9a2a5245 | 1285 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 MB |
1286 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1287 | ||
9f667bff TA |
1288 | clk_disable_unprepare(sdd->clk); |
1289 | clk_disable_unprepare(sdd->src_clk); | |
b97b6621 MB |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1295 | { | |
9a2a5245 | 1296 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 | 1297 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
8b06d5b8 | 1298 | int ret; |
b97b6621 | 1299 | |
8b06d5b8 MB |
1300 | ret = clk_prepare_enable(sdd->src_clk); |
1301 | if (ret != 0) | |
1302 | return ret; | |
1303 | ||
1304 | ret = clk_prepare_enable(sdd->clk); | |
1305 | if (ret != 0) { | |
1306 | clk_disable_unprepare(sdd->src_clk); | |
1307 | return ret; | |
1308 | } | |
b97b6621 MB |
1309 | |
1310 | return 0; | |
1311 | } | |
ec833050 | 1312 | #endif /* CONFIG_PM */ |
b97b6621 | 1313 | |
e25d0bf9 MB |
1314 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1315 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
b97b6621 MB |
1316 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1317 | s3c64xx_spi_runtime_resume, NULL) | |
e25d0bf9 MB |
1318 | }; |
1319 | ||
10ce0473 | 1320 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
a5238e36 TA |
1321 | .fifo_lvl_mask = { 0x7f }, |
1322 | .rx_lvl_offset = 13, | |
1323 | .tx_st_done = 21, | |
1324 | .high_speed = true, | |
1325 | }; | |
1326 | ||
10ce0473 | 1327 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
a5238e36 TA |
1328 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1329 | .rx_lvl_offset = 13, | |
1330 | .tx_st_done = 21, | |
1331 | }; | |
1332 | ||
10ce0473 | 1333 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
a5238e36 TA |
1334 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1335 | .rx_lvl_offset = 15, | |
1336 | .tx_st_done = 25, | |
1337 | .high_speed = true, | |
1338 | }; | |
1339 | ||
10ce0473 | 1340 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
a5238e36 TA |
1341 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
1342 | .rx_lvl_offset = 15, | |
1343 | .tx_st_done = 25, | |
1344 | .high_speed = true, | |
1345 | .clk_from_cmu = true, | |
1346 | }; | |
1347 | ||
bff82038 G |
1348 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
1349 | .fifo_lvl_mask = { 0x1ff }, | |
1350 | .rx_lvl_offset = 15, | |
1351 | .tx_st_done = 25, | |
1352 | .high_speed = true, | |
1353 | .clk_from_cmu = true, | |
1354 | .quirks = S3C64XX_SPI_QUIRK_POLL, | |
1355 | }; | |
1356 | ||
bf77cba9 PV |
1357 | static struct s3c64xx_spi_port_config exynos7_spi_port_config = { |
1358 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, | |
1359 | .rx_lvl_offset = 15, | |
1360 | .tx_st_done = 25, | |
1361 | .high_speed = true, | |
1362 | .clk_from_cmu = true, | |
1363 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1364 | }; | |
1365 | ||
23f6d39e | 1366 | static const struct platform_device_id s3c64xx_spi_driver_ids[] = { |
a5238e36 TA |
1367 | { |
1368 | .name = "s3c2443-spi", | |
1369 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | |
1370 | }, { | |
1371 | .name = "s3c6410-spi", | |
1372 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | |
a5238e36 TA |
1373 | }, { |
1374 | .name = "s5pv210-spi", | |
1375 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, | |
1376 | }, { | |
1377 | .name = "exynos4210-spi", | |
1378 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, | |
1379 | }, | |
1380 | { }, | |
1381 | }; | |
1382 | ||
2b908075 | 1383 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
a3b924df MK |
1384 | { .compatible = "samsung,s3c2443-spi", |
1385 | .data = (void *)&s3c2443_spi_port_config, | |
1386 | }, | |
1387 | { .compatible = "samsung,s3c6410-spi", | |
1388 | .data = (void *)&s3c6410_spi_port_config, | |
1389 | }, | |
a3b924df MK |
1390 | { .compatible = "samsung,s5pv210-spi", |
1391 | .data = (void *)&s5pv210_spi_port_config, | |
1392 | }, | |
2b908075 TA |
1393 | { .compatible = "samsung,exynos4210-spi", |
1394 | .data = (void *)&exynos4_spi_port_config, | |
1395 | }, | |
bff82038 G |
1396 | { .compatible = "samsung,exynos5440-spi", |
1397 | .data = (void *)&exynos5440_spi_port_config, | |
1398 | }, | |
bf77cba9 PV |
1399 | { .compatible = "samsung,exynos7-spi", |
1400 | .data = (void *)&exynos7_spi_port_config, | |
1401 | }, | |
2b908075 TA |
1402 | { }, |
1403 | }; | |
1404 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | |
2b908075 | 1405 | |
230d42d4 JB |
1406 | static struct platform_driver s3c64xx_spi_driver = { |
1407 | .driver = { | |
1408 | .name = "s3c64xx-spi", | |
e25d0bf9 | 1409 | .pm = &s3c64xx_spi_pm, |
2b908075 | 1410 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
230d42d4 | 1411 | }, |
50c959fc | 1412 | .probe = s3c64xx_spi_probe, |
230d42d4 | 1413 | .remove = s3c64xx_spi_remove, |
a5238e36 | 1414 | .id_table = s3c64xx_spi_driver_ids, |
230d42d4 JB |
1415 | }; |
1416 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1417 | ||
50c959fc | 1418 | module_platform_driver(s3c64xx_spi_driver); |
230d42d4 JB |
1419 | |
1420 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1421 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1422 | MODULE_LICENSE("GPL"); |