Commit | Line | Data |
---|---|---|
ca632f55 | 1 | /* |
7fba5340 | 2 | * Copyright (c) 2006 Ben Dooks |
bec0806c | 3 | * Copyright 2006-2009 Simtec Electronics |
7fba5340 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
7fba5340 BD |
12 | #include <linux/spinlock.h> |
13 | #include <linux/workqueue.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/platform_device.h> | |
ee9c1fbf | 20 | #include <linux/gpio.h> |
1a0c220f | 21 | #include <linux/io.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
7fba5340 BD |
23 | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/spi/spi_bitbang.h> | |
f35ef7ca | 26 | #include <linux/spi/s3c24xx.h> |
d7614de4 | 27 | #include <linux/module.h> |
7fba5340 | 28 | |
13622708 | 29 | #include <plat/regs-spi.h> |
7fba5340 | 30 | |
bec0806c BD |
31 | #include <asm/fiq.h> |
32 | ||
ca632f55 | 33 | #include "spi-s3c24xx-fiq.h" |
bec0806c | 34 | |
570327d9 BD |
35 | /** |
36 | * s3c24xx_spi_devstate - per device data | |
37 | * @hz: Last frequency calculated for @sppre field. | |
38 | * @mode: Last mode setting for the @spcon field. | |
39 | * @spcon: Value to write to the SPCON register. | |
40 | * @sppre: Value to write to the SPPRE register. | |
41 | */ | |
42 | struct s3c24xx_spi_devstate { | |
43 | unsigned int hz; | |
44 | unsigned int mode; | |
45 | u8 spcon; | |
46 | u8 sppre; | |
47 | }; | |
48 | ||
bec0806c BD |
49 | enum spi_fiq_mode { |
50 | FIQ_MODE_NONE = 0, | |
51 | FIQ_MODE_TX = 1, | |
52 | FIQ_MODE_RX = 2, | |
53 | FIQ_MODE_TXRX = 3, | |
54 | }; | |
55 | ||
7fba5340 BD |
56 | struct s3c24xx_spi { |
57 | /* bitbang has to be first */ | |
58 | struct spi_bitbang bitbang; | |
59 | struct completion done; | |
60 | ||
61 | void __iomem *regs; | |
62 | int irq; | |
63 | int len; | |
64 | int count; | |
65 | ||
bec0806c BD |
66 | struct fiq_handler fiq_handler; |
67 | enum spi_fiq_mode fiq_mode; | |
68 | unsigned char fiq_inuse; | |
69 | unsigned char fiq_claimed; | |
70 | ||
6c912a3d | 71 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
72 | int cs, int pol); |
73 | ||
7fba5340 BD |
74 | /* data buffers */ |
75 | const unsigned char *tx; | |
76 | unsigned char *rx; | |
77 | ||
78 | struct clk *clk; | |
7fba5340 BD |
79 | struct spi_master *master; |
80 | struct spi_device *curdev; | |
81 | struct device *dev; | |
82 | struct s3c2410_spi_info *pdata; | |
83 | }; | |
84 | ||
85 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
86 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
87 | ||
88 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
89 | { | |
90 | return spi_master_get_devdata(sdev->master); | |
91 | } | |
92 | ||
8736b927 BD |
93 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
94 | { | |
ee9c1fbf | 95 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
96 | } |
97 | ||
7fba5340 BD |
98 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
99 | { | |
570327d9 | 100 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
101 | struct s3c24xx_spi *hw = to_hw(spi); |
102 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
570327d9 BD |
103 | |
104 | /* change the chipselect state and the state of the spi engine clock */ | |
7fba5340 BD |
105 | |
106 | switch (value) { | |
107 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 108 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
570327d9 | 109 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
7fba5340 BD |
110 | break; |
111 | ||
112 | case BITBANG_CS_ACTIVE: | |
570327d9 BD |
113 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
114 | hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 115 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 | 116 | break; |
7fba5340 BD |
117 | } |
118 | } | |
119 | ||
570327d9 BD |
120 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
121 | struct spi_transfer *t) | |
7fba5340 BD |
122 | { |
123 | struct s3c24xx_spi *hw = to_hw(spi); | |
570327d9 | 124 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
125 | unsigned int hz; |
126 | unsigned int div; | |
b8978784 | 127 | unsigned long clk; |
7fba5340 | 128 | |
7fba5340 BD |
129 | hz = t ? t->speed_hz : spi->max_speed_hz; |
130 | ||
19152975 BD |
131 | if (!hz) |
132 | hz = spi->max_speed_hz; | |
133 | ||
570327d9 | 134 | if (spi->mode != cs->mode) { |
bec0806c | 135 | u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; |
570327d9 BD |
136 | |
137 | if (spi->mode & SPI_CPHA) | |
138 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
7fba5340 | 139 | |
570327d9 BD |
140 | if (spi->mode & SPI_CPOL) |
141 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
7fba5340 | 142 | |
570327d9 BD |
143 | cs->mode = spi->mode; |
144 | cs->spcon = spcon; | |
145 | } | |
b8978784 | 146 | |
570327d9 BD |
147 | if (cs->hz != hz) { |
148 | clk = clk_get_rate(hw->clk); | |
149 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
b8978784 | 150 | |
570327d9 BD |
151 | if (div > 255) |
152 | div = 255; | |
7fba5340 | 153 | |
570327d9 BD |
154 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
155 | div, hz, clk / (2 * (div + 1))); | |
156 | ||
157 | cs->hz = hz; | |
158 | cs->sppre = div; | |
7fba5340 | 159 | } |
7fba5340 BD |
160 | |
161 | return 0; | |
162 | } | |
163 | ||
570327d9 BD |
164 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
165 | struct spi_transfer *t) | |
166 | { | |
167 | struct s3c24xx_spi_devstate *cs = spi->controller_state; | |
168 | struct s3c24xx_spi *hw = to_hw(spi); | |
169 | int ret; | |
170 | ||
171 | ret = s3c24xx_spi_update_state(spi, t); | |
172 | if (!ret) | |
173 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
7fba5340 BD |
178 | static int s3c24xx_spi_setup(struct spi_device *spi) |
179 | { | |
570327d9 BD |
180 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
181 | struct s3c24xx_spi *hw = to_hw(spi); | |
7fba5340 BD |
182 | int ret; |
183 | ||
570327d9 BD |
184 | /* allocate settings on the first call */ |
185 | if (!cs) { | |
c586feba AL |
186 | cs = devm_kzalloc(&spi->dev, |
187 | sizeof(struct s3c24xx_spi_devstate), | |
188 | GFP_KERNEL); | |
570327d9 BD |
189 | if (!cs) { |
190 | dev_err(&spi->dev, "no memory for controller state\n"); | |
191 | return -ENOMEM; | |
192 | } | |
193 | ||
194 | cs->spcon = SPCON_DEFAULT; | |
195 | cs->hz = -1; | |
196 | spi->controller_state = cs; | |
197 | } | |
198 | ||
199 | /* initialise the state from the device */ | |
200 | ret = s3c24xx_spi_update_state(spi, NULL); | |
201 | if (ret) | |
7fba5340 | 202 | return ret; |
570327d9 BD |
203 | |
204 | spin_lock(&hw->bitbang.lock); | |
205 | if (!hw->bitbang.busy) { | |
206 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
207 | /* need to ndelay for 0.5 clocktick ? */ | |
7fba5340 | 208 | } |
570327d9 | 209 | spin_unlock(&hw->bitbang.lock); |
7fba5340 | 210 | |
7fba5340 BD |
211 | return 0; |
212 | } | |
213 | ||
214 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) | |
215 | { | |
4b1badf5 | 216 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
217 | } |
218 | ||
bec0806c BD |
219 | #ifdef CONFIG_SPI_S3C24XX_FIQ |
220 | /* Support for FIQ based pseudo-DMA to improve the transfer speed. | |
221 | * | |
222 | * This code uses the assembly helper in spi_s3c24xx_spi.S which is | |
223 | * used by the FIQ core to move data between main memory and the peripheral | |
224 | * block. Since this is code running on the processor, there is no problem | |
225 | * with cache coherency of the buffers, so we can use any buffer we like. | |
226 | */ | |
227 | ||
228 | /** | |
229 | * struct spi_fiq_code - FIQ code and header | |
230 | * @length: The length of the code fragment, excluding this header. | |
231 | * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at. | |
232 | * @data: The code itself to install as a FIQ handler. | |
233 | */ | |
234 | struct spi_fiq_code { | |
235 | u32 length; | |
236 | u32 ack_offset; | |
237 | u8 data[0]; | |
238 | }; | |
239 | ||
240 | extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; | |
241 | extern struct spi_fiq_code s3c24xx_spi_fiq_tx; | |
242 | extern struct spi_fiq_code s3c24xx_spi_fiq_rx; | |
243 | ||
244 | /** | |
245 | * ack_bit - turn IRQ into IRQ acknowledgement bit | |
246 | * @irq: The interrupt number | |
247 | * | |
248 | * Returns the bit to write to the interrupt acknowledge register. | |
249 | */ | |
250 | static inline u32 ack_bit(unsigned int irq) | |
251 | { | |
252 | return 1 << (irq - IRQ_EINT0); | |
253 | } | |
254 | ||
255 | /** | |
256 | * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer | |
257 | * @hw: The hardware state. | |
258 | * | |
259 | * Claim the FIQ handler (only one can be active at any one time) and | |
260 | * then setup the correct transfer code for this transfer. | |
261 | * | |
3ad2f3fb | 262 | * This call updates all the necessary state information if successful, |
bec0806c BD |
263 | * so the caller does not need to do anything more than start the transfer |
264 | * as normal, since the IRQ will have been re-routed to the FIQ handler. | |
265 | */ | |
cfeb3312 | 266 | static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) |
bec0806c BD |
267 | { |
268 | struct pt_regs regs; | |
269 | enum spi_fiq_mode mode; | |
270 | struct spi_fiq_code *code; | |
271 | int ret; | |
272 | ||
273 | if (!hw->fiq_claimed) { | |
274 | /* try and claim fiq if we haven't got it, and if not | |
275 | * then return and simply use another transfer method */ | |
276 | ||
277 | ret = claim_fiq(&hw->fiq_handler); | |
278 | if (ret) | |
279 | return; | |
280 | } | |
281 | ||
282 | if (hw->tx && !hw->rx) | |
283 | mode = FIQ_MODE_TX; | |
284 | else if (hw->rx && !hw->tx) | |
285 | mode = FIQ_MODE_RX; | |
286 | else | |
287 | mode = FIQ_MODE_TXRX; | |
288 | ||
289 | regs.uregs[fiq_rspi] = (long)hw->regs; | |
290 | regs.uregs[fiq_rrx] = (long)hw->rx; | |
291 | regs.uregs[fiq_rtx] = (long)hw->tx + 1; | |
292 | regs.uregs[fiq_rcount] = hw->len - 1; | |
293 | regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ; | |
294 | ||
295 | set_fiq_regs(®s); | |
296 | ||
297 | if (hw->fiq_mode != mode) { | |
298 | u32 *ack_ptr; | |
299 | ||
300 | hw->fiq_mode = mode; | |
301 | ||
302 | switch (mode) { | |
303 | case FIQ_MODE_TX: | |
304 | code = &s3c24xx_spi_fiq_tx; | |
305 | break; | |
306 | case FIQ_MODE_RX: | |
307 | code = &s3c24xx_spi_fiq_rx; | |
308 | break; | |
309 | case FIQ_MODE_TXRX: | |
310 | code = &s3c24xx_spi_fiq_txrx; | |
311 | break; | |
312 | default: | |
313 | code = NULL; | |
314 | } | |
315 | ||
316 | BUG_ON(!code); | |
317 | ||
318 | ack_ptr = (u32 *)&code->data[code->ack_offset]; | |
319 | *ack_ptr = ack_bit(hw->irq); | |
320 | ||
321 | set_fiq_handler(&code->data, code->length); | |
322 | } | |
323 | ||
324 | s3c24xx_set_fiq(hw->irq, true); | |
325 | ||
326 | hw->fiq_mode = mode; | |
327 | hw->fiq_inuse = 1; | |
328 | } | |
329 | ||
330 | /** | |
331 | * s3c24xx_spi_fiqop - FIQ core code callback | |
332 | * @pw: Data registered with the handler | |
333 | * @release: Whether this is a release or a return. | |
334 | * | |
335 | * Called by the FIQ code when another module wants to use the FIQ, so | |
336 | * return whether we are currently using this or not and then update our | |
337 | * internal state. | |
338 | */ | |
339 | static int s3c24xx_spi_fiqop(void *pw, int release) | |
340 | { | |
341 | struct s3c24xx_spi *hw = pw; | |
342 | int ret = 0; | |
343 | ||
344 | if (release) { | |
345 | if (hw->fiq_inuse) | |
346 | ret = -EBUSY; | |
347 | ||
348 | /* note, we do not need to unroute the FIQ, as the FIQ | |
349 | * vector code de-routes it to signal the end of transfer */ | |
350 | ||
351 | hw->fiq_mode = FIQ_MODE_NONE; | |
352 | hw->fiq_claimed = 0; | |
353 | } else { | |
354 | hw->fiq_claimed = 1; | |
355 | } | |
356 | ||
357 | return ret; | |
358 | } | |
359 | ||
360 | /** | |
361 | * s3c24xx_spi_initfiq - setup the information for the FIQ core | |
362 | * @hw: The hardware state. | |
363 | * | |
364 | * Setup the fiq_handler block to pass to the FIQ core. | |
365 | */ | |
366 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) | |
367 | { | |
368 | hw->fiq_handler.dev_id = hw; | |
369 | hw->fiq_handler.name = dev_name(hw->dev); | |
370 | hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; | |
371 | } | |
372 | ||
373 | /** | |
374 | * s3c24xx_spi_usefiq - return if we should be using FIQ. | |
375 | * @hw: The hardware state. | |
376 | * | |
377 | * Return true if the platform data specifies whether this channel is | |
378 | * allowed to use the FIQ. | |
379 | */ | |
380 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) | |
381 | { | |
382 | return hw->pdata->use_fiq; | |
383 | } | |
384 | ||
385 | /** | |
386 | * s3c24xx_spi_usingfiq - return if channel is using FIQ | |
387 | * @spi: The hardware state. | |
388 | * | |
389 | * Return whether the channel is currently using the FIQ (separate from | |
390 | * whether the FIQ is claimed). | |
391 | */ | |
392 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi) | |
393 | { | |
394 | return spi->fiq_inuse; | |
395 | } | |
396 | #else | |
397 | ||
398 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { } | |
399 | static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { } | |
400 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; } | |
401 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; } | |
402 | ||
403 | #endif /* CONFIG_SPI_S3C24XX_FIQ */ | |
404 | ||
7fba5340 BD |
405 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) |
406 | { | |
407 | struct s3c24xx_spi *hw = to_hw(spi); | |
408 | ||
7fba5340 BD |
409 | hw->tx = t->tx_buf; |
410 | hw->rx = t->rx_buf; | |
411 | hw->len = t->len; | |
412 | hw->count = 0; | |
413 | ||
4bb5eba0 BD |
414 | init_completion(&hw->done); |
415 | ||
bec0806c BD |
416 | hw->fiq_inuse = 0; |
417 | if (s3c24xx_spi_usefiq(hw) && t->len >= 3) | |
418 | s3c24xx_spi_tryfiq(hw); | |
419 | ||
7fba5340 BD |
420 | /* send the first byte */ |
421 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 422 | |
7fba5340 | 423 | wait_for_completion(&hw->done); |
7fba5340 BD |
424 | return hw->count; |
425 | } | |
426 | ||
7d12e780 | 427 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
428 | { |
429 | struct s3c24xx_spi *hw = dev; | |
430 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
431 | unsigned int count = hw->count; | |
432 | ||
433 | if (spsta & S3C2410_SPSTA_DCOL) { | |
434 | dev_dbg(hw->dev, "data-collision\n"); | |
435 | complete(&hw->done); | |
436 | goto irq_done; | |
437 | } | |
438 | ||
439 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
440 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
441 | complete(&hw->done); | |
442 | goto irq_done; | |
443 | } | |
444 | ||
bec0806c BD |
445 | if (!s3c24xx_spi_usingfiq(hw)) { |
446 | hw->count++; | |
7fba5340 | 447 | |
bec0806c BD |
448 | if (hw->rx) |
449 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 450 | |
bec0806c BD |
451 | count++; |
452 | ||
453 | if (count < hw->len) | |
454 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
455 | else | |
456 | complete(&hw->done); | |
457 | } else { | |
458 | hw->count = hw->len; | |
459 | hw->fiq_inuse = 0; | |
460 | ||
461 | if (hw->rx) | |
462 | hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 463 | |
7fba5340 | 464 | complete(&hw->done); |
bec0806c | 465 | } |
7fba5340 BD |
466 | |
467 | irq_done: | |
468 | return IRQ_HANDLED; | |
469 | } | |
470 | ||
5aa6cf30 BD |
471 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
472 | { | |
473 | /* for the moment, permanently enable the clock */ | |
474 | ||
475 | clk_enable(hw->clk); | |
476 | ||
477 | /* program defaults into the registers */ | |
478 | ||
479 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
480 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
481 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 482 | |
ee9c1fbf BD |
483 | if (hw->pdata) { |
484 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
485 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
486 | ||
487 | if (hw->pdata->gpio_setup) | |
488 | hw->pdata->gpio_setup(hw->pdata, 1); | |
489 | } | |
5aa6cf30 BD |
490 | } |
491 | ||
fd4a319b | 492 | static int s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 493 | { |
50f426b5 | 494 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
495 | struct s3c24xx_spi *hw; |
496 | struct spi_master *master; | |
7fba5340 BD |
497 | struct resource *res; |
498 | int err = 0; | |
7fba5340 BD |
499 | |
500 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
501 | if (master == NULL) { | |
502 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
c9f722e8 | 503 | return -ENOMEM; |
7fba5340 BD |
504 | } |
505 | ||
506 | hw = spi_master_get_devdata(master); | |
507 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
508 | ||
94c69f76 | 509 | hw->master = master; |
8074cf06 | 510 | hw->pdata = pdata = dev_get_platdata(&pdev->dev); |
7fba5340 BD |
511 | hw->dev = &pdev->dev; |
512 | ||
50f426b5 | 513 | if (pdata == NULL) { |
7fba5340 BD |
514 | dev_err(&pdev->dev, "No platform data supplied\n"); |
515 | err = -ENOENT; | |
516 | goto err_no_pdata; | |
517 | } | |
518 | ||
519 | platform_set_drvdata(pdev, hw); | |
520 | init_completion(&hw->done); | |
521 | ||
bec0806c BD |
522 | /* initialise fiq handler */ |
523 | ||
524 | s3c24xx_spi_initfiq(hw); | |
525 | ||
d1e77806 BD |
526 | /* setup the master state. */ |
527 | ||
e7db06b5 DB |
528 | /* the spi->mode bits understood by this driver: */ |
529 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
530 | ||
d1e77806 | 531 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 532 | master->bus_num = pdata->bus_num; |
08850fa9 | 533 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
d1e77806 | 534 | |
7fba5340 BD |
535 | /* setup the state for the bitbang driver */ |
536 | ||
537 | hw->bitbang.master = hw->master; | |
538 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
539 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
540 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
570327d9 BD |
541 | |
542 | hw->master->setup = s3c24xx_spi_setup; | |
7fba5340 BD |
543 | |
544 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
545 | ||
546 | /* find and map our resources */ | |
7fba5340 | 547 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9f722e8 JH |
548 | hw->regs = devm_ioremap_resource(&pdev->dev, res); |
549 | if (IS_ERR(hw->regs)) { | |
550 | err = PTR_ERR(hw->regs); | |
551 | goto err_no_pdata; | |
7fba5340 BD |
552 | } |
553 | ||
554 | hw->irq = platform_get_irq(pdev, 0); | |
555 | if (hw->irq < 0) { | |
556 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
557 | err = -ENOENT; | |
c9f722e8 | 558 | goto err_no_pdata; |
7fba5340 BD |
559 | } |
560 | ||
c9f722e8 JH |
561 | err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, |
562 | pdev->name, hw); | |
7fba5340 BD |
563 | if (err) { |
564 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
c9f722e8 | 565 | goto err_no_pdata; |
7fba5340 BD |
566 | } |
567 | ||
c9f722e8 | 568 | hw->clk = devm_clk_get(&pdev->dev, "spi"); |
7fba5340 BD |
569 | if (IS_ERR(hw->clk)) { |
570 | dev_err(&pdev->dev, "No clock for device\n"); | |
571 | err = PTR_ERR(hw->clk); | |
c9f722e8 | 572 | goto err_no_pdata; |
7fba5340 BD |
573 | } |
574 | ||
7fba5340 BD |
575 | /* setup any gpio we can */ |
576 | ||
50f426b5 | 577 | if (!pdata->set_cs) { |
ee9c1fbf BD |
578 | if (pdata->pin_cs < 0) { |
579 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
b2af045c | 580 | err = -EINVAL; |
ee9c1fbf BD |
581 | goto err_register; |
582 | } | |
8736b927 | 583 | |
c9f722e8 JH |
584 | err = devm_gpio_request(&pdev->dev, pdata->pin_cs, |
585 | dev_name(&pdev->dev)); | |
ee9c1fbf BD |
586 | if (err) { |
587 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
588 | goto err_register; | |
589 | } | |
590 | ||
591 | hw->set_cs = s3c24xx_spi_gpiocs; | |
592 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 593 | } else |
50f426b5 | 594 | hw->set_cs = pdata->set_cs; |
7fba5340 | 595 | |
ee9c1fbf BD |
596 | s3c24xx_spi_initialsetup(hw); |
597 | ||
7fba5340 BD |
598 | /* register our spi controller */ |
599 | ||
600 | err = spi_bitbang_start(&hw->bitbang); | |
601 | if (err) { | |
602 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
603 | goto err_register; | |
604 | } | |
605 | ||
7fba5340 BD |
606 | return 0; |
607 | ||
608 | err_register: | |
609 | clk_disable(hw->clk); | |
7fba5340 | 610 | |
7fba5340 | 611 | err_no_pdata: |
a419aef8 | 612 | spi_master_put(hw->master); |
7fba5340 BD |
613 | return err; |
614 | } | |
615 | ||
fd4a319b | 616 | static int s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
617 | { |
618 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
619 | ||
c6e7b8cb | 620 | spi_bitbang_stop(&hw->bitbang); |
7fba5340 | 621 | clk_disable(hw->clk); |
7fba5340 BD |
622 | spi_master_put(hw->master); |
623 | return 0; | |
624 | } | |
625 | ||
626 | ||
627 | #ifdef CONFIG_PM | |
628 | ||
6d613207 | 629 | static int s3c24xx_spi_suspend(struct device *dev) |
7fba5340 | 630 | { |
a1216394 | 631 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
38060371 AL |
632 | int ret; |
633 | ||
634 | ret = spi_master_suspend(hw->master); | |
635 | if (ret) | |
636 | return ret; | |
7fba5340 | 637 | |
cf46b973 BD |
638 | if (hw->pdata && hw->pdata->gpio_setup) |
639 | hw->pdata->gpio_setup(hw->pdata, 0); | |
640 | ||
7fba5340 BD |
641 | clk_disable(hw->clk); |
642 | return 0; | |
643 | } | |
644 | ||
6d613207 | 645 | static int s3c24xx_spi_resume(struct device *dev) |
7fba5340 | 646 | { |
a1216394 | 647 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
7fba5340 | 648 | |
5aa6cf30 | 649 | s3c24xx_spi_initialsetup(hw); |
38060371 | 650 | return spi_master_resume(hw->master); |
7fba5340 BD |
651 | } |
652 | ||
47145210 | 653 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
6d613207 BD |
654 | .suspend = s3c24xx_spi_suspend, |
655 | .resume = s3c24xx_spi_resume, | |
656 | }; | |
657 | ||
658 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops | |
7fba5340 | 659 | #else |
6d613207 BD |
660 | #define S3C24XX_SPI_PMOPS NULL |
661 | #endif /* CONFIG_PM */ | |
7fba5340 | 662 | |
7e38c3c4 | 663 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 664 | static struct platform_driver s3c24xx_spi_driver = { |
940ab889 | 665 | .probe = s3c24xx_spi_probe, |
fd4a319b | 666 | .remove = s3c24xx_spi_remove, |
7fba5340 BD |
667 | .driver = { |
668 | .name = "s3c2410-spi", | |
669 | .owner = THIS_MODULE, | |
6d613207 | 670 | .pm = S3C24XX_SPI_PMOPS, |
7fba5340 BD |
671 | }, |
672 | }; | |
940ab889 | 673 | module_platform_driver(s3c24xx_spi_driver); |
7fba5340 BD |
674 | |
675 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
676 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
677 | MODULE_LICENSE("GPL"); |