Commit | Line | Data |
---|---|---|
ca632f55 | 1 | /* |
7fba5340 | 2 | * Copyright (c) 2006 Ben Dooks |
bec0806c | 3 | * Copyright 2006-2009 Simtec Electronics |
7fba5340 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
7fba5340 BD |
12 | #include <linux/init.h> |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/workqueue.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
ee9c1fbf | 21 | #include <linux/gpio.h> |
1a0c220f | 22 | #include <linux/io.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7fba5340 BD |
24 | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/spi/spi_bitbang.h> | |
f35ef7ca | 27 | #include <linux/spi/s3c24xx.h> |
d7614de4 | 28 | #include <linux/module.h> |
7fba5340 | 29 | |
13622708 | 30 | #include <plat/regs-spi.h> |
7fba5340 | 31 | |
bec0806c BD |
32 | #include <asm/fiq.h> |
33 | ||
ca632f55 | 34 | #include "spi-s3c24xx-fiq.h" |
bec0806c | 35 | |
570327d9 BD |
36 | /** |
37 | * s3c24xx_spi_devstate - per device data | |
38 | * @hz: Last frequency calculated for @sppre field. | |
39 | * @mode: Last mode setting for the @spcon field. | |
40 | * @spcon: Value to write to the SPCON register. | |
41 | * @sppre: Value to write to the SPPRE register. | |
42 | */ | |
43 | struct s3c24xx_spi_devstate { | |
44 | unsigned int hz; | |
45 | unsigned int mode; | |
46 | u8 spcon; | |
47 | u8 sppre; | |
48 | }; | |
49 | ||
bec0806c BD |
50 | enum spi_fiq_mode { |
51 | FIQ_MODE_NONE = 0, | |
52 | FIQ_MODE_TX = 1, | |
53 | FIQ_MODE_RX = 2, | |
54 | FIQ_MODE_TXRX = 3, | |
55 | }; | |
56 | ||
7fba5340 BD |
57 | struct s3c24xx_spi { |
58 | /* bitbang has to be first */ | |
59 | struct spi_bitbang bitbang; | |
60 | struct completion done; | |
61 | ||
62 | void __iomem *regs; | |
63 | int irq; | |
64 | int len; | |
65 | int count; | |
66 | ||
bec0806c BD |
67 | struct fiq_handler fiq_handler; |
68 | enum spi_fiq_mode fiq_mode; | |
69 | unsigned char fiq_inuse; | |
70 | unsigned char fiq_claimed; | |
71 | ||
6c912a3d | 72 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
73 | int cs, int pol); |
74 | ||
7fba5340 BD |
75 | /* data buffers */ |
76 | const unsigned char *tx; | |
77 | unsigned char *rx; | |
78 | ||
79 | struct clk *clk; | |
7fba5340 BD |
80 | struct spi_master *master; |
81 | struct spi_device *curdev; | |
82 | struct device *dev; | |
83 | struct s3c2410_spi_info *pdata; | |
84 | }; | |
85 | ||
86 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
87 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
88 | ||
89 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
90 | { | |
91 | return spi_master_get_devdata(sdev->master); | |
92 | } | |
93 | ||
8736b927 BD |
94 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
95 | { | |
ee9c1fbf | 96 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
97 | } |
98 | ||
7fba5340 BD |
99 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
100 | { | |
570327d9 | 101 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
102 | struct s3c24xx_spi *hw = to_hw(spi); |
103 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
570327d9 BD |
104 | |
105 | /* change the chipselect state and the state of the spi engine clock */ | |
7fba5340 BD |
106 | |
107 | switch (value) { | |
108 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 109 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
570327d9 | 110 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
7fba5340 BD |
111 | break; |
112 | ||
113 | case BITBANG_CS_ACTIVE: | |
570327d9 BD |
114 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
115 | hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 116 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 | 117 | break; |
7fba5340 BD |
118 | } |
119 | } | |
120 | ||
570327d9 BD |
121 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
122 | struct spi_transfer *t) | |
7fba5340 BD |
123 | { |
124 | struct s3c24xx_spi *hw = to_hw(spi); | |
570327d9 | 125 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
126 | unsigned int bpw; |
127 | unsigned int hz; | |
128 | unsigned int div; | |
b8978784 | 129 | unsigned long clk; |
7fba5340 BD |
130 | |
131 | bpw = t ? t->bits_per_word : spi->bits_per_word; | |
132 | hz = t ? t->speed_hz : spi->max_speed_hz; | |
133 | ||
19152975 BD |
134 | if (!bpw) |
135 | bpw = 8; | |
136 | ||
137 | if (!hz) | |
138 | hz = spi->max_speed_hz; | |
139 | ||
7fba5340 BD |
140 | if (bpw != 8) { |
141 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw); | |
142 | return -EINVAL; | |
143 | } | |
144 | ||
570327d9 | 145 | if (spi->mode != cs->mode) { |
bec0806c | 146 | u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; |
570327d9 BD |
147 | |
148 | if (spi->mode & SPI_CPHA) | |
149 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
7fba5340 | 150 | |
570327d9 BD |
151 | if (spi->mode & SPI_CPOL) |
152 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
7fba5340 | 153 | |
570327d9 BD |
154 | cs->mode = spi->mode; |
155 | cs->spcon = spcon; | |
156 | } | |
b8978784 | 157 | |
570327d9 BD |
158 | if (cs->hz != hz) { |
159 | clk = clk_get_rate(hw->clk); | |
160 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
b8978784 | 161 | |
570327d9 BD |
162 | if (div > 255) |
163 | div = 255; | |
7fba5340 | 164 | |
570327d9 BD |
165 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
166 | div, hz, clk / (2 * (div + 1))); | |
167 | ||
168 | cs->hz = hz; | |
169 | cs->sppre = div; | |
7fba5340 | 170 | } |
7fba5340 BD |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
570327d9 BD |
175 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
176 | struct spi_transfer *t) | |
177 | { | |
178 | struct s3c24xx_spi_devstate *cs = spi->controller_state; | |
179 | struct s3c24xx_spi *hw = to_hw(spi); | |
180 | int ret; | |
181 | ||
182 | ret = s3c24xx_spi_update_state(spi, t); | |
183 | if (!ret) | |
184 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); | |
185 | ||
186 | return ret; | |
187 | } | |
188 | ||
7fba5340 BD |
189 | static int s3c24xx_spi_setup(struct spi_device *spi) |
190 | { | |
570327d9 BD |
191 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
192 | struct s3c24xx_spi *hw = to_hw(spi); | |
7fba5340 BD |
193 | int ret; |
194 | ||
570327d9 BD |
195 | /* allocate settings on the first call */ |
196 | if (!cs) { | |
197 | cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL); | |
198 | if (!cs) { | |
199 | dev_err(&spi->dev, "no memory for controller state\n"); | |
200 | return -ENOMEM; | |
201 | } | |
202 | ||
203 | cs->spcon = SPCON_DEFAULT; | |
204 | cs->hz = -1; | |
205 | spi->controller_state = cs; | |
206 | } | |
207 | ||
208 | /* initialise the state from the device */ | |
209 | ret = s3c24xx_spi_update_state(spi, NULL); | |
210 | if (ret) | |
7fba5340 | 211 | return ret; |
570327d9 BD |
212 | |
213 | spin_lock(&hw->bitbang.lock); | |
214 | if (!hw->bitbang.busy) { | |
215 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
216 | /* need to ndelay for 0.5 clocktick ? */ | |
7fba5340 | 217 | } |
570327d9 | 218 | spin_unlock(&hw->bitbang.lock); |
7fba5340 | 219 | |
7fba5340 BD |
220 | return 0; |
221 | } | |
222 | ||
570327d9 BD |
223 | static void s3c24xx_spi_cleanup(struct spi_device *spi) |
224 | { | |
225 | kfree(spi->controller_state); | |
226 | } | |
227 | ||
7fba5340 BD |
228 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) |
229 | { | |
4b1badf5 | 230 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
231 | } |
232 | ||
bec0806c BD |
233 | #ifdef CONFIG_SPI_S3C24XX_FIQ |
234 | /* Support for FIQ based pseudo-DMA to improve the transfer speed. | |
235 | * | |
236 | * This code uses the assembly helper in spi_s3c24xx_spi.S which is | |
237 | * used by the FIQ core to move data between main memory and the peripheral | |
238 | * block. Since this is code running on the processor, there is no problem | |
239 | * with cache coherency of the buffers, so we can use any buffer we like. | |
240 | */ | |
241 | ||
242 | /** | |
243 | * struct spi_fiq_code - FIQ code and header | |
244 | * @length: The length of the code fragment, excluding this header. | |
245 | * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at. | |
246 | * @data: The code itself to install as a FIQ handler. | |
247 | */ | |
248 | struct spi_fiq_code { | |
249 | u32 length; | |
250 | u32 ack_offset; | |
251 | u8 data[0]; | |
252 | }; | |
253 | ||
254 | extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; | |
255 | extern struct spi_fiq_code s3c24xx_spi_fiq_tx; | |
256 | extern struct spi_fiq_code s3c24xx_spi_fiq_rx; | |
257 | ||
258 | /** | |
259 | * ack_bit - turn IRQ into IRQ acknowledgement bit | |
260 | * @irq: The interrupt number | |
261 | * | |
262 | * Returns the bit to write to the interrupt acknowledge register. | |
263 | */ | |
264 | static inline u32 ack_bit(unsigned int irq) | |
265 | { | |
266 | return 1 << (irq - IRQ_EINT0); | |
267 | } | |
268 | ||
269 | /** | |
270 | * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer | |
271 | * @hw: The hardware state. | |
272 | * | |
273 | * Claim the FIQ handler (only one can be active at any one time) and | |
274 | * then setup the correct transfer code for this transfer. | |
275 | * | |
3ad2f3fb | 276 | * This call updates all the necessary state information if successful, |
bec0806c BD |
277 | * so the caller does not need to do anything more than start the transfer |
278 | * as normal, since the IRQ will have been re-routed to the FIQ handler. | |
279 | */ | |
cfeb3312 | 280 | static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) |
bec0806c BD |
281 | { |
282 | struct pt_regs regs; | |
283 | enum spi_fiq_mode mode; | |
284 | struct spi_fiq_code *code; | |
285 | int ret; | |
286 | ||
287 | if (!hw->fiq_claimed) { | |
288 | /* try and claim fiq if we haven't got it, and if not | |
289 | * then return and simply use another transfer method */ | |
290 | ||
291 | ret = claim_fiq(&hw->fiq_handler); | |
292 | if (ret) | |
293 | return; | |
294 | } | |
295 | ||
296 | if (hw->tx && !hw->rx) | |
297 | mode = FIQ_MODE_TX; | |
298 | else if (hw->rx && !hw->tx) | |
299 | mode = FIQ_MODE_RX; | |
300 | else | |
301 | mode = FIQ_MODE_TXRX; | |
302 | ||
303 | regs.uregs[fiq_rspi] = (long)hw->regs; | |
304 | regs.uregs[fiq_rrx] = (long)hw->rx; | |
305 | regs.uregs[fiq_rtx] = (long)hw->tx + 1; | |
306 | regs.uregs[fiq_rcount] = hw->len - 1; | |
307 | regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ; | |
308 | ||
309 | set_fiq_regs(®s); | |
310 | ||
311 | if (hw->fiq_mode != mode) { | |
312 | u32 *ack_ptr; | |
313 | ||
314 | hw->fiq_mode = mode; | |
315 | ||
316 | switch (mode) { | |
317 | case FIQ_MODE_TX: | |
318 | code = &s3c24xx_spi_fiq_tx; | |
319 | break; | |
320 | case FIQ_MODE_RX: | |
321 | code = &s3c24xx_spi_fiq_rx; | |
322 | break; | |
323 | case FIQ_MODE_TXRX: | |
324 | code = &s3c24xx_spi_fiq_txrx; | |
325 | break; | |
326 | default: | |
327 | code = NULL; | |
328 | } | |
329 | ||
330 | BUG_ON(!code); | |
331 | ||
332 | ack_ptr = (u32 *)&code->data[code->ack_offset]; | |
333 | *ack_ptr = ack_bit(hw->irq); | |
334 | ||
335 | set_fiq_handler(&code->data, code->length); | |
336 | } | |
337 | ||
338 | s3c24xx_set_fiq(hw->irq, true); | |
339 | ||
340 | hw->fiq_mode = mode; | |
341 | hw->fiq_inuse = 1; | |
342 | } | |
343 | ||
344 | /** | |
345 | * s3c24xx_spi_fiqop - FIQ core code callback | |
346 | * @pw: Data registered with the handler | |
347 | * @release: Whether this is a release or a return. | |
348 | * | |
349 | * Called by the FIQ code when another module wants to use the FIQ, so | |
350 | * return whether we are currently using this or not and then update our | |
351 | * internal state. | |
352 | */ | |
353 | static int s3c24xx_spi_fiqop(void *pw, int release) | |
354 | { | |
355 | struct s3c24xx_spi *hw = pw; | |
356 | int ret = 0; | |
357 | ||
358 | if (release) { | |
359 | if (hw->fiq_inuse) | |
360 | ret = -EBUSY; | |
361 | ||
362 | /* note, we do not need to unroute the FIQ, as the FIQ | |
363 | * vector code de-routes it to signal the end of transfer */ | |
364 | ||
365 | hw->fiq_mode = FIQ_MODE_NONE; | |
366 | hw->fiq_claimed = 0; | |
367 | } else { | |
368 | hw->fiq_claimed = 1; | |
369 | } | |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
374 | /** | |
375 | * s3c24xx_spi_initfiq - setup the information for the FIQ core | |
376 | * @hw: The hardware state. | |
377 | * | |
378 | * Setup the fiq_handler block to pass to the FIQ core. | |
379 | */ | |
380 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) | |
381 | { | |
382 | hw->fiq_handler.dev_id = hw; | |
383 | hw->fiq_handler.name = dev_name(hw->dev); | |
384 | hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; | |
385 | } | |
386 | ||
387 | /** | |
388 | * s3c24xx_spi_usefiq - return if we should be using FIQ. | |
389 | * @hw: The hardware state. | |
390 | * | |
391 | * Return true if the platform data specifies whether this channel is | |
392 | * allowed to use the FIQ. | |
393 | */ | |
394 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) | |
395 | { | |
396 | return hw->pdata->use_fiq; | |
397 | } | |
398 | ||
399 | /** | |
400 | * s3c24xx_spi_usingfiq - return if channel is using FIQ | |
401 | * @spi: The hardware state. | |
402 | * | |
403 | * Return whether the channel is currently using the FIQ (separate from | |
404 | * whether the FIQ is claimed). | |
405 | */ | |
406 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi) | |
407 | { | |
408 | return spi->fiq_inuse; | |
409 | } | |
410 | #else | |
411 | ||
412 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { } | |
413 | static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { } | |
414 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; } | |
415 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; } | |
416 | ||
417 | #endif /* CONFIG_SPI_S3C24XX_FIQ */ | |
418 | ||
7fba5340 BD |
419 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) |
420 | { | |
421 | struct s3c24xx_spi *hw = to_hw(spi); | |
422 | ||
7fba5340 BD |
423 | hw->tx = t->tx_buf; |
424 | hw->rx = t->rx_buf; | |
425 | hw->len = t->len; | |
426 | hw->count = 0; | |
427 | ||
4bb5eba0 BD |
428 | init_completion(&hw->done); |
429 | ||
bec0806c BD |
430 | hw->fiq_inuse = 0; |
431 | if (s3c24xx_spi_usefiq(hw) && t->len >= 3) | |
432 | s3c24xx_spi_tryfiq(hw); | |
433 | ||
7fba5340 BD |
434 | /* send the first byte */ |
435 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 436 | |
7fba5340 | 437 | wait_for_completion(&hw->done); |
7fba5340 BD |
438 | return hw->count; |
439 | } | |
440 | ||
7d12e780 | 441 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
442 | { |
443 | struct s3c24xx_spi *hw = dev; | |
444 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
445 | unsigned int count = hw->count; | |
446 | ||
447 | if (spsta & S3C2410_SPSTA_DCOL) { | |
448 | dev_dbg(hw->dev, "data-collision\n"); | |
449 | complete(&hw->done); | |
450 | goto irq_done; | |
451 | } | |
452 | ||
453 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
454 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
455 | complete(&hw->done); | |
456 | goto irq_done; | |
457 | } | |
458 | ||
bec0806c BD |
459 | if (!s3c24xx_spi_usingfiq(hw)) { |
460 | hw->count++; | |
7fba5340 | 461 | |
bec0806c BD |
462 | if (hw->rx) |
463 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 464 | |
bec0806c BD |
465 | count++; |
466 | ||
467 | if (count < hw->len) | |
468 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
469 | else | |
470 | complete(&hw->done); | |
471 | } else { | |
472 | hw->count = hw->len; | |
473 | hw->fiq_inuse = 0; | |
474 | ||
475 | if (hw->rx) | |
476 | hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 477 | |
7fba5340 | 478 | complete(&hw->done); |
bec0806c | 479 | } |
7fba5340 BD |
480 | |
481 | irq_done: | |
482 | return IRQ_HANDLED; | |
483 | } | |
484 | ||
5aa6cf30 BD |
485 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
486 | { | |
487 | /* for the moment, permanently enable the clock */ | |
488 | ||
489 | clk_enable(hw->clk); | |
490 | ||
491 | /* program defaults into the registers */ | |
492 | ||
493 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
494 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
495 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 496 | |
ee9c1fbf BD |
497 | if (hw->pdata) { |
498 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
499 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
500 | ||
501 | if (hw->pdata->gpio_setup) | |
502 | hw->pdata->gpio_setup(hw->pdata, 1); | |
503 | } | |
5aa6cf30 BD |
504 | } |
505 | ||
fd4a319b | 506 | static int s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 507 | { |
50f426b5 | 508 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
509 | struct s3c24xx_spi *hw; |
510 | struct spi_master *master; | |
7fba5340 BD |
511 | struct resource *res; |
512 | int err = 0; | |
7fba5340 BD |
513 | |
514 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
515 | if (master == NULL) { | |
516 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
c9f722e8 | 517 | return -ENOMEM; |
7fba5340 BD |
518 | } |
519 | ||
520 | hw = spi_master_get_devdata(master); | |
521 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
522 | ||
94c69f76 | 523 | hw->master = master; |
8074cf06 | 524 | hw->pdata = pdata = dev_get_platdata(&pdev->dev); |
7fba5340 BD |
525 | hw->dev = &pdev->dev; |
526 | ||
50f426b5 | 527 | if (pdata == NULL) { |
7fba5340 BD |
528 | dev_err(&pdev->dev, "No platform data supplied\n"); |
529 | err = -ENOENT; | |
530 | goto err_no_pdata; | |
531 | } | |
532 | ||
533 | platform_set_drvdata(pdev, hw); | |
534 | init_completion(&hw->done); | |
535 | ||
bec0806c BD |
536 | /* initialise fiq handler */ |
537 | ||
538 | s3c24xx_spi_initfiq(hw); | |
539 | ||
d1e77806 BD |
540 | /* setup the master state. */ |
541 | ||
e7db06b5 DB |
542 | /* the spi->mode bits understood by this driver: */ |
543 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
544 | ||
d1e77806 | 545 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 546 | master->bus_num = pdata->bus_num; |
d1e77806 | 547 | |
7fba5340 BD |
548 | /* setup the state for the bitbang driver */ |
549 | ||
550 | hw->bitbang.master = hw->master; | |
551 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
552 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
553 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
570327d9 BD |
554 | |
555 | hw->master->setup = s3c24xx_spi_setup; | |
556 | hw->master->cleanup = s3c24xx_spi_cleanup; | |
7fba5340 BD |
557 | |
558 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
559 | ||
560 | /* find and map our resources */ | |
7fba5340 | 561 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9f722e8 JH |
562 | hw->regs = devm_ioremap_resource(&pdev->dev, res); |
563 | if (IS_ERR(hw->regs)) { | |
564 | err = PTR_ERR(hw->regs); | |
565 | goto err_no_pdata; | |
7fba5340 BD |
566 | } |
567 | ||
568 | hw->irq = platform_get_irq(pdev, 0); | |
569 | if (hw->irq < 0) { | |
570 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
571 | err = -ENOENT; | |
c9f722e8 | 572 | goto err_no_pdata; |
7fba5340 BD |
573 | } |
574 | ||
c9f722e8 JH |
575 | err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, |
576 | pdev->name, hw); | |
7fba5340 BD |
577 | if (err) { |
578 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
c9f722e8 | 579 | goto err_no_pdata; |
7fba5340 BD |
580 | } |
581 | ||
c9f722e8 | 582 | hw->clk = devm_clk_get(&pdev->dev, "spi"); |
7fba5340 BD |
583 | if (IS_ERR(hw->clk)) { |
584 | dev_err(&pdev->dev, "No clock for device\n"); | |
585 | err = PTR_ERR(hw->clk); | |
c9f722e8 | 586 | goto err_no_pdata; |
7fba5340 BD |
587 | } |
588 | ||
7fba5340 BD |
589 | /* setup any gpio we can */ |
590 | ||
50f426b5 | 591 | if (!pdata->set_cs) { |
ee9c1fbf BD |
592 | if (pdata->pin_cs < 0) { |
593 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
b2af045c | 594 | err = -EINVAL; |
ee9c1fbf BD |
595 | goto err_register; |
596 | } | |
8736b927 | 597 | |
c9f722e8 JH |
598 | err = devm_gpio_request(&pdev->dev, pdata->pin_cs, |
599 | dev_name(&pdev->dev)); | |
ee9c1fbf BD |
600 | if (err) { |
601 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
602 | goto err_register; | |
603 | } | |
604 | ||
605 | hw->set_cs = s3c24xx_spi_gpiocs; | |
606 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 607 | } else |
50f426b5 | 608 | hw->set_cs = pdata->set_cs; |
7fba5340 | 609 | |
ee9c1fbf BD |
610 | s3c24xx_spi_initialsetup(hw); |
611 | ||
7fba5340 BD |
612 | /* register our spi controller */ |
613 | ||
614 | err = spi_bitbang_start(&hw->bitbang); | |
615 | if (err) { | |
616 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
617 | goto err_register; | |
618 | } | |
619 | ||
7fba5340 BD |
620 | return 0; |
621 | ||
622 | err_register: | |
623 | clk_disable(hw->clk); | |
7fba5340 | 624 | |
7fba5340 | 625 | err_no_pdata: |
a419aef8 | 626 | spi_master_put(hw->master); |
7fba5340 BD |
627 | return err; |
628 | } | |
629 | ||
fd4a319b | 630 | static int s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
631 | { |
632 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
633 | ||
c6e7b8cb | 634 | spi_bitbang_stop(&hw->bitbang); |
7fba5340 | 635 | clk_disable(hw->clk); |
7fba5340 BD |
636 | spi_master_put(hw->master); |
637 | return 0; | |
638 | } | |
639 | ||
640 | ||
641 | #ifdef CONFIG_PM | |
642 | ||
6d613207 | 643 | static int s3c24xx_spi_suspend(struct device *dev) |
7fba5340 | 644 | { |
a1216394 | 645 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
7fba5340 | 646 | |
cf46b973 BD |
647 | if (hw->pdata && hw->pdata->gpio_setup) |
648 | hw->pdata->gpio_setup(hw->pdata, 0); | |
649 | ||
7fba5340 BD |
650 | clk_disable(hw->clk); |
651 | return 0; | |
652 | } | |
653 | ||
6d613207 | 654 | static int s3c24xx_spi_resume(struct device *dev) |
7fba5340 | 655 | { |
a1216394 | 656 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
7fba5340 | 657 | |
5aa6cf30 | 658 | s3c24xx_spi_initialsetup(hw); |
7fba5340 BD |
659 | return 0; |
660 | } | |
661 | ||
47145210 | 662 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
6d613207 BD |
663 | .suspend = s3c24xx_spi_suspend, |
664 | .resume = s3c24xx_spi_resume, | |
665 | }; | |
666 | ||
667 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops | |
7fba5340 | 668 | #else |
6d613207 BD |
669 | #define S3C24XX_SPI_PMOPS NULL |
670 | #endif /* CONFIG_PM */ | |
7fba5340 | 671 | |
7e38c3c4 | 672 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 673 | static struct platform_driver s3c24xx_spi_driver = { |
940ab889 | 674 | .probe = s3c24xx_spi_probe, |
fd4a319b | 675 | .remove = s3c24xx_spi_remove, |
7fba5340 BD |
676 | .driver = { |
677 | .name = "s3c2410-spi", | |
678 | .owner = THIS_MODULE, | |
6d613207 | 679 | .pm = S3C24XX_SPI_PMOPS, |
7fba5340 BD |
680 | }, |
681 | }; | |
940ab889 | 682 | module_platform_driver(s3c24xx_spi_driver); |
7fba5340 BD |
683 | |
684 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
685 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
686 | MODULE_LICENSE("GPL"); |