Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ca632f55 | 2 | /* |
7fba5340 | 3 | * Copyright (c) 2006 Ben Dooks |
bec0806c | 4 | * Copyright 2006-2009 Simtec Electronics |
7fba5340 | 5 | * Ben Dooks <ben@simtec.co.uk> |
7fba5340 BD |
6 | */ |
7 | ||
7fba5340 | 8 | #include <linux/spinlock.h> |
7fba5340 BD |
9 | #include <linux/interrupt.h> |
10 | #include <linux/delay.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/platform_device.h> | |
ee9c1fbf | 15 | #include <linux/gpio.h> |
1a0c220f | 16 | #include <linux/io.h> |
5a0e3ad6 | 17 | #include <linux/slab.h> |
7fba5340 BD |
18 | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/spi/spi_bitbang.h> | |
f35ef7ca | 21 | #include <linux/spi/s3c24xx.h> |
d7614de4 | 22 | #include <linux/module.h> |
7fba5340 | 23 | |
13622708 | 24 | #include <plat/regs-spi.h> |
7fba5340 | 25 | |
bec0806c BD |
26 | #include <asm/fiq.h> |
27 | ||
ca632f55 | 28 | #include "spi-s3c24xx-fiq.h" |
bec0806c | 29 | |
570327d9 BD |
30 | /** |
31 | * s3c24xx_spi_devstate - per device data | |
32 | * @hz: Last frequency calculated for @sppre field. | |
33 | * @mode: Last mode setting for the @spcon field. | |
34 | * @spcon: Value to write to the SPCON register. | |
35 | * @sppre: Value to write to the SPPRE register. | |
36 | */ | |
37 | struct s3c24xx_spi_devstate { | |
38 | unsigned int hz; | |
39 | unsigned int mode; | |
40 | u8 spcon; | |
41 | u8 sppre; | |
42 | }; | |
43 | ||
bec0806c BD |
44 | enum spi_fiq_mode { |
45 | FIQ_MODE_NONE = 0, | |
46 | FIQ_MODE_TX = 1, | |
47 | FIQ_MODE_RX = 2, | |
48 | FIQ_MODE_TXRX = 3, | |
49 | }; | |
50 | ||
7fba5340 BD |
51 | struct s3c24xx_spi { |
52 | /* bitbang has to be first */ | |
53 | struct spi_bitbang bitbang; | |
54 | struct completion done; | |
55 | ||
56 | void __iomem *regs; | |
57 | int irq; | |
58 | int len; | |
59 | int count; | |
60 | ||
bec0806c BD |
61 | struct fiq_handler fiq_handler; |
62 | enum spi_fiq_mode fiq_mode; | |
63 | unsigned char fiq_inuse; | |
64 | unsigned char fiq_claimed; | |
65 | ||
6c912a3d | 66 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
67 | int cs, int pol); |
68 | ||
7fba5340 BD |
69 | /* data buffers */ |
70 | const unsigned char *tx; | |
71 | unsigned char *rx; | |
72 | ||
73 | struct clk *clk; | |
7fba5340 BD |
74 | struct spi_master *master; |
75 | struct spi_device *curdev; | |
76 | struct device *dev; | |
77 | struct s3c2410_spi_info *pdata; | |
78 | }; | |
79 | ||
80 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
81 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
82 | ||
83 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
84 | { | |
85 | return spi_master_get_devdata(sdev->master); | |
86 | } | |
87 | ||
8736b927 BD |
88 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
89 | { | |
ee9c1fbf | 90 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
91 | } |
92 | ||
7fba5340 BD |
93 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
94 | { | |
570327d9 | 95 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
96 | struct s3c24xx_spi *hw = to_hw(spi); |
97 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
570327d9 BD |
98 | |
99 | /* change the chipselect state and the state of the spi engine clock */ | |
7fba5340 BD |
100 | |
101 | switch (value) { | |
102 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 103 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
570327d9 | 104 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
7fba5340 BD |
105 | break; |
106 | ||
107 | case BITBANG_CS_ACTIVE: | |
570327d9 BD |
108 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
109 | hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 110 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 | 111 | break; |
7fba5340 BD |
112 | } |
113 | } | |
114 | ||
570327d9 BD |
115 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
116 | struct spi_transfer *t) | |
7fba5340 BD |
117 | { |
118 | struct s3c24xx_spi *hw = to_hw(spi); | |
570327d9 | 119 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
120 | unsigned int hz; |
121 | unsigned int div; | |
b8978784 | 122 | unsigned long clk; |
7fba5340 | 123 | |
7fba5340 BD |
124 | hz = t ? t->speed_hz : spi->max_speed_hz; |
125 | ||
19152975 BD |
126 | if (!hz) |
127 | hz = spi->max_speed_hz; | |
128 | ||
570327d9 | 129 | if (spi->mode != cs->mode) { |
bec0806c | 130 | u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; |
570327d9 BD |
131 | |
132 | if (spi->mode & SPI_CPHA) | |
133 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
7fba5340 | 134 | |
570327d9 BD |
135 | if (spi->mode & SPI_CPOL) |
136 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
7fba5340 | 137 | |
570327d9 BD |
138 | cs->mode = spi->mode; |
139 | cs->spcon = spcon; | |
140 | } | |
b8978784 | 141 | |
570327d9 BD |
142 | if (cs->hz != hz) { |
143 | clk = clk_get_rate(hw->clk); | |
144 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
b8978784 | 145 | |
570327d9 BD |
146 | if (div > 255) |
147 | div = 255; | |
7fba5340 | 148 | |
570327d9 BD |
149 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
150 | div, hz, clk / (2 * (div + 1))); | |
151 | ||
152 | cs->hz = hz; | |
153 | cs->sppre = div; | |
7fba5340 | 154 | } |
7fba5340 BD |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
570327d9 BD |
159 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
160 | struct spi_transfer *t) | |
161 | { | |
162 | struct s3c24xx_spi_devstate *cs = spi->controller_state; | |
163 | struct s3c24xx_spi *hw = to_hw(spi); | |
164 | int ret; | |
165 | ||
166 | ret = s3c24xx_spi_update_state(spi, t); | |
167 | if (!ret) | |
168 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); | |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
7fba5340 BD |
173 | static int s3c24xx_spi_setup(struct spi_device *spi) |
174 | { | |
570327d9 BD |
175 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
176 | struct s3c24xx_spi *hw = to_hw(spi); | |
7fba5340 BD |
177 | int ret; |
178 | ||
570327d9 BD |
179 | /* allocate settings on the first call */ |
180 | if (!cs) { | |
c586feba AL |
181 | cs = devm_kzalloc(&spi->dev, |
182 | sizeof(struct s3c24xx_spi_devstate), | |
183 | GFP_KERNEL); | |
0375cff5 | 184 | if (!cs) |
570327d9 | 185 | return -ENOMEM; |
570327d9 BD |
186 | |
187 | cs->spcon = SPCON_DEFAULT; | |
188 | cs->hz = -1; | |
189 | spi->controller_state = cs; | |
190 | } | |
191 | ||
192 | /* initialise the state from the device */ | |
193 | ret = s3c24xx_spi_update_state(spi, NULL); | |
194 | if (ret) | |
7fba5340 | 195 | return ret; |
570327d9 | 196 | |
c15f6ed3 | 197 | mutex_lock(&hw->bitbang.lock); |
570327d9 BD |
198 | if (!hw->bitbang.busy) { |
199 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
200 | /* need to ndelay for 0.5 clocktick ? */ | |
7fba5340 | 201 | } |
c15f6ed3 | 202 | mutex_unlock(&hw->bitbang.lock); |
7fba5340 | 203 | |
7fba5340 BD |
204 | return 0; |
205 | } | |
206 | ||
207 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) | |
208 | { | |
4b1badf5 | 209 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
210 | } |
211 | ||
bec0806c BD |
212 | #ifdef CONFIG_SPI_S3C24XX_FIQ |
213 | /* Support for FIQ based pseudo-DMA to improve the transfer speed. | |
214 | * | |
215 | * This code uses the assembly helper in spi_s3c24xx_spi.S which is | |
216 | * used by the FIQ core to move data between main memory and the peripheral | |
217 | * block. Since this is code running on the processor, there is no problem | |
218 | * with cache coherency of the buffers, so we can use any buffer we like. | |
219 | */ | |
220 | ||
221 | /** | |
222 | * struct spi_fiq_code - FIQ code and header | |
223 | * @length: The length of the code fragment, excluding this header. | |
224 | * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at. | |
225 | * @data: The code itself to install as a FIQ handler. | |
226 | */ | |
227 | struct spi_fiq_code { | |
228 | u32 length; | |
229 | u32 ack_offset; | |
230 | u8 data[0]; | |
231 | }; | |
232 | ||
233 | extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; | |
234 | extern struct spi_fiq_code s3c24xx_spi_fiq_tx; | |
235 | extern struct spi_fiq_code s3c24xx_spi_fiq_rx; | |
236 | ||
237 | /** | |
238 | * ack_bit - turn IRQ into IRQ acknowledgement bit | |
239 | * @irq: The interrupt number | |
240 | * | |
241 | * Returns the bit to write to the interrupt acknowledge register. | |
242 | */ | |
243 | static inline u32 ack_bit(unsigned int irq) | |
244 | { | |
245 | return 1 << (irq - IRQ_EINT0); | |
246 | } | |
247 | ||
248 | /** | |
249 | * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer | |
250 | * @hw: The hardware state. | |
251 | * | |
252 | * Claim the FIQ handler (only one can be active at any one time) and | |
253 | * then setup the correct transfer code for this transfer. | |
254 | * | |
3ad2f3fb | 255 | * This call updates all the necessary state information if successful, |
bec0806c BD |
256 | * so the caller does not need to do anything more than start the transfer |
257 | * as normal, since the IRQ will have been re-routed to the FIQ handler. | |
258 | */ | |
cfeb3312 | 259 | static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) |
bec0806c BD |
260 | { |
261 | struct pt_regs regs; | |
262 | enum spi_fiq_mode mode; | |
263 | struct spi_fiq_code *code; | |
264 | int ret; | |
265 | ||
266 | if (!hw->fiq_claimed) { | |
267 | /* try and claim fiq if we haven't got it, and if not | |
268 | * then return and simply use another transfer method */ | |
269 | ||
270 | ret = claim_fiq(&hw->fiq_handler); | |
271 | if (ret) | |
272 | return; | |
273 | } | |
274 | ||
275 | if (hw->tx && !hw->rx) | |
276 | mode = FIQ_MODE_TX; | |
277 | else if (hw->rx && !hw->tx) | |
278 | mode = FIQ_MODE_RX; | |
279 | else | |
280 | mode = FIQ_MODE_TXRX; | |
281 | ||
282 | regs.uregs[fiq_rspi] = (long)hw->regs; | |
283 | regs.uregs[fiq_rrx] = (long)hw->rx; | |
284 | regs.uregs[fiq_rtx] = (long)hw->tx + 1; | |
285 | regs.uregs[fiq_rcount] = hw->len - 1; | |
286 | regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ; | |
287 | ||
288 | set_fiq_regs(®s); | |
289 | ||
290 | if (hw->fiq_mode != mode) { | |
291 | u32 *ack_ptr; | |
292 | ||
293 | hw->fiq_mode = mode; | |
294 | ||
295 | switch (mode) { | |
296 | case FIQ_MODE_TX: | |
297 | code = &s3c24xx_spi_fiq_tx; | |
298 | break; | |
299 | case FIQ_MODE_RX: | |
300 | code = &s3c24xx_spi_fiq_rx; | |
301 | break; | |
302 | case FIQ_MODE_TXRX: | |
303 | code = &s3c24xx_spi_fiq_txrx; | |
304 | break; | |
305 | default: | |
306 | code = NULL; | |
307 | } | |
308 | ||
309 | BUG_ON(!code); | |
310 | ||
311 | ack_ptr = (u32 *)&code->data[code->ack_offset]; | |
312 | *ack_ptr = ack_bit(hw->irq); | |
313 | ||
314 | set_fiq_handler(&code->data, code->length); | |
315 | } | |
316 | ||
317 | s3c24xx_set_fiq(hw->irq, true); | |
318 | ||
319 | hw->fiq_mode = mode; | |
320 | hw->fiq_inuse = 1; | |
321 | } | |
322 | ||
323 | /** | |
324 | * s3c24xx_spi_fiqop - FIQ core code callback | |
325 | * @pw: Data registered with the handler | |
326 | * @release: Whether this is a release or a return. | |
327 | * | |
328 | * Called by the FIQ code when another module wants to use the FIQ, so | |
329 | * return whether we are currently using this or not and then update our | |
330 | * internal state. | |
331 | */ | |
332 | static int s3c24xx_spi_fiqop(void *pw, int release) | |
333 | { | |
334 | struct s3c24xx_spi *hw = pw; | |
335 | int ret = 0; | |
336 | ||
337 | if (release) { | |
338 | if (hw->fiq_inuse) | |
339 | ret = -EBUSY; | |
340 | ||
341 | /* note, we do not need to unroute the FIQ, as the FIQ | |
342 | * vector code de-routes it to signal the end of transfer */ | |
343 | ||
344 | hw->fiq_mode = FIQ_MODE_NONE; | |
345 | hw->fiq_claimed = 0; | |
346 | } else { | |
347 | hw->fiq_claimed = 1; | |
348 | } | |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
353 | /** | |
354 | * s3c24xx_spi_initfiq - setup the information for the FIQ core | |
355 | * @hw: The hardware state. | |
356 | * | |
357 | * Setup the fiq_handler block to pass to the FIQ core. | |
358 | */ | |
359 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) | |
360 | { | |
361 | hw->fiq_handler.dev_id = hw; | |
362 | hw->fiq_handler.name = dev_name(hw->dev); | |
363 | hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; | |
364 | } | |
365 | ||
366 | /** | |
367 | * s3c24xx_spi_usefiq - return if we should be using FIQ. | |
368 | * @hw: The hardware state. | |
369 | * | |
370 | * Return true if the platform data specifies whether this channel is | |
371 | * allowed to use the FIQ. | |
372 | */ | |
373 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) | |
374 | { | |
375 | return hw->pdata->use_fiq; | |
376 | } | |
377 | ||
378 | /** | |
379 | * s3c24xx_spi_usingfiq - return if channel is using FIQ | |
380 | * @spi: The hardware state. | |
381 | * | |
382 | * Return whether the channel is currently using the FIQ (separate from | |
383 | * whether the FIQ is claimed). | |
384 | */ | |
385 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi) | |
386 | { | |
387 | return spi->fiq_inuse; | |
388 | } | |
389 | #else | |
390 | ||
391 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { } | |
392 | static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { } | |
393 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; } | |
394 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; } | |
395 | ||
396 | #endif /* CONFIG_SPI_S3C24XX_FIQ */ | |
397 | ||
7fba5340 BD |
398 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) |
399 | { | |
400 | struct s3c24xx_spi *hw = to_hw(spi); | |
401 | ||
7fba5340 BD |
402 | hw->tx = t->tx_buf; |
403 | hw->rx = t->rx_buf; | |
404 | hw->len = t->len; | |
405 | hw->count = 0; | |
406 | ||
4bb5eba0 BD |
407 | init_completion(&hw->done); |
408 | ||
bec0806c BD |
409 | hw->fiq_inuse = 0; |
410 | if (s3c24xx_spi_usefiq(hw) && t->len >= 3) | |
411 | s3c24xx_spi_tryfiq(hw); | |
412 | ||
7fba5340 BD |
413 | /* send the first byte */ |
414 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 415 | |
7fba5340 | 416 | wait_for_completion(&hw->done); |
7fba5340 BD |
417 | return hw->count; |
418 | } | |
419 | ||
7d12e780 | 420 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
421 | { |
422 | struct s3c24xx_spi *hw = dev; | |
423 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
424 | unsigned int count = hw->count; | |
425 | ||
426 | if (spsta & S3C2410_SPSTA_DCOL) { | |
427 | dev_dbg(hw->dev, "data-collision\n"); | |
428 | complete(&hw->done); | |
429 | goto irq_done; | |
430 | } | |
431 | ||
432 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
433 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
434 | complete(&hw->done); | |
435 | goto irq_done; | |
436 | } | |
437 | ||
bec0806c BD |
438 | if (!s3c24xx_spi_usingfiq(hw)) { |
439 | hw->count++; | |
7fba5340 | 440 | |
bec0806c BD |
441 | if (hw->rx) |
442 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 443 | |
bec0806c BD |
444 | count++; |
445 | ||
446 | if (count < hw->len) | |
447 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
448 | else | |
449 | complete(&hw->done); | |
450 | } else { | |
451 | hw->count = hw->len; | |
452 | hw->fiq_inuse = 0; | |
453 | ||
454 | if (hw->rx) | |
455 | hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 456 | |
7fba5340 | 457 | complete(&hw->done); |
bec0806c | 458 | } |
7fba5340 BD |
459 | |
460 | irq_done: | |
461 | return IRQ_HANDLED; | |
462 | } | |
463 | ||
5aa6cf30 BD |
464 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
465 | { | |
466 | /* for the moment, permanently enable the clock */ | |
467 | ||
468 | clk_enable(hw->clk); | |
469 | ||
470 | /* program defaults into the registers */ | |
471 | ||
472 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
473 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
474 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 475 | |
ee9c1fbf BD |
476 | if (hw->pdata) { |
477 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
478 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
479 | ||
480 | if (hw->pdata->gpio_setup) | |
481 | hw->pdata->gpio_setup(hw->pdata, 1); | |
482 | } | |
5aa6cf30 BD |
483 | } |
484 | ||
fd4a319b | 485 | static int s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 486 | { |
50f426b5 | 487 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
488 | struct s3c24xx_spi *hw; |
489 | struct spi_master *master; | |
7fba5340 BD |
490 | struct resource *res; |
491 | int err = 0; | |
7fba5340 BD |
492 | |
493 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
494 | if (master == NULL) { | |
495 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
c9f722e8 | 496 | return -ENOMEM; |
7fba5340 BD |
497 | } |
498 | ||
499 | hw = spi_master_get_devdata(master); | |
7fba5340 | 500 | |
94c69f76 | 501 | hw->master = master; |
8074cf06 | 502 | hw->pdata = pdata = dev_get_platdata(&pdev->dev); |
7fba5340 BD |
503 | hw->dev = &pdev->dev; |
504 | ||
50f426b5 | 505 | if (pdata == NULL) { |
7fba5340 BD |
506 | dev_err(&pdev->dev, "No platform data supplied\n"); |
507 | err = -ENOENT; | |
508 | goto err_no_pdata; | |
509 | } | |
510 | ||
511 | platform_set_drvdata(pdev, hw); | |
512 | init_completion(&hw->done); | |
513 | ||
bec0806c BD |
514 | /* initialise fiq handler */ |
515 | ||
516 | s3c24xx_spi_initfiq(hw); | |
517 | ||
d1e77806 BD |
518 | /* setup the master state. */ |
519 | ||
e7db06b5 DB |
520 | /* the spi->mode bits understood by this driver: */ |
521 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
522 | ||
d1e77806 | 523 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 524 | master->bus_num = pdata->bus_num; |
08850fa9 | 525 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
d1e77806 | 526 | |
7fba5340 BD |
527 | /* setup the state for the bitbang driver */ |
528 | ||
529 | hw->bitbang.master = hw->master; | |
530 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
531 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
532 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
570327d9 BD |
533 | |
534 | hw->master->setup = s3c24xx_spi_setup; | |
7fba5340 BD |
535 | |
536 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
537 | ||
538 | /* find and map our resources */ | |
7fba5340 | 539 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9f722e8 JH |
540 | hw->regs = devm_ioremap_resource(&pdev->dev, res); |
541 | if (IS_ERR(hw->regs)) { | |
542 | err = PTR_ERR(hw->regs); | |
543 | goto err_no_pdata; | |
7fba5340 BD |
544 | } |
545 | ||
546 | hw->irq = platform_get_irq(pdev, 0); | |
547 | if (hw->irq < 0) { | |
548 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
549 | err = -ENOENT; | |
c9f722e8 | 550 | goto err_no_pdata; |
7fba5340 BD |
551 | } |
552 | ||
c9f722e8 JH |
553 | err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, |
554 | pdev->name, hw); | |
7fba5340 BD |
555 | if (err) { |
556 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
c9f722e8 | 557 | goto err_no_pdata; |
7fba5340 BD |
558 | } |
559 | ||
c9f722e8 | 560 | hw->clk = devm_clk_get(&pdev->dev, "spi"); |
7fba5340 BD |
561 | if (IS_ERR(hw->clk)) { |
562 | dev_err(&pdev->dev, "No clock for device\n"); | |
563 | err = PTR_ERR(hw->clk); | |
c9f722e8 | 564 | goto err_no_pdata; |
7fba5340 BD |
565 | } |
566 | ||
7fba5340 BD |
567 | /* setup any gpio we can */ |
568 | ||
50f426b5 | 569 | if (!pdata->set_cs) { |
ee9c1fbf BD |
570 | if (pdata->pin_cs < 0) { |
571 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
b2af045c | 572 | err = -EINVAL; |
ee9c1fbf BD |
573 | goto err_register; |
574 | } | |
8736b927 | 575 | |
c9f722e8 JH |
576 | err = devm_gpio_request(&pdev->dev, pdata->pin_cs, |
577 | dev_name(&pdev->dev)); | |
ee9c1fbf BD |
578 | if (err) { |
579 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
580 | goto err_register; | |
581 | } | |
582 | ||
583 | hw->set_cs = s3c24xx_spi_gpiocs; | |
584 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 585 | } else |
50f426b5 | 586 | hw->set_cs = pdata->set_cs; |
7fba5340 | 587 | |
ee9c1fbf BD |
588 | s3c24xx_spi_initialsetup(hw); |
589 | ||
7fba5340 BD |
590 | /* register our spi controller */ |
591 | ||
592 | err = spi_bitbang_start(&hw->bitbang); | |
593 | if (err) { | |
594 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
595 | goto err_register; | |
596 | } | |
597 | ||
7fba5340 BD |
598 | return 0; |
599 | ||
600 | err_register: | |
601 | clk_disable(hw->clk); | |
7fba5340 | 602 | |
7fba5340 | 603 | err_no_pdata: |
a419aef8 | 604 | spi_master_put(hw->master); |
7fba5340 BD |
605 | return err; |
606 | } | |
607 | ||
fd4a319b | 608 | static int s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
609 | { |
610 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
611 | ||
c6e7b8cb | 612 | spi_bitbang_stop(&hw->bitbang); |
7fba5340 | 613 | clk_disable(hw->clk); |
7fba5340 BD |
614 | spi_master_put(hw->master); |
615 | return 0; | |
616 | } | |
617 | ||
618 | ||
619 | #ifdef CONFIG_PM | |
620 | ||
6d613207 | 621 | static int s3c24xx_spi_suspend(struct device *dev) |
7fba5340 | 622 | { |
a1216394 | 623 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
38060371 AL |
624 | int ret; |
625 | ||
626 | ret = spi_master_suspend(hw->master); | |
627 | if (ret) | |
628 | return ret; | |
7fba5340 | 629 | |
cf46b973 BD |
630 | if (hw->pdata && hw->pdata->gpio_setup) |
631 | hw->pdata->gpio_setup(hw->pdata, 0); | |
632 | ||
7fba5340 BD |
633 | clk_disable(hw->clk); |
634 | return 0; | |
635 | } | |
636 | ||
6d613207 | 637 | static int s3c24xx_spi_resume(struct device *dev) |
7fba5340 | 638 | { |
a1216394 | 639 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
7fba5340 | 640 | |
5aa6cf30 | 641 | s3c24xx_spi_initialsetup(hw); |
38060371 | 642 | return spi_master_resume(hw->master); |
7fba5340 BD |
643 | } |
644 | ||
47145210 | 645 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
6d613207 BD |
646 | .suspend = s3c24xx_spi_suspend, |
647 | .resume = s3c24xx_spi_resume, | |
648 | }; | |
649 | ||
650 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops | |
7fba5340 | 651 | #else |
6d613207 BD |
652 | #define S3C24XX_SPI_PMOPS NULL |
653 | #endif /* CONFIG_PM */ | |
7fba5340 | 654 | |
7e38c3c4 | 655 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 656 | static struct platform_driver s3c24xx_spi_driver = { |
940ab889 | 657 | .probe = s3c24xx_spi_probe, |
fd4a319b | 658 | .remove = s3c24xx_spi_remove, |
7fba5340 BD |
659 | .driver = { |
660 | .name = "s3c2410-spi", | |
6d613207 | 661 | .pm = S3C24XX_SPI_PMOPS, |
7fba5340 BD |
662 | }, |
663 | }; | |
940ab889 | 664 | module_platform_driver(s3c24xx_spi_driver); |
7fba5340 BD |
665 | |
666 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
667 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
668 | MODULE_LICENSE("GPL"); |