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9135bac3 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0b2182dd SY |
2 | /* |
3 | * SH RSPI driver | |
4 | * | |
93722206 | 5 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 6 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
7 | * |
8 | * Based on spi-sh.c: | |
9 | * Copyright (C) 2011 Renesas Solutions Corp. | |
0b2182dd SY |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/errno.h> | |
0b2182dd SY |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/clk.h> | |
a3633fe7 SY |
20 | #include <linux/dmaengine.h> |
21 | #include <linux/dma-mapping.h> | |
426ef76d | 22 | #include <linux/of_device.h> |
490c9774 | 23 | #include <linux/pm_runtime.h> |
a3633fe7 | 24 | #include <linux/sh_dma.h> |
0b2182dd | 25 | #include <linux/spi/spi.h> |
a3633fe7 | 26 | #include <linux/spi/rspi.h> |
f3a14a3a | 27 | #include <linux/spinlock.h> |
0b2182dd | 28 | |
6ab4865b GU |
29 | #define RSPI_SPCR 0x00 /* Control Register */ |
30 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
31 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
32 | #define RSPI_SPSR 0x03 /* Status Register */ | |
33 | #define RSPI_SPDR 0x04 /* Data Register */ | |
34 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
35 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
36 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
37 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
38 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
39 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
40 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 41 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
42 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
43 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
44 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
45 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
46 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
47 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
48 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
49 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
50 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
51 | #define RSPI_NUM_SPCMD 8 | |
52 | #define RSPI_RZ_NUM_SPCMD 4 | |
53 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
54 | |
55 | /* RSPI on RZ only */ | |
6ab4865b GU |
56 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
57 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 58 | |
862d357f | 59 | /* QSPI only */ |
fbe5072b GU |
60 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
61 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
62 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
63 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
64 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
65 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 66 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 67 | |
6ab4865b GU |
68 | /* SPCR - Control Register */ |
69 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
70 | #define SPCR_SPE 0x40 /* Function Enable */ | |
71 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
72 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
73 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
74 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
75 | /* RSPI on SH only */ | |
76 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
77 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
6089af77 | 78 | /* QSPI on R-Car Gen2 only */ |
fbe5072b GU |
79 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ |
80 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
81 | |
82 | /* SSLP - Slave Select Polarity Register */ | |
f3a14a3a | 83 | #define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */ |
6ab4865b GU |
84 | |
85 | /* SPPCR - Pin Control Register */ | |
86 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
87 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 88 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
89 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
90 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
91 | ||
fbe5072b GU |
92 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
93 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
94 | ||
6ab4865b GU |
95 | /* SPSR - Status Register */ |
96 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
97 | #define SPSR_TEND 0x40 /* Transmit End */ | |
98 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
99 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
100 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
101 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 102 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
103 | |
104 | /* SPSCR - Sequence Control Register */ | |
105 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
106 | ||
107 | /* SPSSR - Sequence Status Register */ | |
108 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
109 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
110 | ||
111 | /* SPDCR - Data Control Register */ | |
112 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
113 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
114 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
115 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
116 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
117 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
118 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 119 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
120 | #define SPDCR_SLSEL1 0x08 |
121 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 122 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
123 | #define SPDCR_SPFC1 0x02 |
124 | #define SPDCR_SPFC0 0x01 | |
862d357f | 125 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 126 | |
6ab4865b GU |
127 | /* SPCKD - Clock Delay Register */ |
128 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 129 | |
6ab4865b GU |
130 | /* SSLND - Slave Select Negation Delay Register */ |
131 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 132 | |
6ab4865b GU |
133 | /* SPND - Next-Access Delay Register */ |
134 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 135 | |
6ab4865b GU |
136 | /* SPCR2 - Control Register 2 */ |
137 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
138 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
139 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
140 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 141 | |
6ab4865b GU |
142 | /* SPCMDn - Command Registers */ |
143 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
144 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
145 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
146 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
147 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 148 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 149 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 150 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
151 | #define SPCMD_SPB_20BIT 0x0000 |
152 | #define SPCMD_SPB_24BIT 0x0100 | |
153 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 154 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
155 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
156 | #define SPCMD_SPIMOD1 0x0040 | |
157 | #define SPCMD_SPIMOD0 0x0020 | |
158 | #define SPCMD_SPIMOD_SINGLE 0 | |
159 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
160 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
161 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
9815ed87 | 162 | #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */ |
6ab4865b | 163 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ |
8dd71698 | 164 | #define SPCMD_BRDV(brdv) ((brdv) << 2) |
6ab4865b GU |
165 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ |
166 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
167 | ||
168 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
169 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
170 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
171 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
172 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
4b6fe3ed HCM |
173 | /* QSPI on R-Car Gen2 */ |
174 | #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */ | |
175 | #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */ | |
176 | #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */ | |
177 | #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */ | |
178 | ||
179 | #define QSPI_BUFFER_SIZE 32u | |
5ce0ba88 | 180 | |
0b2182dd SY |
181 | struct rspi_data { |
182 | void __iomem *addr; | |
e0fe7005 | 183 | u32 speed_hz; |
9428a073 | 184 | struct spi_controller *ctlr; |
f3a14a3a | 185 | struct platform_device *pdev; |
0b2182dd | 186 | wait_queue_head_t wait; |
f3a14a3a | 187 | spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */ |
0b2182dd | 188 | struct clk *clk; |
348e5153 | 189 | u16 spcmd; |
06a7a3cf GU |
190 | u8 spsr; |
191 | u8 sppcr; | |
93722206 | 192 | int rx_irq, tx_irq; |
5ce0ba88 | 193 | const struct spi_ops *ops; |
a3633fe7 | 194 | |
a3633fe7 | 195 | unsigned dma_callbacked:1; |
74da7686 | 196 | unsigned byte_access:1; |
0b2182dd SY |
197 | }; |
198 | ||
baf588f4 | 199 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
200 | { |
201 | iowrite8(data, rspi->addr + offset); | |
202 | } | |
203 | ||
baf588f4 | 204 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
205 | { |
206 | iowrite16(data, rspi->addr + offset); | |
207 | } | |
208 | ||
baf588f4 | 209 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
210 | { |
211 | iowrite32(data, rspi->addr + offset); | |
212 | } | |
213 | ||
baf588f4 | 214 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
215 | { |
216 | return ioread8(rspi->addr + offset); | |
217 | } | |
218 | ||
baf588f4 | 219 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
220 | { |
221 | return ioread16(rspi->addr + offset); | |
222 | } | |
223 | ||
74da7686 GU |
224 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
225 | { | |
226 | if (rspi->byte_access) | |
227 | rspi_write8(rspi, data, RSPI_SPDR); | |
228 | else /* 16 bit */ | |
229 | rspi_write16(rspi, data, RSPI_SPDR); | |
230 | } | |
231 | ||
232 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
233 | { | |
234 | if (rspi->byte_access) | |
235 | return rspi_read8(rspi, RSPI_SPDR); | |
236 | else /* 16 bit */ | |
237 | return rspi_read16(rspi, RSPI_SPDR); | |
238 | } | |
239 | ||
5ce0ba88 HCM |
240 | /* optional functions */ |
241 | struct spi_ops { | |
74da7686 | 242 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
9428a073 GU |
243 | int (*transfer_one)(struct spi_controller *ctlr, |
244 | struct spi_device *spi, struct spi_transfer *xfer); | |
cd982e6c | 245 | u16 extra_mode_bits; |
b42e0359 | 246 | u16 flags; |
2f777ec9 | 247 | u16 fifo_size; |
144d8f97 | 248 | u8 num_hw_ss; |
5ce0ba88 HCM |
249 | }; |
250 | ||
4e71d926 GU |
251 | static void rspi_set_rate(struct rspi_data *rspi) |
252 | { | |
253 | unsigned long clksrc; | |
254 | int brdv = 0, spbr; | |
255 | ||
256 | clksrc = clk_get_rate(rspi->clk); | |
257 | spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; | |
258 | while (spbr > 255 && brdv < 3) { | |
259 | brdv++; | |
260 | spbr = DIV_ROUND_UP(spbr + 1, 2) - 1; | |
261 | } | |
262 | ||
263 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
264 | rspi->spcmd |= SPCMD_BRDV(brdv); | |
265 | } | |
266 | ||
5ce0ba88 | 267 | /* |
862d357f | 268 | * functions for RSPI on legacy SH |
5ce0ba88 | 269 | */ |
74da7686 | 270 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 271 | { |
06a7a3cf GU |
272 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
273 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 274 | |
5ce0ba88 | 275 | /* Sets transfer bit rate */ |
4e71d926 | 276 | rspi_set_rate(rspi); |
5ce0ba88 | 277 | |
74da7686 GU |
278 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
279 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
280 | rspi->byte_access = 0; | |
0b2182dd | 281 | |
5ce0ba88 HCM |
282 | /* Sets RSPCK, SSL, next-access delay value */ |
283 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
284 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
285 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
286 | ||
287 | /* Sets parity, interrupt mask */ | |
288 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
289 | ||
26843bb1 GU |
290 | /* Resets sequencer */ |
291 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
880c6d11 GU |
292 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
293 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
294 | |
295 | /* Sets RSPI mode */ | |
296 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
297 | ||
298 | return 0; | |
0b2182dd SY |
299 | } |
300 | ||
862d357f GU |
301 | /* |
302 | * functions for RSPI on RZ | |
303 | */ | |
304 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
305 | { | |
06a7a3cf GU |
306 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
307 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
308 | |
309 | /* Sets transfer bit rate */ | |
4e71d926 | 310 | rspi_set_rate(rspi); |
862d357f GU |
311 | |
312 | /* Disable dummy transmission, set byte access */ | |
313 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
314 | rspi->byte_access = 1; | |
315 | ||
316 | /* Sets RSPCK, SSL, next-access delay value */ | |
317 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
318 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
319 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
320 | ||
26843bb1 GU |
321 | /* Resets sequencer */ |
322 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
862d357f GU |
323 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
324 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
325 | ||
326 | /* Sets RSPI mode */ | |
327 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
5ce0ba88 HCM |
332 | /* |
333 | * functions for QSPI | |
334 | */ | |
74da7686 | 335 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 336 | { |
6a195f24 GU |
337 | unsigned long clksrc; |
338 | int brdv = 0, spbr; | |
5ce0ba88 | 339 | |
06a7a3cf GU |
340 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
341 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
342 | |
343 | /* Sets transfer bit rate */ | |
6a195f24 GU |
344 | clksrc = clk_get_rate(rspi->clk); |
345 | if (rspi->speed_hz >= clksrc) { | |
346 | spbr = 0; | |
347 | } else { | |
348 | spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); | |
349 | while (spbr > 255 && brdv < 3) { | |
350 | brdv++; | |
351 | spbr = DIV_ROUND_UP(spbr, 2); | |
352 | } | |
353 | spbr = clamp(spbr, 0, 255); | |
354 | } | |
355 | rspi_write8(rspi, spbr, RSPI_SPBR); | |
356 | rspi->spcmd |= SPCMD_BRDV(brdv); | |
5ce0ba88 | 357 | |
74da7686 GU |
358 | /* Disable dummy transmission, set byte access */ |
359 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
360 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
361 | |
362 | /* Sets RSPCK, SSL, next-access delay value */ | |
363 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
364 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
365 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
366 | ||
367 | /* Data Length Setting */ | |
368 | if (access_size == 8) | |
880c6d11 | 369 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 370 | else if (access_size == 16) |
880c6d11 | 371 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 372 | else |
880c6d11 | 373 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 374 | |
880c6d11 | 375 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
376 | |
377 | /* Resets transfer data length */ | |
378 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
379 | ||
380 | /* Resets transmit and receive buffer */ | |
381 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
382 | /* Sets buffer to allow normal operation */ | |
383 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
384 | ||
26843bb1 GU |
385 | /* Resets sequencer */ |
386 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
880c6d11 | 387 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 388 | |
b458a349 GU |
389 | /* Sets RSPI mode */ |
390 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
5ce0ba88 HCM |
391 | |
392 | return 0; | |
393 | } | |
394 | ||
4b6fe3ed HCM |
395 | static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) |
396 | { | |
397 | u8 data; | |
398 | ||
399 | data = rspi_read8(rspi, reg); | |
400 | data &= ~mask; | |
401 | data |= (val & mask); | |
402 | rspi_write8(rspi, data, reg); | |
403 | } | |
404 | ||
cb76b1ca GU |
405 | static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, |
406 | unsigned int len) | |
4b6fe3ed HCM |
407 | { |
408 | unsigned int n; | |
409 | ||
410 | n = min(len, QSPI_BUFFER_SIZE); | |
411 | ||
412 | if (len >= QSPI_BUFFER_SIZE) { | |
413 | /* sets triggering number to 32 bytes */ | |
414 | qspi_update(rspi, SPBFCR_TXTRG_MASK, | |
415 | SPBFCR_TXTRG_32B, QSPI_SPBFCR); | |
416 | } else { | |
417 | /* sets triggering number to 1 byte */ | |
418 | qspi_update(rspi, SPBFCR_TXTRG_MASK, | |
419 | SPBFCR_TXTRG_1B, QSPI_SPBFCR); | |
420 | } | |
421 | ||
422 | return n; | |
423 | } | |
424 | ||
3be09bec | 425 | static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len) |
4b6fe3ed HCM |
426 | { |
427 | unsigned int n; | |
428 | ||
429 | n = min(len, QSPI_BUFFER_SIZE); | |
430 | ||
431 | if (len >= QSPI_BUFFER_SIZE) { | |
432 | /* sets triggering number to 32 bytes */ | |
433 | qspi_update(rspi, SPBFCR_RXTRG_MASK, | |
434 | SPBFCR_RXTRG_32B, QSPI_SPBFCR); | |
435 | } else { | |
436 | /* sets triggering number to 1 byte */ | |
437 | qspi_update(rspi, SPBFCR_RXTRG_MASK, | |
438 | SPBFCR_RXTRG_1B, QSPI_SPBFCR); | |
439 | } | |
3be09bec | 440 | return n; |
4b6fe3ed HCM |
441 | } |
442 | ||
baf588f4 | 443 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
444 | { |
445 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
446 | } | |
447 | ||
baf588f4 | 448 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
449 | { |
450 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
451 | } | |
452 | ||
453 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
454 | u8 enable_bit) | |
455 | { | |
456 | int ret; | |
457 | ||
458 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
459 | if (rspi->spsr & wait_mask) |
460 | return 0; | |
461 | ||
0b2182dd SY |
462 | rspi_enable_irq(rspi, enable_bit); |
463 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
464 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
465 | return -ETIMEDOUT; | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
5f684c34 GU |
470 | static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) |
471 | { | |
472 | return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
473 | } | |
474 | ||
475 | static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) | |
476 | { | |
477 | return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); | |
478 | } | |
479 | ||
35301c99 GU |
480 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
481 | { | |
5f684c34 GU |
482 | int error = rspi_wait_for_tx_empty(rspi); |
483 | if (error < 0) { | |
9428a073 | 484 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); |
5f684c34 | 485 | return error; |
35301c99 GU |
486 | } |
487 | rspi_write_data(rspi, data); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | static int rspi_data_in(struct rspi_data *rspi) | |
492 | { | |
5f684c34 | 493 | int error; |
35301c99 GU |
494 | u8 data; |
495 | ||
5f684c34 GU |
496 | error = rspi_wait_for_rx_full(rspi); |
497 | if (error < 0) { | |
9428a073 | 498 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); |
5f684c34 | 499 | return error; |
35301c99 GU |
500 | } |
501 | data = rspi_read_data(rspi); | |
502 | return data; | |
503 | } | |
504 | ||
6837b8e9 GU |
505 | static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, |
506 | unsigned int n) | |
35301c99 | 507 | { |
6837b8e9 GU |
508 | while (n-- > 0) { |
509 | if (tx) { | |
510 | int ret = rspi_data_out(rspi, *tx++); | |
511 | if (ret < 0) | |
512 | return ret; | |
513 | } | |
514 | if (rx) { | |
515 | int ret = rspi_data_in(rspi); | |
516 | if (ret < 0) | |
517 | return ret; | |
518 | *rx++ = ret; | |
519 | } | |
520 | } | |
35301c99 | 521 | |
6837b8e9 | 522 | return 0; |
35301c99 GU |
523 | } |
524 | ||
a3633fe7 SY |
525 | static void rspi_dma_complete(void *arg) |
526 | { | |
527 | struct rspi_data *rspi = arg; | |
528 | ||
529 | rspi->dma_callbacked = 1; | |
530 | wake_up_interruptible(&rspi->wait); | |
531 | } | |
532 | ||
c52fb6d6 GU |
533 | static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, |
534 | struct sg_table *rx) | |
a3633fe7 | 535 | { |
c52fb6d6 GU |
536 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; |
537 | u8 irq_mask = 0; | |
538 | unsigned int other_irq = 0; | |
539 | dma_cookie_t cookie; | |
2f777ec9 | 540 | int ret; |
a3633fe7 | 541 | |
3819bc87 | 542 | /* First prepare and submit the DMA request(s), as this may fail */ |
c52fb6d6 | 543 | if (rx) { |
9428a073 GU |
544 | desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, |
545 | rx->nents, DMA_DEV_TO_MEM, | |
c52fb6d6 | 546 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
3819bc87 GU |
547 | if (!desc_rx) { |
548 | ret = -EAGAIN; | |
549 | goto no_dma_rx; | |
550 | } | |
551 | ||
552 | desc_rx->callback = rspi_dma_complete; | |
553 | desc_rx->callback_param = rspi; | |
554 | cookie = dmaengine_submit(desc_rx); | |
555 | if (dma_submit_error(cookie)) { | |
556 | ret = cookie; | |
557 | goto no_dma_rx; | |
558 | } | |
c52fb6d6 GU |
559 | |
560 | irq_mask |= SPCR_SPRIE; | |
561 | } | |
a3633fe7 | 562 | |
3819bc87 | 563 | if (tx) { |
9428a073 GU |
564 | desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, |
565 | tx->nents, DMA_MEM_TO_DEV, | |
3819bc87 GU |
566 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
567 | if (!desc_tx) { | |
568 | ret = -EAGAIN; | |
569 | goto no_dma_tx; | |
570 | } | |
571 | ||
572 | if (rx) { | |
573 | /* No callback */ | |
574 | desc_tx->callback = NULL; | |
575 | } else { | |
576 | desc_tx->callback = rspi_dma_complete; | |
577 | desc_tx->callback_param = rspi; | |
578 | } | |
579 | cookie = dmaengine_submit(desc_tx); | |
580 | if (dma_submit_error(cookie)) { | |
581 | ret = cookie; | |
582 | goto no_dma_tx; | |
583 | } | |
584 | ||
585 | irq_mask |= SPCR_SPTIE; | |
586 | } | |
587 | ||
a3633fe7 | 588 | /* |
c52fb6d6 | 589 | * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be |
a3633fe7 SY |
590 | * called. So, this driver disables the IRQ while DMA transfer. |
591 | */ | |
c52fb6d6 GU |
592 | if (tx) |
593 | disable_irq(other_irq = rspi->tx_irq); | |
594 | if (rx && rspi->rx_irq != other_irq) | |
595 | disable_irq(rspi->rx_irq); | |
a3633fe7 | 596 | |
c52fb6d6 | 597 | rspi_enable_irq(rspi, irq_mask); |
a3633fe7 SY |
598 | rspi->dma_callbacked = 0; |
599 | ||
3819bc87 GU |
600 | /* Now start DMA */ |
601 | if (rx) | |
9428a073 | 602 | dma_async_issue_pending(rspi->ctlr->dma_rx); |
3819bc87 | 603 | if (tx) |
9428a073 | 604 | dma_async_issue_pending(rspi->ctlr->dma_tx); |
a3633fe7 SY |
605 | |
606 | ret = wait_event_interruptible_timeout(rspi->wait, | |
607 | rspi->dma_callbacked, HZ); | |
8dbbaa47 | 608 | if (ret > 0 && rspi->dma_callbacked) { |
a3633fe7 | 609 | ret = 0; |
8dbbaa47 GU |
610 | } else { |
611 | if (!ret) { | |
9428a073 | 612 | dev_err(&rspi->ctlr->dev, "DMA timeout\n"); |
8dbbaa47 GU |
613 | ret = -ETIMEDOUT; |
614 | } | |
3819bc87 | 615 | if (tx) |
9428a073 | 616 | dmaengine_terminate_all(rspi->ctlr->dma_tx); |
3819bc87 | 617 | if (rx) |
9428a073 | 618 | dmaengine_terminate_all(rspi->ctlr->dma_rx); |
3819bc87 | 619 | } |
a3633fe7 | 620 | |
c52fb6d6 GU |
621 | rspi_disable_irq(rspi, irq_mask); |
622 | ||
623 | if (tx) | |
624 | enable_irq(rspi->tx_irq); | |
625 | if (rx && rspi->rx_irq != other_irq) | |
626 | enable_irq(rspi->rx_irq); | |
627 | ||
a3633fe7 | 628 | return ret; |
85912a88 | 629 | |
3819bc87 GU |
630 | no_dma_tx: |
631 | if (rx) | |
9428a073 | 632 | dmaengine_terminate_all(rspi->ctlr->dma_rx); |
3819bc87 GU |
633 | no_dma_rx: |
634 | if (ret == -EAGAIN) { | |
1bec84dd GU |
635 | dev_warn_once(&rspi->ctlr->dev, |
636 | "DMA not available, falling back to PIO\n"); | |
3819bc87 GU |
637 | } |
638 | return ret; | |
a3633fe7 SY |
639 | } |
640 | ||
baf588f4 | 641 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 642 | { |
97b95c11 | 643 | u8 spsr; |
0b2182dd SY |
644 | |
645 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
646 | if (spsr & SPSR_SPRF) | |
74da7686 | 647 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
648 | if (spsr & SPSR_OVRF) |
649 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 650 | RSPI_SPSR); |
a3633fe7 SY |
651 | } |
652 | ||
862d357f GU |
653 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
654 | { | |
655 | rspi_receive_init(rspi); | |
656 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
657 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
658 | } | |
659 | ||
baf588f4 | 660 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 661 | { |
97b95c11 | 662 | u8 spsr; |
cb52c673 HCM |
663 | |
664 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
665 | if (spsr & SPSR_SPRF) | |
74da7686 | 666 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 667 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 668 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
669 | } |
670 | ||
2f777ec9 GU |
671 | static bool __rspi_can_dma(const struct rspi_data *rspi, |
672 | const struct spi_transfer *xfer) | |
a3633fe7 | 673 | { |
2f777ec9 GU |
674 | return xfer->len > rspi->ops->fifo_size; |
675 | } | |
a3633fe7 | 676 | |
9428a073 | 677 | static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, |
2f777ec9 GU |
678 | struct spi_transfer *xfer) |
679 | { | |
9428a073 | 680 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
2f777ec9 GU |
681 | |
682 | return __rspi_can_dma(rspi, xfer); | |
a3633fe7 SY |
683 | } |
684 | ||
4b6fe3ed HCM |
685 | static int rspi_dma_check_then_transfer(struct rspi_data *rspi, |
686 | struct spi_transfer *xfer) | |
8b983e90 | 687 | { |
9428a073 | 688 | if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) |
6310372d | 689 | return -EAGAIN; |
8b983e90 | 690 | |
6310372d HCM |
691 | /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ |
692 | return rspi_dma_transfer(rspi, &xfer->tx_sg, | |
693 | xfer->rx_buf ? &xfer->rx_sg : NULL); | |
4b6fe3ed HCM |
694 | } |
695 | ||
696 | static int rspi_common_transfer(struct rspi_data *rspi, | |
697 | struct spi_transfer *xfer) | |
698 | { | |
699 | int ret; | |
700 | ||
701 | ret = rspi_dma_check_then_transfer(rspi, xfer); | |
702 | if (ret != -EAGAIN) | |
703 | return ret; | |
704 | ||
8b983e90 GU |
705 | ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); |
706 | if (ret < 0) | |
707 | return ret; | |
708 | ||
709 | /* Wait for the last transmission */ | |
710 | rspi_wait_for_tx_empty(rspi); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
9428a073 GU |
715 | static int rspi_transfer_one(struct spi_controller *ctlr, |
716 | struct spi_device *spi, struct spi_transfer *xfer) | |
8449fd76 | 717 | { |
9428a073 | 718 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
b42e0359 | 719 | u8 spcr; |
8449fd76 | 720 | |
8449fd76 | 721 | spcr = rspi_read8(rspi, RSPI_SPCR); |
6837b8e9 | 722 | if (xfer->rx_buf) { |
32c64261 | 723 | rspi_receive_init(rspi); |
8449fd76 | 724 | spcr &= ~SPCR_TXMD; |
32c64261 | 725 | } else { |
8449fd76 | 726 | spcr |= SPCR_TXMD; |
32c64261 | 727 | } |
8449fd76 GU |
728 | rspi_write8(rspi, spcr, RSPI_SPCR); |
729 | ||
8b983e90 | 730 | return rspi_common_transfer(rspi, xfer); |
8449fd76 GU |
731 | } |
732 | ||
9428a073 | 733 | static int rspi_rz_transfer_one(struct spi_controller *ctlr, |
03e627c5 GU |
734 | struct spi_device *spi, |
735 | struct spi_transfer *xfer) | |
862d357f | 736 | { |
9428a073 | 737 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
862d357f GU |
738 | |
739 | rspi_rz_receive_init(rspi); | |
740 | ||
8b983e90 | 741 | return rspi_common_transfer(rspi, xfer); |
862d357f GU |
742 | } |
743 | ||
a91bbe7d | 744 | static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, |
4b6fe3ed HCM |
745 | u8 *rx, unsigned int len) |
746 | { | |
cb76b1ca GU |
747 | unsigned int i, n; |
748 | int ret; | |
4b6fe3ed HCM |
749 | |
750 | while (len > 0) { | |
751 | n = qspi_set_send_trigger(rspi, len); | |
752 | qspi_set_receive_trigger(rspi, len); | |
7e95b166 HNA |
753 | ret = rspi_wait_for_tx_empty(rspi); |
754 | if (ret < 0) { | |
755 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); | |
756 | return ret; | |
757 | } | |
758 | for (i = 0; i < n; i++) | |
759 | rspi_write_data(rspi, *tx++); | |
4b6fe3ed | 760 | |
7e95b166 HNA |
761 | ret = rspi_wait_for_rx_full(rspi); |
762 | if (ret < 0) { | |
763 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); | |
764 | return ret; | |
4b6fe3ed | 765 | } |
7e95b166 HNA |
766 | for (i = 0; i < n; i++) |
767 | *rx++ = rspi_read_data(rspi); | |
768 | ||
4b6fe3ed HCM |
769 | len -= n; |
770 | } | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
340a15e6 GU |
775 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
776 | struct spi_transfer *xfer) | |
eb557f75 | 777 | { |
4b6fe3ed HCM |
778 | int ret; |
779 | ||
340a15e6 GU |
780 | qspi_receive_init(rspi); |
781 | ||
4b6fe3ed HCM |
782 | ret = rspi_dma_check_then_transfer(rspi, xfer); |
783 | if (ret != -EAGAIN) | |
784 | return ret; | |
785 | ||
cc2e9328 | 786 | return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, |
4b6fe3ed | 787 | xfer->rx_buf, xfer->len); |
340a15e6 GU |
788 | } |
789 | ||
880c6d11 GU |
790 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
791 | { | |
db300838 AB |
792 | const u8 *tx = xfer->tx_buf; |
793 | unsigned int n = xfer->len; | |
794 | unsigned int i, len; | |
880c6d11 GU |
795 | int ret; |
796 | ||
9428a073 | 797 | if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { |
85912a88 GU |
798 | ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); |
799 | if (ret != -EAGAIN) | |
800 | return ret; | |
801 | } | |
4f12b5e5 | 802 | |
db300838 AB |
803 | while (n > 0) { |
804 | len = qspi_set_send_trigger(rspi, n); | |
7e95b166 HNA |
805 | ret = rspi_wait_for_tx_empty(rspi); |
806 | if (ret < 0) { | |
807 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); | |
808 | return ret; | |
db300838 | 809 | } |
7e95b166 HNA |
810 | for (i = 0; i < len; i++) |
811 | rspi_write_data(rspi, *tx++); | |
812 | ||
db300838 AB |
813 | n -= len; |
814 | } | |
880c6d11 GU |
815 | |
816 | /* Wait for the last transmission */ | |
5f684c34 | 817 | rspi_wait_for_tx_empty(rspi); |
880c6d11 GU |
818 | |
819 | return 0; | |
820 | } | |
821 | ||
822 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
823 | { | |
db300838 AB |
824 | u8 *rx = xfer->rx_buf; |
825 | unsigned int n = xfer->len; | |
826 | unsigned int i, len; | |
827 | int ret; | |
828 | ||
9428a073 | 829 | if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { |
85912a88 GU |
830 | int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); |
831 | if (ret != -EAGAIN) | |
832 | return ret; | |
833 | } | |
4f12b5e5 | 834 | |
db300838 AB |
835 | while (n > 0) { |
836 | len = qspi_set_receive_trigger(rspi, n); | |
7e95b166 HNA |
837 | ret = rspi_wait_for_rx_full(rspi); |
838 | if (ret < 0) { | |
839 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); | |
840 | return ret; | |
db300838 | 841 | } |
7e95b166 HNA |
842 | for (i = 0; i < len; i++) |
843 | *rx++ = rspi_read_data(rspi); | |
844 | ||
db300838 AB |
845 | n -= len; |
846 | } | |
847 | ||
848 | return 0; | |
880c6d11 GU |
849 | } |
850 | ||
9428a073 GU |
851 | static int qspi_transfer_one(struct spi_controller *ctlr, |
852 | struct spi_device *spi, struct spi_transfer *xfer) | |
340a15e6 | 853 | { |
9428a073 | 854 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
340a15e6 | 855 | |
ba824d49 GU |
856 | if (spi->mode & SPI_LOOP) { |
857 | return qspi_transfer_out_in(rspi, xfer); | |
b42e0359 | 858 | } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
859 | /* Quad or Dual SPI Write */ |
860 | return qspi_transfer_out(rspi, xfer); | |
b42e0359 | 861 | } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
862 | /* Quad or Dual SPI Read */ |
863 | return qspi_transfer_in(rspi, xfer); | |
864 | } else { | |
865 | /* Single SPI Transfer */ | |
866 | return qspi_transfer_out_in(rspi, xfer); | |
867 | } | |
0b2182dd SY |
868 | } |
869 | ||
880c6d11 GU |
870 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
871 | { | |
872 | if (xfer->tx_buf) | |
873 | switch (xfer->tx_nbits) { | |
874 | case SPI_NBITS_QUAD: | |
875 | return SPCMD_SPIMOD_QUAD; | |
876 | case SPI_NBITS_DUAL: | |
877 | return SPCMD_SPIMOD_DUAL; | |
878 | default: | |
879 | return 0; | |
880 | } | |
881 | if (xfer->rx_buf) | |
882 | switch (xfer->rx_nbits) { | |
883 | case SPI_NBITS_QUAD: | |
884 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
885 | case SPI_NBITS_DUAL: | |
886 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
887 | default: | |
888 | return 0; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
895 | const struct spi_message *msg) | |
896 | { | |
897 | const struct spi_transfer *xfer; | |
898 | unsigned int i = 0, len = 0; | |
899 | u16 current_mode = 0xffff, mode; | |
900 | ||
901 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
902 | mode = qspi_transfer_mode(xfer); | |
903 | if (mode == current_mode) { | |
904 | len += xfer->len; | |
905 | continue; | |
906 | } | |
907 | ||
908 | /* Transfer mode change */ | |
909 | if (i) { | |
910 | /* Set transfer data length of previous transfer */ | |
911 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
912 | } | |
913 | ||
914 | if (i >= QSPI_NUM_SPCMD) { | |
915 | dev_err(&msg->spi->dev, | |
916 | "Too many different transfer modes"); | |
917 | return -EINVAL; | |
918 | } | |
919 | ||
920 | /* Program transfer mode for this transfer */ | |
921 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
922 | current_mode = mode; | |
923 | len = xfer->len; | |
924 | i++; | |
925 | } | |
926 | if (i) { | |
927 | /* Set final transfer data length and sequence length */ | |
928 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
929 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
930 | } | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
f3a14a3a GU |
935 | static int rspi_setup(struct spi_device *spi) |
936 | { | |
937 | struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); | |
938 | u8 sslp; | |
939 | ||
940 | if (spi->cs_gpiod) | |
941 | return 0; | |
942 | ||
943 | pm_runtime_get_sync(&rspi->pdev->dev); | |
944 | spin_lock_irq(&rspi->lock); | |
945 | ||
946 | sslp = rspi_read8(rspi, RSPI_SSLP); | |
947 | if (spi->mode & SPI_CS_HIGH) | |
948 | sslp |= SSLP_SSLP(spi->chip_select); | |
949 | else | |
950 | sslp &= ~SSLP_SSLP(spi->chip_select); | |
951 | rspi_write8(rspi, sslp, RSPI_SSLP); | |
952 | ||
953 | spin_unlock_irq(&rspi->lock); | |
954 | pm_runtime_put(&rspi->pdev->dev); | |
955 | return 0; | |
956 | } | |
957 | ||
9428a073 | 958 | static int rspi_prepare_message(struct spi_controller *ctlr, |
880c6d11 | 959 | struct spi_message *msg) |
79d23495 | 960 | { |
9428a073 | 961 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
42bdaaec | 962 | struct spi_device *spi = msg->spi; |
e0fe7005 | 963 | const struct spi_transfer *xfer; |
880c6d11 | 964 | int ret; |
0b2182dd | 965 | |
e0fe7005 GU |
966 | /* |
967 | * As the Bit Rate Register must not be changed while the device is | |
968 | * active, all transfers in a message must use the same bit rate. | |
969 | * In theory, the sequencer could be enabled, and each Command Register | |
970 | * could divide the base bit rate by a different value. | |
971 | * However, most RSPI variants do not have Transfer Data Length | |
972 | * Multiplier Setting Registers, so each sequence step would be limited | |
973 | * to a single word, making this feature unsuitable for large | |
974 | * transfers, which would gain most from it. | |
975 | */ | |
976 | rspi->speed_hz = spi->max_speed_hz; | |
977 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
978 | if (xfer->speed_hz < rspi->speed_hz) | |
979 | rspi->speed_hz = xfer->speed_hz; | |
980 | } | |
42bdaaec GU |
981 | |
982 | rspi->spcmd = SPCMD_SSLKP; | |
983 | if (spi->mode & SPI_CPOL) | |
984 | rspi->spcmd |= SPCMD_CPOL; | |
985 | if (spi->mode & SPI_CPHA) | |
986 | rspi->spcmd |= SPCMD_CPHA; | |
c046f8fd GU |
987 | if (spi->mode & SPI_LSB_FIRST) |
988 | rspi->spcmd |= SPCMD_LSBF; | |
42bdaaec | 989 | |
9815ed87 | 990 | /* Configure slave signal to assert */ |
144d8f97 GU |
991 | rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs |
992 | : spi->chip_select); | |
9815ed87 | 993 | |
42bdaaec GU |
994 | /* CMOS output mode and MOSI signal from previous transfer */ |
995 | rspi->sppcr = 0; | |
996 | if (spi->mode & SPI_LOOP) | |
997 | rspi->sppcr |= SPPCR_SPLP; | |
998 | ||
8f2344fa | 999 | rspi->ops->set_config_register(rspi, 8); |
42bdaaec | 1000 | |
880c6d11 GU |
1001 | if (msg->spi->mode & |
1002 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
1003 | /* Setup sequencer for messages with multiple transfer modes */ | |
1004 | ret = qspi_setup_sequencer(rspi, msg); | |
1005 | if (ret < 0) | |
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | /* Enable SPI function in master mode */ | |
79d23495 | 1010 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
1011 | return 0; |
1012 | } | |
1013 | ||
9428a073 | 1014 | static int rspi_unprepare_message(struct spi_controller *ctlr, |
880c6d11 | 1015 | struct spi_message *msg) |
0b2182dd | 1016 | { |
9428a073 | 1017 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
79d23495 | 1018 | |
880c6d11 | 1019 | /* Disable SPI function */ |
79d23495 | 1020 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
1021 | |
1022 | /* Reset sequencer for Single SPI Transfers */ | |
1023 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
1024 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 1025 | return 0; |
0b2182dd SY |
1026 | } |
1027 | ||
93722206 | 1028 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 1029 | { |
c132f094 | 1030 | struct rspi_data *rspi = _sr; |
97b95c11 | 1031 | u8 spsr; |
0b2182dd | 1032 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 1033 | u8 disable_irq = 0; |
0b2182dd SY |
1034 | |
1035 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1036 | if (spsr & SPSR_SPRF) | |
1037 | disable_irq |= SPCR_SPRIE; | |
1038 | if (spsr & SPSR_SPTEF) | |
1039 | disable_irq |= SPCR_SPTIE; | |
1040 | ||
1041 | if (disable_irq) { | |
1042 | ret = IRQ_HANDLED; | |
1043 | rspi_disable_irq(rspi, disable_irq); | |
1044 | wake_up(&rspi->wait); | |
1045 | } | |
1046 | ||
1047 | return ret; | |
1048 | } | |
1049 | ||
93722206 GU |
1050 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
1051 | { | |
1052 | struct rspi_data *rspi = _sr; | |
1053 | u8 spsr; | |
1054 | ||
1055 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1056 | if (spsr & SPSR_SPRF) { | |
1057 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
1058 | wake_up(&rspi->wait); | |
1059 | return IRQ_HANDLED; | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
1066 | { | |
1067 | struct rspi_data *rspi = _sr; | |
1068 | u8 spsr; | |
1069 | ||
1070 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1071 | if (spsr & SPSR_SPTEF) { | |
1072 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
1073 | wake_up(&rspi->wait); | |
1074 | return IRQ_HANDLED; | |
1075 | } | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
65bf2205 GU |
1080 | static struct dma_chan *rspi_request_dma_chan(struct device *dev, |
1081 | enum dma_transfer_direction dir, | |
1082 | unsigned int id, | |
1083 | dma_addr_t port_addr) | |
a3633fe7 | 1084 | { |
a3633fe7 | 1085 | dma_cap_mask_t mask; |
65bf2205 | 1086 | struct dma_chan *chan; |
0243c536 SY |
1087 | struct dma_slave_config cfg; |
1088 | int ret; | |
a3633fe7 | 1089 | |
65bf2205 GU |
1090 | dma_cap_zero(mask); |
1091 | dma_cap_set(DMA_SLAVE, mask); | |
1092 | ||
e825b8dd GU |
1093 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
1094 | (void *)(unsigned long)id, dev, | |
1095 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
65bf2205 | 1096 | if (!chan) { |
e825b8dd | 1097 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
65bf2205 GU |
1098 | return NULL; |
1099 | } | |
1100 | ||
1101 | memset(&cfg, 0, sizeof(cfg)); | |
65bf2205 | 1102 | cfg.direction = dir; |
a30b95a7 | 1103 | if (dir == DMA_MEM_TO_DEV) { |
65bf2205 | 1104 | cfg.dst_addr = port_addr; |
a30b95a7 GU |
1105 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1106 | } else { | |
65bf2205 | 1107 | cfg.src_addr = port_addr; |
a30b95a7 GU |
1108 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1109 | } | |
65bf2205 GU |
1110 | |
1111 | ret = dmaengine_slave_config(chan, &cfg); | |
1112 | if (ret) { | |
1113 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
1114 | dma_release_channel(chan); | |
1115 | return NULL; | |
1116 | } | |
1117 | ||
1118 | return chan; | |
1119 | } | |
1120 | ||
9428a073 | 1121 | static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr, |
fcdc49ae | 1122 | const struct resource *res) |
65bf2205 | 1123 | { |
fcdc49ae | 1124 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); |
e825b8dd GU |
1125 | unsigned int dma_tx_id, dma_rx_id; |
1126 | ||
1127 | if (dev->of_node) { | |
1128 | /* In the OF case we will get the slave IDs from the DT */ | |
1129 | dma_tx_id = 0; | |
1130 | dma_rx_id = 0; | |
1131 | } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { | |
1132 | dma_tx_id = rspi_pd->dma_tx_id; | |
1133 | dma_rx_id = rspi_pd->dma_rx_id; | |
1134 | } else { | |
1135 | /* The driver assumes no error. */ | |
1136 | return 0; | |
1137 | } | |
65bf2205 | 1138 | |
9428a073 GU |
1139 | ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, |
1140 | res->start + RSPI_SPDR); | |
1141 | if (!ctlr->dma_tx) | |
5f338d0c GU |
1142 | return -ENODEV; |
1143 | ||
9428a073 GU |
1144 | ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, |
1145 | res->start + RSPI_SPDR); | |
1146 | if (!ctlr->dma_rx) { | |
1147 | dma_release_channel(ctlr->dma_tx); | |
1148 | ctlr->dma_tx = NULL; | |
5f338d0c | 1149 | return -ENODEV; |
a3633fe7 | 1150 | } |
0243c536 | 1151 | |
9428a073 | 1152 | ctlr->can_dma = rspi_can_dma; |
5f338d0c | 1153 | dev_info(dev, "DMA available"); |
0243c536 | 1154 | return 0; |
a3633fe7 SY |
1155 | } |
1156 | ||
9428a073 | 1157 | static void rspi_release_dma(struct spi_controller *ctlr) |
a3633fe7 | 1158 | { |
9428a073 GU |
1159 | if (ctlr->dma_tx) |
1160 | dma_release_channel(ctlr->dma_tx); | |
1161 | if (ctlr->dma_rx) | |
1162 | dma_release_channel(ctlr->dma_rx); | |
a3633fe7 SY |
1163 | } |
1164 | ||
fd4a319b | 1165 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 1166 | { |
5ffbe2d9 | 1167 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 1168 | |
9428a073 | 1169 | rspi_release_dma(rspi->ctlr); |
490c9774 | 1170 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1171 | |
1172 | return 0; | |
1173 | } | |
1174 | ||
426ef76d | 1175 | static const struct spi_ops rspi_ops = { |
b42e0359 GU |
1176 | .set_config_register = rspi_set_config_register, |
1177 | .transfer_one = rspi_transfer_one, | |
9428a073 | 1178 | .flags = SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1179 | .fifo_size = 8, |
144d8f97 | 1180 | .num_hw_ss = 2, |
426ef76d GU |
1181 | }; |
1182 | ||
1183 | static const struct spi_ops rspi_rz_ops = { | |
b42e0359 GU |
1184 | .set_config_register = rspi_rz_set_config_register, |
1185 | .transfer_one = rspi_rz_transfer_one, | |
9428a073 | 1186 | .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1187 | .fifo_size = 8, /* 8 for TX, 32 for RX */ |
144d8f97 | 1188 | .num_hw_ss = 1, |
426ef76d GU |
1189 | }; |
1190 | ||
1191 | static const struct spi_ops qspi_ops = { | |
b42e0359 GU |
1192 | .set_config_register = qspi_set_config_register, |
1193 | .transfer_one = qspi_transfer_one, | |
cd982e6c | 1194 | .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | |
b42e0359 | 1195 | SPI_RX_DUAL | SPI_RX_QUAD, |
9428a073 | 1196 | .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1197 | .fifo_size = 32, |
144d8f97 | 1198 | .num_hw_ss = 1, |
426ef76d GU |
1199 | }; |
1200 | ||
1201 | #ifdef CONFIG_OF | |
1202 | static const struct of_device_id rspi_of_match[] = { | |
1203 | /* RSPI on legacy SH */ | |
1204 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1205 | /* RSPI on RZ/A1H */ | |
1206 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1207 | /* QSPI on R-Car Gen2 */ | |
1208 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1209 | { /* sentinel */ } | |
1210 | }; | |
1211 | ||
1212 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1213 | ||
9428a073 | 1214 | static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) |
426ef76d GU |
1215 | { |
1216 | u32 num_cs; | |
1217 | int error; | |
1218 | ||
1219 | /* Parse DT properties */ | |
1220 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1221 | if (error) { | |
1222 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1223 | return error; | |
1224 | } | |
1225 | ||
9428a073 | 1226 | ctlr->num_chipselect = num_cs; |
426ef76d GU |
1227 | return 0; |
1228 | } | |
1229 | #else | |
64b67def | 1230 | #define rspi_of_match NULL |
9428a073 | 1231 | static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) |
426ef76d GU |
1232 | { |
1233 | return -EINVAL; | |
1234 | } | |
1235 | #endif /* CONFIG_OF */ | |
1236 | ||
93722206 GU |
1237 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1238 | irq_handler_t handler, const char *suffix, | |
1239 | void *dev_id) | |
1240 | { | |
43937455 GU |
1241 | const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", |
1242 | dev_name(dev), suffix); | |
93722206 GU |
1243 | if (!name) |
1244 | return -ENOMEM; | |
43937455 | 1245 | |
93722206 GU |
1246 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); |
1247 | } | |
1248 | ||
fd4a319b | 1249 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1250 | { |
1251 | struct resource *res; | |
9428a073 | 1252 | struct spi_controller *ctlr; |
0b2182dd | 1253 | struct rspi_data *rspi; |
93722206 | 1254 | int ret; |
426ef76d | 1255 | const struct rspi_plat_data *rspi_pd; |
5ce0ba88 | 1256 | const struct spi_ops *ops; |
0b2182dd | 1257 | |
9428a073 GU |
1258 | ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1259 | if (ctlr == NULL) | |
0b2182dd | 1260 | return -ENOMEM; |
0b2182dd | 1261 | |
219a7bc5 GU |
1262 | ops = of_device_get_match_data(&pdev->dev); |
1263 | if (ops) { | |
9428a073 | 1264 | ret = rspi_parse_dt(&pdev->dev, ctlr); |
426ef76d GU |
1265 | if (ret) |
1266 | goto error1; | |
1267 | } else { | |
1268 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1269 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1270 | if (rspi_pd && rspi_pd->num_chipselect) | |
9428a073 | 1271 | ctlr->num_chipselect = rspi_pd->num_chipselect; |
426ef76d | 1272 | else |
9428a073 | 1273 | ctlr->num_chipselect = 2; /* default */ |
d64b4726 | 1274 | } |
426ef76d | 1275 | |
9428a073 | 1276 | rspi = spi_controller_get_devdata(ctlr); |
24b5a82c | 1277 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1278 | rspi->ops = ops; |
9428a073 | 1279 | rspi->ctlr = ctlr; |
5d79e9ac LP |
1280 | |
1281 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1282 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1283 | if (IS_ERR(rspi->addr)) { | |
1284 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1285 | goto error1; |
1286 | } | |
1287 | ||
29f397b7 | 1288 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1289 | if (IS_ERR(rspi->clk)) { |
1290 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1291 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1292 | goto error1; |
0b2182dd | 1293 | } |
17fe0d9a | 1294 | |
f3a14a3a | 1295 | rspi->pdev = pdev; |
490c9774 | 1296 | pm_runtime_enable(&pdev->dev); |
0b2182dd | 1297 | |
0b2182dd | 1298 | init_waitqueue_head(&rspi->wait); |
f3a14a3a | 1299 | spin_lock_init(&rspi->lock); |
0b2182dd | 1300 | |
9428a073 | 1301 | ctlr->bus_num = pdev->id; |
f3a14a3a | 1302 | ctlr->setup = rspi_setup; |
9428a073 GU |
1303 | ctlr->auto_runtime_pm = true; |
1304 | ctlr->transfer_one = ops->transfer_one; | |
1305 | ctlr->prepare_message = rspi_prepare_message; | |
1306 | ctlr->unprepare_message = rspi_unprepare_message; | |
f3a14a3a GU |
1307 | ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | |
1308 | SPI_LOOP | ops->extra_mode_bits; | |
9428a073 GU |
1309 | ctlr->flags = ops->flags; |
1310 | ctlr->dev.of_node = pdev->dev.of_node; | |
144d8f97 GU |
1311 | ctlr->use_gpio_descriptors = true; |
1312 | ctlr->max_native_cs = rspi->ops->num_hw_ss; | |
0b2182dd | 1313 | |
2de860b4 | 1314 | ret = platform_get_irq_byname_optional(pdev, "rx"); |
93722206 | 1315 | if (ret < 0) { |
2de860b4 | 1316 | ret = platform_get_irq_byname_optional(pdev, "mux"); |
93722206 GU |
1317 | if (ret < 0) |
1318 | ret = platform_get_irq(pdev, 0); | |
1319 | if (ret >= 0) | |
1320 | rspi->rx_irq = rspi->tx_irq = ret; | |
1321 | } else { | |
1322 | rspi->rx_irq = ret; | |
1323 | ret = platform_get_irq_byname(pdev, "tx"); | |
1324 | if (ret >= 0) | |
1325 | rspi->tx_irq = ret; | |
1326 | } | |
93722206 GU |
1327 | |
1328 | if (rspi->rx_irq == rspi->tx_irq) { | |
1329 | /* Single multiplexed interrupt */ | |
1330 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1331 | "mux", rspi); | |
1332 | } else { | |
1333 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1334 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1335 | "rx", rspi); | |
1336 | if (!ret) | |
1337 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1338 | rspi_irq_tx, "tx", rspi); | |
1339 | } | |
0b2182dd SY |
1340 | if (ret < 0) { |
1341 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1342 | goto error2; |
0b2182dd SY |
1343 | } |
1344 | ||
9428a073 | 1345 | ret = rspi_request_dma(&pdev->dev, ctlr, res); |
27e105a6 GU |
1346 | if (ret < 0) |
1347 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
a3633fe7 | 1348 | |
9428a073 | 1349 | ret = devm_spi_register_controller(&pdev->dev, ctlr); |
0b2182dd | 1350 | if (ret < 0) { |
9428a073 | 1351 | dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); |
fcb4ed74 | 1352 | goto error3; |
0b2182dd SY |
1353 | } |
1354 | ||
1355 | dev_info(&pdev->dev, "probed\n"); | |
1356 | ||
1357 | return 0; | |
1358 | ||
fcb4ed74 | 1359 | error3: |
9428a073 | 1360 | rspi_release_dma(ctlr); |
fcb4ed74 | 1361 | error2: |
490c9774 | 1362 | pm_runtime_disable(&pdev->dev); |
0b2182dd | 1363 | error1: |
9428a073 | 1364 | spi_controller_put(ctlr); |
0b2182dd SY |
1365 | |
1366 | return ret; | |
1367 | } | |
1368 | ||
8634dafa | 1369 | static const struct platform_device_id spi_driver_ids[] = { |
5ce0ba88 | 1370 | { "rspi", (kernel_ulong_t)&rspi_ops }, |
5ce0ba88 HCM |
1371 | {}, |
1372 | }; | |
1373 | ||
1374 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1375 | ||
c1ca59c2 GU |
1376 | #ifdef CONFIG_PM_SLEEP |
1377 | static int rspi_suspend(struct device *dev) | |
1378 | { | |
be0bf62e | 1379 | struct rspi_data *rspi = dev_get_drvdata(dev); |
c1ca59c2 | 1380 | |
9428a073 | 1381 | return spi_controller_suspend(rspi->ctlr); |
c1ca59c2 GU |
1382 | } |
1383 | ||
1384 | static int rspi_resume(struct device *dev) | |
1385 | { | |
be0bf62e | 1386 | struct rspi_data *rspi = dev_get_drvdata(dev); |
c1ca59c2 | 1387 | |
9428a073 | 1388 | return spi_controller_resume(rspi->ctlr); |
c1ca59c2 GU |
1389 | } |
1390 | ||
1391 | static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume); | |
1392 | #define DEV_PM_OPS &rspi_pm_ops | |
1393 | #else | |
1394 | #define DEV_PM_OPS NULL | |
1395 | #endif /* CONFIG_PM_SLEEP */ | |
1396 | ||
0b2182dd SY |
1397 | static struct platform_driver rspi_driver = { |
1398 | .probe = rspi_probe, | |
fd4a319b | 1399 | .remove = rspi_remove, |
5ce0ba88 | 1400 | .id_table = spi_driver_ids, |
0b2182dd | 1401 | .driver = { |
5ce0ba88 | 1402 | .name = "renesas_spi", |
c1ca59c2 | 1403 | .pm = DEV_PM_OPS, |
426ef76d | 1404 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1405 | }, |
1406 | }; | |
1407 | module_platform_driver(rspi_driver); | |
1408 | ||
1409 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1410 | MODULE_LICENSE("GPL v2"); | |
1411 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1412 | MODULE_ALIAS("platform:rspi"); |