Commit | Line | Data |
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9135bac3 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0b2182dd SY |
2 | /* |
3 | * SH RSPI driver | |
4 | * | |
93722206 | 5 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 6 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
7 | * |
8 | * Based on spi-sh.c: | |
9 | * Copyright (C) 2011 Renesas Solutions Corp. | |
0b2182dd SY |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/errno.h> | |
0b2182dd SY |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/clk.h> | |
a3633fe7 SY |
20 | #include <linux/dmaengine.h> |
21 | #include <linux/dma-mapping.h> | |
749396cb | 22 | #include <linux/of.h> |
490c9774 | 23 | #include <linux/pm_runtime.h> |
aadbff4a | 24 | #include <linux/reset.h> |
a3633fe7 | 25 | #include <linux/sh_dma.h> |
0b2182dd | 26 | #include <linux/spi/spi.h> |
a3633fe7 | 27 | #include <linux/spi/rspi.h> |
f3a14a3a | 28 | #include <linux/spinlock.h> |
0b2182dd | 29 | |
6ab4865b GU |
30 | #define RSPI_SPCR 0x00 /* Control Register */ |
31 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
32 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
33 | #define RSPI_SPSR 0x03 /* Status Register */ | |
34 | #define RSPI_SPDR 0x04 /* Data Register */ | |
35 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
36 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
37 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
38 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
39 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
40 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
41 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 42 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
43 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
44 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
45 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
46 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
47 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
48 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
49 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
50 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
51 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
52 | #define RSPI_NUM_SPCMD 8 | |
53 | #define RSPI_RZ_NUM_SPCMD 4 | |
54 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
55 | |
56 | /* RSPI on RZ only */ | |
6ab4865b GU |
57 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
58 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 59 | |
862d357f | 60 | /* QSPI only */ |
fbe5072b GU |
61 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
62 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
63 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
64 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
65 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
66 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 67 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 68 | |
6ab4865b GU |
69 | /* SPCR - Control Register */ |
70 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
71 | #define SPCR_SPE 0x40 /* Function Enable */ | |
72 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
73 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
74 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
75 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
76 | /* RSPI on SH only */ | |
77 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
78 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
6089af77 | 79 | /* QSPI on R-Car Gen2 only */ |
fbe5072b GU |
80 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ |
81 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
82 | |
83 | /* SSLP - Slave Select Polarity Register */ | |
f3a14a3a | 84 | #define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */ |
6ab4865b GU |
85 | |
86 | /* SPPCR - Pin Control Register */ | |
87 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
88 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 89 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
90 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
91 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
92 | ||
fbe5072b GU |
93 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
94 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
95 | ||
6ab4865b GU |
96 | /* SPSR - Status Register */ |
97 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
98 | #define SPSR_TEND 0x40 /* Transmit End */ | |
99 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
100 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
101 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
102 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 103 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
104 | |
105 | /* SPSCR - Sequence Control Register */ | |
106 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
107 | ||
108 | /* SPSSR - Sequence Status Register */ | |
109 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
110 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
111 | ||
112 | /* SPDCR - Data Control Register */ | |
113 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
114 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
115 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
116 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
117 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
118 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
119 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 120 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
121 | #define SPDCR_SLSEL1 0x08 |
122 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 123 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
124 | #define SPDCR_SPFC1 0x02 |
125 | #define SPDCR_SPFC0 0x01 | |
862d357f | 126 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 127 | |
6ab4865b GU |
128 | /* SPCKD - Clock Delay Register */ |
129 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 130 | |
6ab4865b GU |
131 | /* SSLND - Slave Select Negation Delay Register */ |
132 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 133 | |
6ab4865b GU |
134 | /* SPND - Next-Access Delay Register */ |
135 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 136 | |
6ab4865b GU |
137 | /* SPCR2 - Control Register 2 */ |
138 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
139 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
140 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
141 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 142 | |
6ab4865b GU |
143 | /* SPCMDn - Command Registers */ |
144 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
145 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
146 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
147 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
148 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 149 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 150 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 151 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
152 | #define SPCMD_SPB_20BIT 0x0000 |
153 | #define SPCMD_SPB_24BIT 0x0100 | |
154 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 155 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
156 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
157 | #define SPCMD_SPIMOD1 0x0040 | |
158 | #define SPCMD_SPIMOD0 0x0020 | |
159 | #define SPCMD_SPIMOD_SINGLE 0 | |
160 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
161 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
162 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
9815ed87 | 163 | #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */ |
6ab4865b | 164 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ |
8dd71698 | 165 | #define SPCMD_BRDV(brdv) ((brdv) << 2) |
6ab4865b GU |
166 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ |
167 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
168 | ||
169 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
170 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
171 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
172 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
173 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
4b6fe3ed HCM |
174 | /* QSPI on R-Car Gen2 */ |
175 | #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */ | |
176 | #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */ | |
177 | #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */ | |
178 | #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */ | |
179 | ||
180 | #define QSPI_BUFFER_SIZE 32u | |
5ce0ba88 | 181 | |
0b2182dd SY |
182 | struct rspi_data { |
183 | void __iomem *addr; | |
e0fe7005 | 184 | u32 speed_hz; |
9428a073 | 185 | struct spi_controller *ctlr; |
f3a14a3a | 186 | struct platform_device *pdev; |
0b2182dd | 187 | wait_queue_head_t wait; |
f3a14a3a | 188 | spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */ |
0b2182dd | 189 | struct clk *clk; |
348e5153 | 190 | u16 spcmd; |
06a7a3cf GU |
191 | u8 spsr; |
192 | u8 sppcr; | |
93722206 | 193 | int rx_irq, tx_irq; |
5ce0ba88 | 194 | const struct spi_ops *ops; |
a3633fe7 | 195 | |
a3633fe7 | 196 | unsigned dma_callbacked:1; |
74da7686 | 197 | unsigned byte_access:1; |
0b2182dd SY |
198 | }; |
199 | ||
baf588f4 | 200 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
201 | { |
202 | iowrite8(data, rspi->addr + offset); | |
203 | } | |
204 | ||
baf588f4 | 205 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
206 | { |
207 | iowrite16(data, rspi->addr + offset); | |
208 | } | |
209 | ||
baf588f4 | 210 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
211 | { |
212 | iowrite32(data, rspi->addr + offset); | |
213 | } | |
214 | ||
baf588f4 | 215 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
216 | { |
217 | return ioread8(rspi->addr + offset); | |
218 | } | |
219 | ||
baf588f4 | 220 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
221 | { |
222 | return ioread16(rspi->addr + offset); | |
223 | } | |
224 | ||
74da7686 GU |
225 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
226 | { | |
227 | if (rspi->byte_access) | |
228 | rspi_write8(rspi, data, RSPI_SPDR); | |
229 | else /* 16 bit */ | |
230 | rspi_write16(rspi, data, RSPI_SPDR); | |
231 | } | |
232 | ||
233 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
234 | { | |
235 | if (rspi->byte_access) | |
236 | return rspi_read8(rspi, RSPI_SPDR); | |
237 | else /* 16 bit */ | |
238 | return rspi_read16(rspi, RSPI_SPDR); | |
239 | } | |
240 | ||
5ce0ba88 HCM |
241 | /* optional functions */ |
242 | struct spi_ops { | |
74da7686 | 243 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
9428a073 GU |
244 | int (*transfer_one)(struct spi_controller *ctlr, |
245 | struct spi_device *spi, struct spi_transfer *xfer); | |
cd982e6c | 246 | u16 extra_mode_bits; |
c3197974 GU |
247 | u16 min_div; |
248 | u16 max_div; | |
b42e0359 | 249 | u16 flags; |
2f777ec9 | 250 | u16 fifo_size; |
144d8f97 | 251 | u8 num_hw_ss; |
5ce0ba88 HCM |
252 | }; |
253 | ||
4e71d926 GU |
254 | static void rspi_set_rate(struct rspi_data *rspi) |
255 | { | |
256 | unsigned long clksrc; | |
257 | int brdv = 0, spbr; | |
258 | ||
259 | clksrc = clk_get_rate(rspi->clk); | |
260 | spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; | |
261 | while (spbr > 255 && brdv < 3) { | |
262 | brdv++; | |
263 | spbr = DIV_ROUND_UP(spbr + 1, 2) - 1; | |
264 | } | |
265 | ||
266 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
267 | rspi->spcmd |= SPCMD_BRDV(brdv); | |
cb588254 | 268 | rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1)); |
4e71d926 GU |
269 | } |
270 | ||
5ce0ba88 | 271 | /* |
862d357f | 272 | * functions for RSPI on legacy SH |
5ce0ba88 | 273 | */ |
74da7686 | 274 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 275 | { |
06a7a3cf GU |
276 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
277 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 278 | |
5ce0ba88 | 279 | /* Sets transfer bit rate */ |
4e71d926 | 280 | rspi_set_rate(rspi); |
5ce0ba88 | 281 | |
74da7686 GU |
282 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
283 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
284 | rspi->byte_access = 0; | |
0b2182dd | 285 | |
5ce0ba88 HCM |
286 | /* Sets RSPCK, SSL, next-access delay value */ |
287 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
288 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
289 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
290 | ||
291 | /* Sets parity, interrupt mask */ | |
292 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
293 | ||
26843bb1 GU |
294 | /* Resets sequencer */ |
295 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
880c6d11 GU |
296 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
297 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
298 | |
299 | /* Sets RSPI mode */ | |
300 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
301 | ||
302 | return 0; | |
0b2182dd SY |
303 | } |
304 | ||
862d357f GU |
305 | /* |
306 | * functions for RSPI on RZ | |
307 | */ | |
308 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
309 | { | |
06a7a3cf GU |
310 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
311 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
312 | |
313 | /* Sets transfer bit rate */ | |
4e71d926 | 314 | rspi_set_rate(rspi); |
862d357f GU |
315 | |
316 | /* Disable dummy transmission, set byte access */ | |
317 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
318 | rspi->byte_access = 1; | |
319 | ||
320 | /* Sets RSPCK, SSL, next-access delay value */ | |
321 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
322 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
323 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
324 | ||
26843bb1 GU |
325 | /* Resets sequencer */ |
326 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
862d357f GU |
327 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
328 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
329 | ||
330 | /* Sets RSPI mode */ | |
331 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
5ce0ba88 HCM |
336 | /* |
337 | * functions for QSPI | |
338 | */ | |
74da7686 | 339 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 340 | { |
6a195f24 GU |
341 | unsigned long clksrc; |
342 | int brdv = 0, spbr; | |
5ce0ba88 | 343 | |
06a7a3cf GU |
344 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
345 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
346 | |
347 | /* Sets transfer bit rate */ | |
6a195f24 GU |
348 | clksrc = clk_get_rate(rspi->clk); |
349 | if (rspi->speed_hz >= clksrc) { | |
350 | spbr = 0; | |
cb588254 | 351 | rspi->speed_hz = clksrc; |
6a195f24 GU |
352 | } else { |
353 | spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); | |
354 | while (spbr > 255 && brdv < 3) { | |
355 | brdv++; | |
356 | spbr = DIV_ROUND_UP(spbr, 2); | |
357 | } | |
358 | spbr = clamp(spbr, 0, 255); | |
cb588254 | 359 | rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr); |
6a195f24 GU |
360 | } |
361 | rspi_write8(rspi, spbr, RSPI_SPBR); | |
362 | rspi->spcmd |= SPCMD_BRDV(brdv); | |
5ce0ba88 | 363 | |
74da7686 GU |
364 | /* Disable dummy transmission, set byte access */ |
365 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
366 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
367 | |
368 | /* Sets RSPCK, SSL, next-access delay value */ | |
369 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
370 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
371 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
372 | ||
373 | /* Data Length Setting */ | |
374 | if (access_size == 8) | |
880c6d11 | 375 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 376 | else if (access_size == 16) |
880c6d11 | 377 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 378 | else |
880c6d11 | 379 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 380 | |
880c6d11 | 381 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
382 | |
383 | /* Resets transfer data length */ | |
384 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
385 | ||
386 | /* Resets transmit and receive buffer */ | |
387 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
388 | /* Sets buffer to allow normal operation */ | |
389 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
390 | ||
26843bb1 GU |
391 | /* Resets sequencer */ |
392 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
880c6d11 | 393 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 394 | |
b458a349 GU |
395 | /* Sets RSPI mode */ |
396 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
5ce0ba88 HCM |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
4b6fe3ed HCM |
401 | static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) |
402 | { | |
403 | u8 data; | |
404 | ||
405 | data = rspi_read8(rspi, reg); | |
406 | data &= ~mask; | |
407 | data |= (val & mask); | |
408 | rspi_write8(rspi, data, reg); | |
409 | } | |
410 | ||
cb76b1ca GU |
411 | static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, |
412 | unsigned int len) | |
4b6fe3ed HCM |
413 | { |
414 | unsigned int n; | |
415 | ||
416 | n = min(len, QSPI_BUFFER_SIZE); | |
417 | ||
418 | if (len >= QSPI_BUFFER_SIZE) { | |
419 | /* sets triggering number to 32 bytes */ | |
420 | qspi_update(rspi, SPBFCR_TXTRG_MASK, | |
421 | SPBFCR_TXTRG_32B, QSPI_SPBFCR); | |
422 | } else { | |
423 | /* sets triggering number to 1 byte */ | |
424 | qspi_update(rspi, SPBFCR_TXTRG_MASK, | |
425 | SPBFCR_TXTRG_1B, QSPI_SPBFCR); | |
426 | } | |
427 | ||
428 | return n; | |
429 | } | |
430 | ||
3be09bec | 431 | static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len) |
4b6fe3ed HCM |
432 | { |
433 | unsigned int n; | |
434 | ||
435 | n = min(len, QSPI_BUFFER_SIZE); | |
436 | ||
437 | if (len >= QSPI_BUFFER_SIZE) { | |
438 | /* sets triggering number to 32 bytes */ | |
439 | qspi_update(rspi, SPBFCR_RXTRG_MASK, | |
440 | SPBFCR_RXTRG_32B, QSPI_SPBFCR); | |
441 | } else { | |
442 | /* sets triggering number to 1 byte */ | |
443 | qspi_update(rspi, SPBFCR_RXTRG_MASK, | |
444 | SPBFCR_RXTRG_1B, QSPI_SPBFCR); | |
445 | } | |
3be09bec | 446 | return n; |
4b6fe3ed HCM |
447 | } |
448 | ||
baf588f4 | 449 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
450 | { |
451 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
452 | } | |
453 | ||
baf588f4 | 454 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
455 | { |
456 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
457 | } | |
458 | ||
459 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
460 | u8 enable_bit) | |
461 | { | |
462 | int ret; | |
463 | ||
464 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
465 | if (rspi->spsr & wait_mask) |
466 | return 0; | |
467 | ||
0b2182dd SY |
468 | rspi_enable_irq(rspi, enable_bit); |
469 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
470 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
471 | return -ETIMEDOUT; | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
5f684c34 GU |
476 | static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) |
477 | { | |
478 | return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
479 | } | |
480 | ||
481 | static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) | |
482 | { | |
483 | return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); | |
484 | } | |
485 | ||
35301c99 GU |
486 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
487 | { | |
5f684c34 GU |
488 | int error = rspi_wait_for_tx_empty(rspi); |
489 | if (error < 0) { | |
9428a073 | 490 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); |
5f684c34 | 491 | return error; |
35301c99 GU |
492 | } |
493 | rspi_write_data(rspi, data); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static int rspi_data_in(struct rspi_data *rspi) | |
498 | { | |
5f684c34 | 499 | int error; |
35301c99 GU |
500 | u8 data; |
501 | ||
5f684c34 GU |
502 | error = rspi_wait_for_rx_full(rspi); |
503 | if (error < 0) { | |
9428a073 | 504 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); |
5f684c34 | 505 | return error; |
35301c99 GU |
506 | } |
507 | data = rspi_read_data(rspi); | |
508 | return data; | |
509 | } | |
510 | ||
6837b8e9 GU |
511 | static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, |
512 | unsigned int n) | |
35301c99 | 513 | { |
6837b8e9 GU |
514 | while (n-- > 0) { |
515 | if (tx) { | |
516 | int ret = rspi_data_out(rspi, *tx++); | |
517 | if (ret < 0) | |
518 | return ret; | |
519 | } | |
520 | if (rx) { | |
521 | int ret = rspi_data_in(rspi); | |
522 | if (ret < 0) | |
523 | return ret; | |
524 | *rx++ = ret; | |
525 | } | |
526 | } | |
35301c99 | 527 | |
6837b8e9 | 528 | return 0; |
35301c99 GU |
529 | } |
530 | ||
a3633fe7 SY |
531 | static void rspi_dma_complete(void *arg) |
532 | { | |
533 | struct rspi_data *rspi = arg; | |
534 | ||
535 | rspi->dma_callbacked = 1; | |
536 | wake_up_interruptible(&rspi->wait); | |
537 | } | |
538 | ||
c52fb6d6 GU |
539 | static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, |
540 | struct sg_table *rx) | |
a3633fe7 | 541 | { |
c52fb6d6 GU |
542 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; |
543 | u8 irq_mask = 0; | |
544 | unsigned int other_irq = 0; | |
545 | dma_cookie_t cookie; | |
2f777ec9 | 546 | int ret; |
a3633fe7 | 547 | |
3819bc87 | 548 | /* First prepare and submit the DMA request(s), as this may fail */ |
c52fb6d6 | 549 | if (rx) { |
9428a073 GU |
550 | desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, |
551 | rx->nents, DMA_DEV_TO_MEM, | |
c52fb6d6 | 552 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
3819bc87 GU |
553 | if (!desc_rx) { |
554 | ret = -EAGAIN; | |
555 | goto no_dma_rx; | |
556 | } | |
557 | ||
558 | desc_rx->callback = rspi_dma_complete; | |
559 | desc_rx->callback_param = rspi; | |
560 | cookie = dmaengine_submit(desc_rx); | |
561 | if (dma_submit_error(cookie)) { | |
562 | ret = cookie; | |
563 | goto no_dma_rx; | |
564 | } | |
c52fb6d6 GU |
565 | |
566 | irq_mask |= SPCR_SPRIE; | |
567 | } | |
a3633fe7 | 568 | |
3819bc87 | 569 | if (tx) { |
9428a073 GU |
570 | desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, |
571 | tx->nents, DMA_MEM_TO_DEV, | |
3819bc87 GU |
572 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
573 | if (!desc_tx) { | |
574 | ret = -EAGAIN; | |
575 | goto no_dma_tx; | |
576 | } | |
577 | ||
578 | if (rx) { | |
579 | /* No callback */ | |
580 | desc_tx->callback = NULL; | |
581 | } else { | |
582 | desc_tx->callback = rspi_dma_complete; | |
583 | desc_tx->callback_param = rspi; | |
584 | } | |
585 | cookie = dmaengine_submit(desc_tx); | |
586 | if (dma_submit_error(cookie)) { | |
587 | ret = cookie; | |
588 | goto no_dma_tx; | |
589 | } | |
590 | ||
591 | irq_mask |= SPCR_SPTIE; | |
592 | } | |
593 | ||
a3633fe7 | 594 | /* |
c52fb6d6 | 595 | * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be |
a3633fe7 SY |
596 | * called. So, this driver disables the IRQ while DMA transfer. |
597 | */ | |
c52fb6d6 GU |
598 | if (tx) |
599 | disable_irq(other_irq = rspi->tx_irq); | |
600 | if (rx && rspi->rx_irq != other_irq) | |
601 | disable_irq(rspi->rx_irq); | |
a3633fe7 | 602 | |
c52fb6d6 | 603 | rspi_enable_irq(rspi, irq_mask); |
a3633fe7 SY |
604 | rspi->dma_callbacked = 0; |
605 | ||
3819bc87 GU |
606 | /* Now start DMA */ |
607 | if (rx) | |
9428a073 | 608 | dma_async_issue_pending(rspi->ctlr->dma_rx); |
3819bc87 | 609 | if (tx) |
9428a073 | 610 | dma_async_issue_pending(rspi->ctlr->dma_tx); |
a3633fe7 SY |
611 | |
612 | ret = wait_event_interruptible_timeout(rspi->wait, | |
613 | rspi->dma_callbacked, HZ); | |
8dbbaa47 | 614 | if (ret > 0 && rspi->dma_callbacked) { |
a3633fe7 | 615 | ret = 0; |
b620aa3a BD |
616 | if (tx) |
617 | dmaengine_synchronize(rspi->ctlr->dma_tx); | |
618 | if (rx) | |
619 | dmaengine_synchronize(rspi->ctlr->dma_rx); | |
8dbbaa47 GU |
620 | } else { |
621 | if (!ret) { | |
9428a073 | 622 | dev_err(&rspi->ctlr->dev, "DMA timeout\n"); |
8dbbaa47 GU |
623 | ret = -ETIMEDOUT; |
624 | } | |
3819bc87 | 625 | if (tx) |
29176edd | 626 | dmaengine_terminate_sync(rspi->ctlr->dma_tx); |
3819bc87 | 627 | if (rx) |
29176edd | 628 | dmaengine_terminate_sync(rspi->ctlr->dma_rx); |
3819bc87 | 629 | } |
a3633fe7 | 630 | |
c52fb6d6 GU |
631 | rspi_disable_irq(rspi, irq_mask); |
632 | ||
633 | if (tx) | |
634 | enable_irq(rspi->tx_irq); | |
635 | if (rx && rspi->rx_irq != other_irq) | |
636 | enable_irq(rspi->rx_irq); | |
637 | ||
a3633fe7 | 638 | return ret; |
85912a88 | 639 | |
3819bc87 GU |
640 | no_dma_tx: |
641 | if (rx) | |
29176edd | 642 | dmaengine_terminate_sync(rspi->ctlr->dma_rx); |
3819bc87 GU |
643 | no_dma_rx: |
644 | if (ret == -EAGAIN) { | |
1bec84dd GU |
645 | dev_warn_once(&rspi->ctlr->dev, |
646 | "DMA not available, falling back to PIO\n"); | |
3819bc87 GU |
647 | } |
648 | return ret; | |
a3633fe7 SY |
649 | } |
650 | ||
baf588f4 | 651 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 652 | { |
97b95c11 | 653 | u8 spsr; |
0b2182dd SY |
654 | |
655 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
656 | if (spsr & SPSR_SPRF) | |
74da7686 | 657 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
658 | if (spsr & SPSR_OVRF) |
659 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 660 | RSPI_SPSR); |
a3633fe7 SY |
661 | } |
662 | ||
862d357f GU |
663 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
664 | { | |
665 | rspi_receive_init(rspi); | |
666 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
667 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
668 | } | |
669 | ||
baf588f4 | 670 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 671 | { |
97b95c11 | 672 | u8 spsr; |
cb52c673 HCM |
673 | |
674 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
675 | if (spsr & SPSR_SPRF) | |
74da7686 | 676 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 677 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 678 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
679 | } |
680 | ||
2f777ec9 GU |
681 | static bool __rspi_can_dma(const struct rspi_data *rspi, |
682 | const struct spi_transfer *xfer) | |
a3633fe7 | 683 | { |
2f777ec9 GU |
684 | return xfer->len > rspi->ops->fifo_size; |
685 | } | |
a3633fe7 | 686 | |
9428a073 | 687 | static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, |
2f777ec9 GU |
688 | struct spi_transfer *xfer) |
689 | { | |
9428a073 | 690 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
2f777ec9 GU |
691 | |
692 | return __rspi_can_dma(rspi, xfer); | |
a3633fe7 SY |
693 | } |
694 | ||
4b6fe3ed HCM |
695 | static int rspi_dma_check_then_transfer(struct rspi_data *rspi, |
696 | struct spi_transfer *xfer) | |
8b983e90 | 697 | { |
9428a073 | 698 | if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) |
6310372d | 699 | return -EAGAIN; |
8b983e90 | 700 | |
6310372d HCM |
701 | /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ |
702 | return rspi_dma_transfer(rspi, &xfer->tx_sg, | |
703 | xfer->rx_buf ? &xfer->rx_sg : NULL); | |
4b6fe3ed HCM |
704 | } |
705 | ||
706 | static int rspi_common_transfer(struct rspi_data *rspi, | |
707 | struct spi_transfer *xfer) | |
708 | { | |
709 | int ret; | |
710 | ||
cb588254 GU |
711 | xfer->effective_speed_hz = rspi->speed_hz; |
712 | ||
4b6fe3ed HCM |
713 | ret = rspi_dma_check_then_transfer(rspi, xfer); |
714 | if (ret != -EAGAIN) | |
715 | return ret; | |
716 | ||
8b983e90 GU |
717 | ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); |
718 | if (ret < 0) | |
719 | return ret; | |
720 | ||
721 | /* Wait for the last transmission */ | |
722 | rspi_wait_for_tx_empty(rspi); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
9428a073 GU |
727 | static int rspi_transfer_one(struct spi_controller *ctlr, |
728 | struct spi_device *spi, struct spi_transfer *xfer) | |
8449fd76 | 729 | { |
9428a073 | 730 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
b42e0359 | 731 | u8 spcr; |
8449fd76 | 732 | |
8449fd76 | 733 | spcr = rspi_read8(rspi, RSPI_SPCR); |
6837b8e9 | 734 | if (xfer->rx_buf) { |
32c64261 | 735 | rspi_receive_init(rspi); |
8449fd76 | 736 | spcr &= ~SPCR_TXMD; |
32c64261 | 737 | } else { |
8449fd76 | 738 | spcr |= SPCR_TXMD; |
32c64261 | 739 | } |
8449fd76 GU |
740 | rspi_write8(rspi, spcr, RSPI_SPCR); |
741 | ||
8b983e90 | 742 | return rspi_common_transfer(rspi, xfer); |
8449fd76 GU |
743 | } |
744 | ||
9428a073 | 745 | static int rspi_rz_transfer_one(struct spi_controller *ctlr, |
03e627c5 GU |
746 | struct spi_device *spi, |
747 | struct spi_transfer *xfer) | |
862d357f | 748 | { |
9428a073 | 749 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
862d357f GU |
750 | |
751 | rspi_rz_receive_init(rspi); | |
752 | ||
8b983e90 | 753 | return rspi_common_transfer(rspi, xfer); |
862d357f GU |
754 | } |
755 | ||
a91bbe7d | 756 | static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, |
4b6fe3ed HCM |
757 | u8 *rx, unsigned int len) |
758 | { | |
cb76b1ca GU |
759 | unsigned int i, n; |
760 | int ret; | |
4b6fe3ed HCM |
761 | |
762 | while (len > 0) { | |
763 | n = qspi_set_send_trigger(rspi, len); | |
764 | qspi_set_receive_trigger(rspi, len); | |
7e95b166 HNA |
765 | ret = rspi_wait_for_tx_empty(rspi); |
766 | if (ret < 0) { | |
767 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); | |
768 | return ret; | |
769 | } | |
770 | for (i = 0; i < n; i++) | |
771 | rspi_write_data(rspi, *tx++); | |
4b6fe3ed | 772 | |
7e95b166 HNA |
773 | ret = rspi_wait_for_rx_full(rspi); |
774 | if (ret < 0) { | |
775 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); | |
776 | return ret; | |
4b6fe3ed | 777 | } |
7e95b166 HNA |
778 | for (i = 0; i < n; i++) |
779 | *rx++ = rspi_read_data(rspi); | |
780 | ||
4b6fe3ed HCM |
781 | len -= n; |
782 | } | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
340a15e6 GU |
787 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
788 | struct spi_transfer *xfer) | |
eb557f75 | 789 | { |
4b6fe3ed HCM |
790 | int ret; |
791 | ||
340a15e6 GU |
792 | qspi_receive_init(rspi); |
793 | ||
4b6fe3ed HCM |
794 | ret = rspi_dma_check_then_transfer(rspi, xfer); |
795 | if (ret != -EAGAIN) | |
796 | return ret; | |
797 | ||
cc2e9328 | 798 | return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, |
4b6fe3ed | 799 | xfer->rx_buf, xfer->len); |
340a15e6 GU |
800 | } |
801 | ||
880c6d11 GU |
802 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
803 | { | |
db300838 AB |
804 | const u8 *tx = xfer->tx_buf; |
805 | unsigned int n = xfer->len; | |
806 | unsigned int i, len; | |
880c6d11 GU |
807 | int ret; |
808 | ||
9428a073 | 809 | if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { |
85912a88 GU |
810 | ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); |
811 | if (ret != -EAGAIN) | |
812 | return ret; | |
813 | } | |
4f12b5e5 | 814 | |
db300838 AB |
815 | while (n > 0) { |
816 | len = qspi_set_send_trigger(rspi, n); | |
7e95b166 HNA |
817 | ret = rspi_wait_for_tx_empty(rspi); |
818 | if (ret < 0) { | |
819 | dev_err(&rspi->ctlr->dev, "transmit timeout\n"); | |
820 | return ret; | |
db300838 | 821 | } |
7e95b166 HNA |
822 | for (i = 0; i < len; i++) |
823 | rspi_write_data(rspi, *tx++); | |
824 | ||
db300838 AB |
825 | n -= len; |
826 | } | |
880c6d11 GU |
827 | |
828 | /* Wait for the last transmission */ | |
5f684c34 | 829 | rspi_wait_for_tx_empty(rspi); |
880c6d11 GU |
830 | |
831 | return 0; | |
832 | } | |
833 | ||
834 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
835 | { | |
db300838 AB |
836 | u8 *rx = xfer->rx_buf; |
837 | unsigned int n = xfer->len; | |
838 | unsigned int i, len; | |
839 | int ret; | |
840 | ||
9428a073 | 841 | if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { |
1d734f59 | 842 | ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); |
85912a88 GU |
843 | if (ret != -EAGAIN) |
844 | return ret; | |
845 | } | |
4f12b5e5 | 846 | |
db300838 AB |
847 | while (n > 0) { |
848 | len = qspi_set_receive_trigger(rspi, n); | |
7e95b166 HNA |
849 | ret = rspi_wait_for_rx_full(rspi); |
850 | if (ret < 0) { | |
851 | dev_err(&rspi->ctlr->dev, "receive timeout\n"); | |
852 | return ret; | |
db300838 | 853 | } |
7e95b166 HNA |
854 | for (i = 0; i < len; i++) |
855 | *rx++ = rspi_read_data(rspi); | |
856 | ||
db300838 AB |
857 | n -= len; |
858 | } | |
859 | ||
860 | return 0; | |
880c6d11 GU |
861 | } |
862 | ||
9428a073 GU |
863 | static int qspi_transfer_one(struct spi_controller *ctlr, |
864 | struct spi_device *spi, struct spi_transfer *xfer) | |
340a15e6 | 865 | { |
9428a073 | 866 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
340a15e6 | 867 | |
cb588254 | 868 | xfer->effective_speed_hz = rspi->speed_hz; |
ba824d49 GU |
869 | if (spi->mode & SPI_LOOP) { |
870 | return qspi_transfer_out_in(rspi, xfer); | |
b42e0359 | 871 | } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
872 | /* Quad or Dual SPI Write */ |
873 | return qspi_transfer_out(rspi, xfer); | |
b42e0359 | 874 | } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
875 | /* Quad or Dual SPI Read */ |
876 | return qspi_transfer_in(rspi, xfer); | |
877 | } else { | |
878 | /* Single SPI Transfer */ | |
879 | return qspi_transfer_out_in(rspi, xfer); | |
880 | } | |
0b2182dd SY |
881 | } |
882 | ||
880c6d11 GU |
883 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
884 | { | |
885 | if (xfer->tx_buf) | |
886 | switch (xfer->tx_nbits) { | |
887 | case SPI_NBITS_QUAD: | |
888 | return SPCMD_SPIMOD_QUAD; | |
889 | case SPI_NBITS_DUAL: | |
890 | return SPCMD_SPIMOD_DUAL; | |
891 | default: | |
892 | return 0; | |
893 | } | |
894 | if (xfer->rx_buf) | |
895 | switch (xfer->rx_nbits) { | |
896 | case SPI_NBITS_QUAD: | |
897 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
898 | case SPI_NBITS_DUAL: | |
899 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
900 | default: | |
901 | return 0; | |
902 | } | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
908 | const struct spi_message *msg) | |
909 | { | |
910 | const struct spi_transfer *xfer; | |
911 | unsigned int i = 0, len = 0; | |
912 | u16 current_mode = 0xffff, mode; | |
913 | ||
914 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
915 | mode = qspi_transfer_mode(xfer); | |
916 | if (mode == current_mode) { | |
917 | len += xfer->len; | |
918 | continue; | |
919 | } | |
920 | ||
921 | /* Transfer mode change */ | |
922 | if (i) { | |
923 | /* Set transfer data length of previous transfer */ | |
924 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
925 | } | |
926 | ||
927 | if (i >= QSPI_NUM_SPCMD) { | |
928 | dev_err(&msg->spi->dev, | |
929 | "Too many different transfer modes"); | |
930 | return -EINVAL; | |
931 | } | |
932 | ||
933 | /* Program transfer mode for this transfer */ | |
934 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
935 | current_mode = mode; | |
936 | len = xfer->len; | |
937 | i++; | |
938 | } | |
939 | if (i) { | |
940 | /* Set final transfer data length and sequence length */ | |
941 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
942 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
943 | } | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
f3a14a3a GU |
948 | static int rspi_setup(struct spi_device *spi) |
949 | { | |
950 | struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); | |
951 | u8 sslp; | |
952 | ||
9e264f3f | 953 | if (spi_get_csgpiod(spi, 0)) |
f3a14a3a GU |
954 | return 0; |
955 | ||
956 | pm_runtime_get_sync(&rspi->pdev->dev); | |
957 | spin_lock_irq(&rspi->lock); | |
958 | ||
959 | sslp = rspi_read8(rspi, RSPI_SSLP); | |
960 | if (spi->mode & SPI_CS_HIGH) | |
9e264f3f | 961 | sslp |= SSLP_SSLP(spi_get_chipselect(spi, 0)); |
f3a14a3a | 962 | else |
9e264f3f | 963 | sslp &= ~SSLP_SSLP(spi_get_chipselect(spi, 0)); |
f3a14a3a GU |
964 | rspi_write8(rspi, sslp, RSPI_SSLP); |
965 | ||
966 | spin_unlock_irq(&rspi->lock); | |
967 | pm_runtime_put(&rspi->pdev->dev); | |
968 | return 0; | |
969 | } | |
970 | ||
9428a073 | 971 | static int rspi_prepare_message(struct spi_controller *ctlr, |
880c6d11 | 972 | struct spi_message *msg) |
79d23495 | 973 | { |
9428a073 | 974 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
42bdaaec | 975 | struct spi_device *spi = msg->spi; |
e0fe7005 | 976 | const struct spi_transfer *xfer; |
880c6d11 | 977 | int ret; |
0b2182dd | 978 | |
e0fe7005 GU |
979 | /* |
980 | * As the Bit Rate Register must not be changed while the device is | |
981 | * active, all transfers in a message must use the same bit rate. | |
982 | * In theory, the sequencer could be enabled, and each Command Register | |
983 | * could divide the base bit rate by a different value. | |
984 | * However, most RSPI variants do not have Transfer Data Length | |
985 | * Multiplier Setting Registers, so each sequence step would be limited | |
986 | * to a single word, making this feature unsuitable for large | |
987 | * transfers, which would gain most from it. | |
988 | */ | |
989 | rspi->speed_hz = spi->max_speed_hz; | |
990 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
991 | if (xfer->speed_hz < rspi->speed_hz) | |
992 | rspi->speed_hz = xfer->speed_hz; | |
993 | } | |
42bdaaec GU |
994 | |
995 | rspi->spcmd = SPCMD_SSLKP; | |
996 | if (spi->mode & SPI_CPOL) | |
997 | rspi->spcmd |= SPCMD_CPOL; | |
998 | if (spi->mode & SPI_CPHA) | |
999 | rspi->spcmd |= SPCMD_CPHA; | |
c046f8fd GU |
1000 | if (spi->mode & SPI_LSB_FIRST) |
1001 | rspi->spcmd |= SPCMD_LSBF; | |
42bdaaec | 1002 | |
9815ed87 | 1003 | /* Configure slave signal to assert */ |
9e264f3f AKMA |
1004 | rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs |
1005 | : spi_get_chipselect(spi, 0)); | |
9815ed87 | 1006 | |
42bdaaec GU |
1007 | /* CMOS output mode and MOSI signal from previous transfer */ |
1008 | rspi->sppcr = 0; | |
1009 | if (spi->mode & SPI_LOOP) | |
1010 | rspi->sppcr |= SPPCR_SPLP; | |
1011 | ||
8f2344fa | 1012 | rspi->ops->set_config_register(rspi, 8); |
42bdaaec | 1013 | |
880c6d11 GU |
1014 | if (msg->spi->mode & |
1015 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
1016 | /* Setup sequencer for messages with multiple transfer modes */ | |
1017 | ret = qspi_setup_sequencer(rspi, msg); | |
1018 | if (ret < 0) | |
1019 | return ret; | |
1020 | } | |
1021 | ||
1022 | /* Enable SPI function in master mode */ | |
79d23495 | 1023 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
1024 | return 0; |
1025 | } | |
1026 | ||
9428a073 | 1027 | static int rspi_unprepare_message(struct spi_controller *ctlr, |
880c6d11 | 1028 | struct spi_message *msg) |
0b2182dd | 1029 | { |
9428a073 | 1030 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr); |
79d23495 | 1031 | |
880c6d11 | 1032 | /* Disable SPI function */ |
79d23495 | 1033 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
1034 | |
1035 | /* Reset sequencer for Single SPI Transfers */ | |
1036 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
1037 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 1038 | return 0; |
0b2182dd SY |
1039 | } |
1040 | ||
93722206 | 1041 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 1042 | { |
c132f094 | 1043 | struct rspi_data *rspi = _sr; |
97b95c11 | 1044 | u8 spsr; |
0b2182dd | 1045 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 1046 | u8 disable_irq = 0; |
0b2182dd SY |
1047 | |
1048 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1049 | if (spsr & SPSR_SPRF) | |
1050 | disable_irq |= SPCR_SPRIE; | |
1051 | if (spsr & SPSR_SPTEF) | |
1052 | disable_irq |= SPCR_SPTIE; | |
1053 | ||
1054 | if (disable_irq) { | |
1055 | ret = IRQ_HANDLED; | |
1056 | rspi_disable_irq(rspi, disable_irq); | |
1057 | wake_up(&rspi->wait); | |
1058 | } | |
1059 | ||
1060 | return ret; | |
1061 | } | |
1062 | ||
93722206 GU |
1063 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
1064 | { | |
1065 | struct rspi_data *rspi = _sr; | |
1066 | u8 spsr; | |
1067 | ||
1068 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1069 | if (spsr & SPSR_SPRF) { | |
1070 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
1071 | wake_up(&rspi->wait); | |
1072 | return IRQ_HANDLED; | |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
1079 | { | |
1080 | struct rspi_data *rspi = _sr; | |
1081 | u8 spsr; | |
1082 | ||
1083 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1084 | if (spsr & SPSR_SPTEF) { | |
1085 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
1086 | wake_up(&rspi->wait); | |
1087 | return IRQ_HANDLED; | |
1088 | } | |
1089 | ||
1090 | return 0; | |
1091 | } | |
1092 | ||
65bf2205 GU |
1093 | static struct dma_chan *rspi_request_dma_chan(struct device *dev, |
1094 | enum dma_transfer_direction dir, | |
1095 | unsigned int id, | |
1096 | dma_addr_t port_addr) | |
a3633fe7 | 1097 | { |
a3633fe7 | 1098 | dma_cap_mask_t mask; |
65bf2205 | 1099 | struct dma_chan *chan; |
0243c536 SY |
1100 | struct dma_slave_config cfg; |
1101 | int ret; | |
a3633fe7 | 1102 | |
65bf2205 GU |
1103 | dma_cap_zero(mask); |
1104 | dma_cap_set(DMA_SLAVE, mask); | |
1105 | ||
e825b8dd GU |
1106 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
1107 | (void *)(unsigned long)id, dev, | |
1108 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
65bf2205 | 1109 | if (!chan) { |
e825b8dd | 1110 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
65bf2205 GU |
1111 | return NULL; |
1112 | } | |
1113 | ||
1114 | memset(&cfg, 0, sizeof(cfg)); | |
6f381481 BD |
1115 | cfg.dst_addr = port_addr + RSPI_SPDR; |
1116 | cfg.src_addr = port_addr + RSPI_SPDR; | |
1117 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1118 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
65bf2205 | 1119 | cfg.direction = dir; |
65bf2205 GU |
1120 | |
1121 | ret = dmaengine_slave_config(chan, &cfg); | |
1122 | if (ret) { | |
1123 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
1124 | dma_release_channel(chan); | |
1125 | return NULL; | |
1126 | } | |
1127 | ||
1128 | return chan; | |
1129 | } | |
1130 | ||
9428a073 | 1131 | static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr, |
fcdc49ae | 1132 | const struct resource *res) |
65bf2205 | 1133 | { |
fcdc49ae | 1134 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); |
e825b8dd GU |
1135 | unsigned int dma_tx_id, dma_rx_id; |
1136 | ||
1137 | if (dev->of_node) { | |
1138 | /* In the OF case we will get the slave IDs from the DT */ | |
1139 | dma_tx_id = 0; | |
1140 | dma_rx_id = 0; | |
1141 | } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { | |
1142 | dma_tx_id = rspi_pd->dma_tx_id; | |
1143 | dma_rx_id = rspi_pd->dma_rx_id; | |
1144 | } else { | |
1145 | /* The driver assumes no error. */ | |
1146 | return 0; | |
1147 | } | |
65bf2205 | 1148 | |
9428a073 | 1149 | ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, |
6f381481 | 1150 | res->start); |
9428a073 | 1151 | if (!ctlr->dma_tx) |
5f338d0c GU |
1152 | return -ENODEV; |
1153 | ||
9428a073 | 1154 | ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, |
6f381481 | 1155 | res->start); |
9428a073 GU |
1156 | if (!ctlr->dma_rx) { |
1157 | dma_release_channel(ctlr->dma_tx); | |
1158 | ctlr->dma_tx = NULL; | |
5f338d0c | 1159 | return -ENODEV; |
a3633fe7 | 1160 | } |
0243c536 | 1161 | |
9428a073 | 1162 | ctlr->can_dma = rspi_can_dma; |
5f338d0c | 1163 | dev_info(dev, "DMA available"); |
0243c536 | 1164 | return 0; |
a3633fe7 SY |
1165 | } |
1166 | ||
9428a073 | 1167 | static void rspi_release_dma(struct spi_controller *ctlr) |
a3633fe7 | 1168 | { |
9428a073 GU |
1169 | if (ctlr->dma_tx) |
1170 | dma_release_channel(ctlr->dma_tx); | |
1171 | if (ctlr->dma_rx) | |
1172 | dma_release_channel(ctlr->dma_rx); | |
a3633fe7 SY |
1173 | } |
1174 | ||
72ec0e8f | 1175 | static void rspi_remove(struct platform_device *pdev) |
0b2182dd | 1176 | { |
5ffbe2d9 | 1177 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 1178 | |
9428a073 | 1179 | rspi_release_dma(rspi->ctlr); |
490c9774 | 1180 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1181 | } |
1182 | ||
426ef76d | 1183 | static const struct spi_ops rspi_ops = { |
b42e0359 GU |
1184 | .set_config_register = rspi_set_config_register, |
1185 | .transfer_one = rspi_transfer_one, | |
c3197974 GU |
1186 | .min_div = 2, |
1187 | .max_div = 4096, | |
9428a073 | 1188 | .flags = SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1189 | .fifo_size = 8, |
144d8f97 | 1190 | .num_hw_ss = 2, |
426ef76d GU |
1191 | }; |
1192 | ||
edfa9703 | 1193 | static const struct spi_ops rspi_rz_ops __maybe_unused = { |
b42e0359 GU |
1194 | .set_config_register = rspi_rz_set_config_register, |
1195 | .transfer_one = rspi_rz_transfer_one, | |
c3197974 GU |
1196 | .min_div = 2, |
1197 | .max_div = 4096, | |
9428a073 | 1198 | .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1199 | .fifo_size = 8, /* 8 for TX, 32 for RX */ |
144d8f97 | 1200 | .num_hw_ss = 1, |
426ef76d GU |
1201 | }; |
1202 | ||
edfa9703 | 1203 | static const struct spi_ops qspi_ops __maybe_unused = { |
b42e0359 GU |
1204 | .set_config_register = qspi_set_config_register, |
1205 | .transfer_one = qspi_transfer_one, | |
cd982e6c | 1206 | .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | |
b42e0359 | 1207 | SPI_RX_DUAL | SPI_RX_QUAD, |
c3197974 GU |
1208 | .min_div = 1, |
1209 | .max_div = 4080, | |
9428a073 | 1210 | .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, |
2f777ec9 | 1211 | .fifo_size = 32, |
144d8f97 | 1212 | .num_hw_ss = 1, |
426ef76d GU |
1213 | }; |
1214 | ||
edfa9703 | 1215 | static const struct of_device_id rspi_of_match[] __maybe_unused = { |
426ef76d GU |
1216 | /* RSPI on legacy SH */ |
1217 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1218 | /* RSPI on RZ/A1H */ | |
1219 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1220 | /* QSPI on R-Car Gen2 */ | |
1221 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1222 | { /* sentinel */ } | |
1223 | }; | |
1224 | ||
1225 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1226 | ||
edfa9703 | 1227 | #ifdef CONFIG_OF |
aadbff4a LP |
1228 | static void rspi_reset_control_assert(void *data) |
1229 | { | |
1230 | reset_control_assert(data); | |
1231 | } | |
1232 | ||
9428a073 | 1233 | static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) |
426ef76d | 1234 | { |
aadbff4a | 1235 | struct reset_control *rstc; |
426ef76d GU |
1236 | u32 num_cs; |
1237 | int error; | |
1238 | ||
1239 | /* Parse DT properties */ | |
1240 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1241 | if (error) { | |
1242 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1243 | return error; | |
1244 | } | |
1245 | ||
9428a073 | 1246 | ctlr->num_chipselect = num_cs; |
aadbff4a LP |
1247 | |
1248 | rstc = devm_reset_control_get_optional_exclusive(dev, NULL); | |
1249 | if (IS_ERR(rstc)) | |
1250 | return dev_err_probe(dev, PTR_ERR(rstc), | |
1251 | "failed to get reset ctrl\n"); | |
1252 | ||
1253 | error = reset_control_deassert(rstc); | |
1254 | if (error) { | |
1255 | dev_err(dev, "failed to deassert reset %d\n", error); | |
1256 | return error; | |
1257 | } | |
1258 | ||
1259 | error = devm_add_action_or_reset(dev, rspi_reset_control_assert, rstc); | |
1260 | if (error) { | |
1261 | dev_err(dev, "failed to register assert devm action, %d\n", error); | |
1262 | return error; | |
1263 | } | |
1264 | ||
426ef76d GU |
1265 | return 0; |
1266 | } | |
1267 | #else | |
64b67def | 1268 | #define rspi_of_match NULL |
9428a073 | 1269 | static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) |
426ef76d GU |
1270 | { |
1271 | return -EINVAL; | |
1272 | } | |
1273 | #endif /* CONFIG_OF */ | |
1274 | ||
93722206 GU |
1275 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1276 | irq_handler_t handler, const char *suffix, | |
1277 | void *dev_id) | |
1278 | { | |
43937455 GU |
1279 | const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", |
1280 | dev_name(dev), suffix); | |
93722206 GU |
1281 | if (!name) |
1282 | return -ENOMEM; | |
43937455 | 1283 | |
93722206 GU |
1284 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); |
1285 | } | |
1286 | ||
fd4a319b | 1287 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1288 | { |
1289 | struct resource *res; | |
9428a073 | 1290 | struct spi_controller *ctlr; |
0b2182dd | 1291 | struct rspi_data *rspi; |
93722206 | 1292 | int ret; |
426ef76d | 1293 | const struct rspi_plat_data *rspi_pd; |
5ce0ba88 | 1294 | const struct spi_ops *ops; |
c3197974 | 1295 | unsigned long clksrc; |
0b2182dd | 1296 | |
1405efe7 | 1297 | ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rspi_data)); |
9428a073 | 1298 | if (ctlr == NULL) |
0b2182dd | 1299 | return -ENOMEM; |
0b2182dd | 1300 | |
219a7bc5 GU |
1301 | ops = of_device_get_match_data(&pdev->dev); |
1302 | if (ops) { | |
9428a073 | 1303 | ret = rspi_parse_dt(&pdev->dev, ctlr); |
426ef76d GU |
1304 | if (ret) |
1305 | goto error1; | |
1306 | } else { | |
1307 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1308 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1309 | if (rspi_pd && rspi_pd->num_chipselect) | |
9428a073 | 1310 | ctlr->num_chipselect = rspi_pd->num_chipselect; |
426ef76d | 1311 | else |
9428a073 | 1312 | ctlr->num_chipselect = 2; /* default */ |
d64b4726 | 1313 | } |
426ef76d | 1314 | |
9428a073 | 1315 | rspi = spi_controller_get_devdata(ctlr); |
24b5a82c | 1316 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1317 | rspi->ops = ops; |
9428a073 | 1318 | rspi->ctlr = ctlr; |
5d79e9ac | 1319 | |
b778d967 | 1320 | rspi->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
5d79e9ac LP |
1321 | if (IS_ERR(rspi->addr)) { |
1322 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1323 | goto error1; |
1324 | } | |
1325 | ||
29f397b7 | 1326 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1327 | if (IS_ERR(rspi->clk)) { |
1328 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1329 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1330 | goto error1; |
0b2182dd | 1331 | } |
17fe0d9a | 1332 | |
f3a14a3a | 1333 | rspi->pdev = pdev; |
490c9774 | 1334 | pm_runtime_enable(&pdev->dev); |
0b2182dd | 1335 | |
0b2182dd | 1336 | init_waitqueue_head(&rspi->wait); |
f3a14a3a | 1337 | spin_lock_init(&rspi->lock); |
0b2182dd | 1338 | |
9428a073 | 1339 | ctlr->bus_num = pdev->id; |
f3a14a3a | 1340 | ctlr->setup = rspi_setup; |
9428a073 GU |
1341 | ctlr->auto_runtime_pm = true; |
1342 | ctlr->transfer_one = ops->transfer_one; | |
1343 | ctlr->prepare_message = rspi_prepare_message; | |
1344 | ctlr->unprepare_message = rspi_unprepare_message; | |
f3a14a3a GU |
1345 | ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | |
1346 | SPI_LOOP | ops->extra_mode_bits; | |
c3197974 GU |
1347 | clksrc = clk_get_rate(rspi->clk); |
1348 | ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div); | |
1349 | ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div); | |
9428a073 GU |
1350 | ctlr->flags = ops->flags; |
1351 | ctlr->dev.of_node = pdev->dev.of_node; | |
144d8f97 GU |
1352 | ctlr->use_gpio_descriptors = true; |
1353 | ctlr->max_native_cs = rspi->ops->num_hw_ss; | |
0b2182dd | 1354 | |
2de860b4 | 1355 | ret = platform_get_irq_byname_optional(pdev, "rx"); |
93722206 | 1356 | if (ret < 0) { |
2de860b4 | 1357 | ret = platform_get_irq_byname_optional(pdev, "mux"); |
93722206 GU |
1358 | if (ret < 0) |
1359 | ret = platform_get_irq(pdev, 0); | |
1360 | if (ret >= 0) | |
1361 | rspi->rx_irq = rspi->tx_irq = ret; | |
1362 | } else { | |
1363 | rspi->rx_irq = ret; | |
1364 | ret = platform_get_irq_byname(pdev, "tx"); | |
1365 | if (ret >= 0) | |
1366 | rspi->tx_irq = ret; | |
1367 | } | |
93722206 GU |
1368 | |
1369 | if (rspi->rx_irq == rspi->tx_irq) { | |
1370 | /* Single multiplexed interrupt */ | |
1371 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1372 | "mux", rspi); | |
1373 | } else { | |
1374 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1375 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1376 | "rx", rspi); | |
1377 | if (!ret) | |
1378 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1379 | rspi_irq_tx, "tx", rspi); | |
1380 | } | |
0b2182dd SY |
1381 | if (ret < 0) { |
1382 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1383 | goto error2; |
0b2182dd SY |
1384 | } |
1385 | ||
9428a073 | 1386 | ret = rspi_request_dma(&pdev->dev, ctlr, res); |
27e105a6 GU |
1387 | if (ret < 0) |
1388 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
a3633fe7 | 1389 | |
9428a073 | 1390 | ret = devm_spi_register_controller(&pdev->dev, ctlr); |
0b2182dd | 1391 | if (ret < 0) { |
9428a073 | 1392 | dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); |
fcb4ed74 | 1393 | goto error3; |
0b2182dd SY |
1394 | } |
1395 | ||
1396 | dev_info(&pdev->dev, "probed\n"); | |
1397 | ||
1398 | return 0; | |
1399 | ||
fcb4ed74 | 1400 | error3: |
9428a073 | 1401 | rspi_release_dma(ctlr); |
fcb4ed74 | 1402 | error2: |
490c9774 | 1403 | pm_runtime_disable(&pdev->dev); |
0b2182dd | 1404 | error1: |
9428a073 | 1405 | spi_controller_put(ctlr); |
0b2182dd SY |
1406 | |
1407 | return ret; | |
1408 | } | |
1409 | ||
8634dafa | 1410 | static const struct platform_device_id spi_driver_ids[] = { |
5ce0ba88 | 1411 | { "rspi", (kernel_ulong_t)&rspi_ops }, |
5ce0ba88 HCM |
1412 | {}, |
1413 | }; | |
1414 | ||
1415 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1416 | ||
c1ca59c2 GU |
1417 | #ifdef CONFIG_PM_SLEEP |
1418 | static int rspi_suspend(struct device *dev) | |
1419 | { | |
be0bf62e | 1420 | struct rspi_data *rspi = dev_get_drvdata(dev); |
c1ca59c2 | 1421 | |
9428a073 | 1422 | return spi_controller_suspend(rspi->ctlr); |
c1ca59c2 GU |
1423 | } |
1424 | ||
1425 | static int rspi_resume(struct device *dev) | |
1426 | { | |
be0bf62e | 1427 | struct rspi_data *rspi = dev_get_drvdata(dev); |
c1ca59c2 | 1428 | |
9428a073 | 1429 | return spi_controller_resume(rspi->ctlr); |
c1ca59c2 GU |
1430 | } |
1431 | ||
1432 | static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume); | |
1433 | #define DEV_PM_OPS &rspi_pm_ops | |
1434 | #else | |
1435 | #define DEV_PM_OPS NULL | |
1436 | #endif /* CONFIG_PM_SLEEP */ | |
1437 | ||
0b2182dd SY |
1438 | static struct platform_driver rspi_driver = { |
1439 | .probe = rspi_probe, | |
72ec0e8f | 1440 | .remove_new = rspi_remove, |
5ce0ba88 | 1441 | .id_table = spi_driver_ids, |
0b2182dd | 1442 | .driver = { |
5ce0ba88 | 1443 | .name = "renesas_spi", |
c1ca59c2 | 1444 | .pm = DEV_PM_OPS, |
426ef76d | 1445 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1446 | }, |
1447 | }; | |
1448 | module_platform_driver(rspi_driver); | |
1449 | ||
1450 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1451 | MODULE_LICENSE("GPL v2"); | |
1452 | MODULE_AUTHOR("Yoshihiro Shimoda"); |