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spi: rockchip: directly use direction constants
[linux-2.6-block.git] / drivers / spi / spi-rockchip.c
CommitLineData
64e36824 1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5dcc44ed 3 * Author: Addy Ke <addy.ke@rock-chips.com>
64e36824 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
64e36824 16#include <linux/clk.h>
ec5c5d8a
SL		 17#include <linux/dmaengine.h>
18#include <linux/module.h>
19#include <linux/of.h>
23e291c2 20#include <linux/pinctrl/consumer.h>
64e36824 21#include <linux/platform_device.h>
64e36824 22#include <linux/spi/spi.h>
64e36824 23#include <linux/pm_runtime.h>
ec5c5d8a 24#include <linux/scatterlist.h>
64e36824 25
26#define DRIVER_NAME "rockchip-spi"
27
aa099382
JC		 28#define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
29 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
30#define ROCKCHIP_SPI_SET_BITS(reg, bits) \
31 writel_relaxed(readl_relaxed(reg) | (bits), reg)
32
64e36824 33/* SPI register offsets */
34#define ROCKCHIP_SPI_CTRLR0 0x0000
35#define ROCKCHIP_SPI_CTRLR1 0x0004
36#define ROCKCHIP_SPI_SSIENR 0x0008
37#define ROCKCHIP_SPI_SER 0x000c
38#define ROCKCHIP_SPI_BAUDR 0x0010
39#define ROCKCHIP_SPI_TXFTLR 0x0014
40#define ROCKCHIP_SPI_RXFTLR 0x0018
41#define ROCKCHIP_SPI_TXFLR 0x001c
42#define ROCKCHIP_SPI_RXFLR 0x0020
43#define ROCKCHIP_SPI_SR 0x0024
44#define ROCKCHIP_SPI_IPR 0x0028
45#define ROCKCHIP_SPI_IMR 0x002c
46#define ROCKCHIP_SPI_ISR 0x0030
47#define ROCKCHIP_SPI_RISR 0x0034
48#define ROCKCHIP_SPI_ICR 0x0038
49#define ROCKCHIP_SPI_DMACR 0x003c
50#define ROCKCHIP_SPI_DMATDLR 0x0040
51#define ROCKCHIP_SPI_DMARDLR 0x0044
52#define ROCKCHIP_SPI_TXDR 0x0400
53#define ROCKCHIP_SPI_RXDR 0x0800
54
55/* Bit fields in CTRLR0 */
56#define CR0_DFS_OFFSET 0
57
58#define CR0_CFS_OFFSET 2
59
60#define CR0_SCPH_OFFSET 6
61
62#define CR0_SCPOL_OFFSET 7
63
64#define CR0_CSM_OFFSET 8
65#define CR0_CSM_KEEP 0x0
66/* ss_n be high for half sclk_out cycles */
67#define CR0_CSM_HALF 0X1
68/* ss_n be high for one sclk_out cycle */
69#define CR0_CSM_ONE 0x2
70
71/* ss_n to sclk_out delay */
72#define CR0_SSD_OFFSET 10
73/*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77#define CR0_SSD_HALF 0x0
78/*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82#define CR0_SSD_ONE 0x1
83
84#define CR0_EM_OFFSET 11
85#define CR0_EM_LITTLE 0x0
86#define CR0_EM_BIG 0x1
87
88#define CR0_FBM_OFFSET 12
89#define CR0_FBM_MSB 0x0
90#define CR0_FBM_LSB 0x1
91
92#define CR0_BHT_OFFSET 13
93#define CR0_BHT_16BIT 0x0
94#define CR0_BHT_8BIT 0x1
95
96#define CR0_RSD_OFFSET 14
97
98#define CR0_FRF_OFFSET 16
99#define CR0_FRF_SPI 0x0
100#define CR0_FRF_SSP 0x1
101#define CR0_FRF_MICROWIRE 0x2
102
103#define CR0_XFM_OFFSET 18
104#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105#define CR0_XFM_TR 0x0
106#define CR0_XFM_TO 0x1
107#define CR0_XFM_RO 0x2
108
109#define CR0_OPM_OFFSET 20
110#define CR0_OPM_MASTER 0x0
111#define CR0_OPM_SLAVE 0x1
112
113#define CR0_MTM_OFFSET 0x21
114
115/* Bit fields in SER, 2bit */
116#define SER_MASK 0x3
117
118/* Bit fields in SR, 5bit */
119#define SR_MASK 0x1f
120#define SR_BUSY (1 << 0)
121#define SR_TF_FULL (1 << 1)
122#define SR_TF_EMPTY (1 << 2)
123#define SR_RF_EMPTY (1 << 3)
124#define SR_RF_FULL (1 << 4)
125
126/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127#define INT_MASK 0x1f
128#define INT_TF_EMPTY (1 << 0)
129#define INT_TF_OVERFLOW (1 << 1)
130#define INT_RF_UNDERFLOW (1 << 2)
131#define INT_RF_OVERFLOW (1 << 3)
132#define INT_RF_FULL (1 << 4)
133
134/* Bit fields in ICR, 4bit */
135#define ICR_MASK 0x0f
136#define ICR_ALL (1 << 0)
137#define ICR_RF_UNDERFLOW (1 << 1)
138#define ICR_RF_OVERFLOW (1 << 2)
139#define ICR_TF_OVERFLOW (1 << 3)
140
141/* Bit fields in DMACR */
142#define RF_DMA_EN (1 << 0)
143#define TF_DMA_EN (1 << 1)
144
145#define RXBUSY (1 << 0)
146#define TXBUSY (1 << 1)
147
f9cfd522
AK		 148/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149#define MAX_SCLK_OUT 50000000
150
5185a81c
BN		 151/*
152 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
153 * the controller seems to hang when given 0x10000, so stick with this for now.
154 */
155#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
156
aa099382
JC		 157#define ROCKCHIP_SPI_MAX_CS_NUM 2
158
64e36824 159enum rockchip_ssi_type {
160 SSI_MOTO_SPI = 0,
161 SSI_TI_SSP,
162 SSI_NS_MICROWIRE,
163};
164
165struct rockchip_spi_dma_data {
166 struct dma_chan *ch;
64e36824 167 dma_addr_t addr;
168};
169
170struct rockchip_spi {
171 struct device *dev;
172 struct spi_master *master;
173
174 struct clk *spiclk;
175 struct clk *apb_pclk;
176
177 void __iomem *regs;
178 /*depth of the FIFO buffer */
179 u32 fifo_len;
180 /* max bus freq supported */
181 u32 max_freq;
182 /* supported slave numbers */
183 enum rockchip_ssi_type type;
184
185 u16 mode;
186 u8 tmode;
187 u8 bpw;
188 u8 n_bytes;
108b5c8b 189 u32 rsd_nsecs;
64e36824 190 unsigned len;
191 u32 speed;
192
193 const void *tx;
194 const void *tx_end;
195 void *rx;
196 void *rx_end;
197
198 u32 state;
5dcc44ed 199 /* protect state */
64e36824 200 spinlock_t lock;
201
aa099382
JC		 202 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
203
f340b920 204 bool use_dma;
64e36824 205 struct sg_table tx_sg;
206 struct sg_table rx_sg;
207 struct rockchip_spi_dma_data dma_rx;
208 struct rockchip_spi_dma_data dma_tx;
209};
210
211static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
212{
213 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
214}
215
216static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
217{
218 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
219}
220
221static inline void flush_fifo(struct rockchip_spi *rs)
222{
223 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
224 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
225}
226
2df08e78
AK		 227static inline void wait_for_idle(struct rockchip_spi *rs)
228{
229 unsigned long timeout = jiffies + msecs_to_jiffies(5);
230
231 do {
232 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
233 return;
64bc0110 234 } while (!time_after(jiffies, timeout));
2df08e78
AK		 235
236 dev_warn(rs->dev, "spi controller is in busy state!\n");
237}
238
64e36824 239static u32 get_fifo_len(struct rockchip_spi *rs)
240{
241 u32 fifo;
242
243 for (fifo = 2; fifo < 32; fifo++) {
244 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
245 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
246 break;
247 }
248
249 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
250
251 return (fifo == 31) ? 0 : fifo;
252}
253
254static inline u32 tx_max(struct rockchip_spi *rs)
255{
256 u32 tx_left, tx_room;
257
258 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
259 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
260
261 return min(tx_left, tx_room);
262}
263
264static inline u32 rx_max(struct rockchip_spi *rs)
265{
266 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
267 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
268
269 return min(rx_left, rx_room);
270}
271
272static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
273{
b920cc31
HH		 274 struct spi_master *master = spi->master;
275 struct rockchip_spi *rs = spi_master_get_devdata(master);
aa099382 276 bool cs_asserted = !enable;
b920cc31 277
aa099382
JC		 278 /* Return immediately for no-op */
279 if (cs_asserted == rs->cs_asserted[spi->chip_select])
280 return;
64e36824 281
aa099382
JC		 282 if (cs_asserted) {
283 /* Keep things powered as long as CS is asserted */
284 pm_runtime_get_sync(rs->dev);
64e36824 285
aa099382
JC		 286 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
287 BIT(spi->chip_select));
288 } else {
289 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
290 BIT(spi->chip_select));
64e36824 291
aa099382
JC		 292 /* Drop reference from when we first asserted CS */
293 pm_runtime_put(rs->dev);
294 }
b920cc31 295
aa099382 296 rs->cs_asserted[spi->chip_select] = cs_asserted;
64e36824 297}
298
299static int rockchip_spi_prepare_message(struct spi_master *master,
5dcc44ed 300 struct spi_message *msg)
64e36824 301{
302 struct rockchip_spi *rs = spi_master_get_devdata(master);
303 struct spi_device *spi = msg->spi;
304
64e36824 305 rs->mode = spi->mode;
306
307 return 0;
308}
309
2291793c
AS		 310static void rockchip_spi_handle_err(struct spi_master *master,
311 struct spi_message *msg)
64e36824 312{
313 unsigned long flags;
314 struct rockchip_spi *rs = spi_master_get_devdata(master);
315
316 spin_lock_irqsave(&rs->lock, flags);
317
5dcc44ed
AK		 318 /*
319 * For DMA mode, we need terminate DMA channel and flush
320 * fifo for the next transfer if DMA thansfer timeout.
2291793c
AS		 321 * handle_err() was called by core if transfer failed.
322 * Maybe it is reasonable for error handling here.
5dcc44ed 323 */
64e36824 324 if (rs->use_dma) {
325 if (rs->state & RXBUSY) {
557b7ea3 326 dmaengine_terminate_async(rs->dma_rx.ch);
64e36824 327 flush_fifo(rs);
328 }
329
330 if (rs->state & TXBUSY)
557b7ea3 331 dmaengine_terminate_async(rs->dma_tx.ch);
64e36824 332 }
333
334 spin_unlock_irqrestore(&rs->lock, flags);
2291793c
AS		 335}
336
337static int rockchip_spi_unprepare_message(struct spi_master *master,
338 struct spi_message *msg)
339{
340 struct rockchip_spi *rs = spi_master_get_devdata(master);
64e36824 341
c28be31b
AK		 342 spi_enable_chip(rs, 0);
343
64e36824 344 return 0;
345}
346
347static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
348{
349 u32 max = tx_max(rs);
350 u32 txw = 0;
351
352 while (max--) {
353 if (rs->n_bytes == 1)
354 txw = *(u8 *)(rs->tx);
355 else
356 txw = *(u16 *)(rs->tx);
357
358 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
359 rs->tx += rs->n_bytes;
360 }
361}
362
363static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
364{
365 u32 max = rx_max(rs);
366 u32 rxw;
367
368 while (max--) {
369 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
370 if (rs->n_bytes == 1)
371 *(u8 *)(rs->rx) = (u8)rxw;
372 else
373 *(u16 *)(rs->rx) = (u16)rxw;
374 rs->rx += rs->n_bytes;
5dcc44ed 375 }
64e36824 376}
377
378static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
379{
380 int remain = 0;
381
382 do {
383 if (rs->tx) {
384 remain = rs->tx_end - rs->tx;
385 rockchip_spi_pio_writer(rs);
386 }
387
388 if (rs->rx) {
389 remain = rs->rx_end - rs->rx;
390 rockchip_spi_pio_reader(rs);
391 }
392
393 cpu_relax();
394 } while (remain);
395
2df08e78
AK		 396 /* If tx, wait until the FIFO data completely. */
397 if (rs->tx)
398 wait_for_idle(rs);
399
c28be31b
AK		 400 spi_enable_chip(rs, 0);
401
64e36824 402 return 0;
403}
404
405static void rockchip_spi_dma_rxcb(void *data)
406{
407 unsigned long flags;
408 struct rockchip_spi *rs = data;
409
410 spin_lock_irqsave(&rs->lock, flags);
411
412 rs->state &= ~RXBUSY;
c28be31b
AK		 413 if (!(rs->state & TXBUSY)) {
414 spi_enable_chip(rs, 0);
64e36824 415 spi_finalize_current_transfer(rs->master);
c28be31b 416 }
64e36824 417
418 spin_unlock_irqrestore(&rs->lock, flags);
419}
420
421static void rockchip_spi_dma_txcb(void *data)
422{
423 unsigned long flags;
424 struct rockchip_spi *rs = data;
425
2df08e78
AK		 426 /* Wait until the FIFO data completely. */
427 wait_for_idle(rs);
428
64e36824 429 spin_lock_irqsave(&rs->lock, flags);
430
431 rs->state &= ~TXBUSY;
2c2bc748
AK		 432 if (!(rs->state & RXBUSY)) {
433 spi_enable_chip(rs, 0);
64e36824 434 spi_finalize_current_transfer(rs->master);
2c2bc748 435 }
64e36824 436
437 spin_unlock_irqrestore(&rs->lock, flags);
438}
439
ea984911 440static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
64e36824 441{
442 unsigned long flags;
443 struct dma_slave_config rxconf, txconf;
444 struct dma_async_tx_descriptor *rxdesc, *txdesc;
445
446 spin_lock_irqsave(&rs->lock, flags);
447 rs->state &= ~RXBUSY;
448 rs->state &= ~TXBUSY;
449 spin_unlock_irqrestore(&rs->lock, flags);
450
97cf5669 451 rxdesc = NULL;
64e36824 452 if (rs->rx) {
d9071b7e 453 rxconf.direction = DMA_DEV_TO_MEM;
64e36824 454 rxconf.src_addr = rs->dma_rx.addr;
455 rxconf.src_addr_width = rs->n_bytes;
dcfc861d 456 rxconf.src_maxburst = 1;
64e36824 457 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
458
5dcc44ed
AK		 459 rxdesc = dmaengine_prep_slave_sg(
460 rs->dma_rx.ch,
64e36824 461 rs->rx_sg.sgl, rs->rx_sg.nents,
d9071b7e 462 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
ea984911
SL		 463 if (!rxdesc)
464 return -EINVAL;
64e36824 465
466 rxdesc->callback = rockchip_spi_dma_rxcb;
467 rxdesc->callback_param = rs;
468 }
469
97cf5669 470 txdesc = NULL;
64e36824 471 if (rs->tx) {
d9071b7e 472 txconf.direction = DMA_MEM_TO_DEV;
64e36824 473 txconf.dst_addr = rs->dma_tx.addr;
474 txconf.dst_addr_width = rs->n_bytes;
dcfc861d 475 txconf.dst_maxburst = rs->fifo_len / 2;
64e36824 476 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
477
5dcc44ed
AK		 478 txdesc = dmaengine_prep_slave_sg(
479 rs->dma_tx.ch,
64e36824 480 rs->tx_sg.sgl, rs->tx_sg.nents,
d9071b7e 481 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
ea984911
SL		 482 if (!txdesc) {
483 if (rxdesc)
484 dmaengine_terminate_sync(rs->dma_rx.ch);
485 return -EINVAL;
486 }
64e36824 487
488 txdesc->callback = rockchip_spi_dma_txcb;
489 txdesc->callback_param = rs;
490 }
491
492 /* rx must be started before tx due to spi instinct */
97cf5669 493 if (rxdesc) {
64e36824 494 spin_lock_irqsave(&rs->lock, flags);
495 rs->state |= RXBUSY;
496 spin_unlock_irqrestore(&rs->lock, flags);
497 dmaengine_submit(rxdesc);
498 dma_async_issue_pending(rs->dma_rx.ch);
499 }
500
97cf5669 501 if (txdesc) {
64e36824 502 spin_lock_irqsave(&rs->lock, flags);
503 rs->state |= TXBUSY;
504 spin_unlock_irqrestore(&rs->lock, flags);
505 dmaengine_submit(txdesc);
506 dma_async_issue_pending(rs->dma_tx.ch);
507 }
ea984911
SL		 508
509 return 0;
64e36824 510}
511
512static void rockchip_spi_config(struct rockchip_spi *rs)
513{
514 u32 div = 0;
515 u32 dmacr = 0;
76b17e6e 516 int rsd = 0;
64e36824 517
518 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
0277e01a
AK		 519 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
520 | (CR0_EM_BIG << CR0_EM_OFFSET);
64e36824 521
522 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
523 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
524 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
525 cr0 |= (rs->type << CR0_FRF_OFFSET);
526
527 if (rs->use_dma) {
528 if (rs->tx)
529 dmacr |= TF_DMA_EN;
530 if (rs->rx)
531 dmacr |= RF_DMA_EN;
532 }
533
f9cfd522
AK		 534 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
535 rs->speed = MAX_SCLK_OUT;
536
bb51537a 537 /* the minimum divisor is 2 */
f9cfd522
AK		 538 if (rs->max_freq < 2 * rs->speed) {
539 clk_set_rate(rs->spiclk, 2 * rs->speed);
540 rs->max_freq = clk_get_rate(rs->spiclk);
541 }
542
64e36824 543 /* div doesn't support odd number */
754ec43c 544 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
64e36824 545 div = (div + 1) & 0xfffe;
546
76b17e6e
JW		 547 /* Rx sample delay is expressed in parent clock cycles (max 3) */
548 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
549 1000000000 >> 8);
550 if (!rsd && rs->rsd_nsecs) {
551 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
552 rs->max_freq, rs->rsd_nsecs);
553 } else if (rsd > 3) {
554 rsd = 3;
555 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
556 rs->max_freq, rs->rsd_nsecs,
557 rsd * 1000000000U / rs->max_freq);
558 }
559 cr0 |= rsd << CR0_RSD_OFFSET;
560
64e36824 561 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
562
04b37d2d
HH		 563 if (rs->n_bytes == 1)
564 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
565 else if (rs->n_bytes == 2)
566 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
567 else
568 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
569
64e36824 570 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
571 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
572
dcfc861d 573 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
64e36824 574 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
575 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
576
577 spi_set_clk(rs, div);
578
5dcc44ed 579 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
64e36824 580}
581
5185a81c
BN		 582static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
583{
584 return ROCKCHIP_SPI_MAX_TRANLEN;
585}
586
5dcc44ed
AK		 587static int rockchip_spi_transfer_one(
588 struct spi_master *master,
64e36824 589 struct spi_device *spi,
590 struct spi_transfer *xfer)
591{
4dc0dd83 592 int ret = 0;
64e36824 593 struct rockchip_spi *rs = spi_master_get_devdata(master);
594
62946172
DA		 595 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
596 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
64e36824 597
598 if (!xfer->tx_buf && !xfer->rx_buf) {
599 dev_err(rs->dev, "No buffer for transfer\n");
600 return -EINVAL;
601 }
602
5185a81c
BN		 603 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
604 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
605 return -EINVAL;
606 }
607
64e36824 608 rs->speed = xfer->speed_hz;
609 rs->bpw = xfer->bits_per_word;
610 rs->n_bytes = rs->bpw >> 3;
611
612 rs->tx = xfer->tx_buf;
613 rs->tx_end = rs->tx + xfer->len;
614 rs->rx = xfer->rx_buf;
615 rs->rx_end = rs->rx + xfer->len;
616 rs->len = xfer->len;
617
618 rs->tx_sg = xfer->tx_sg;
619 rs->rx_sg = xfer->rx_sg;
620
64e36824 621 if (rs->tx && rs->rx)
622 rs->tmode = CR0_XFM_TR;
623 else if (rs->tx)
624 rs->tmode = CR0_XFM_TO;
625 else if (rs->rx)
626 rs->tmode = CR0_XFM_RO;
627
a24e70c0 628 /* we need prepare dma before spi was enabled */
c28be31b 629 if (master->can_dma && master->can_dma(master, spi, xfer))
f340b920 630 rs->use_dma = true;
c28be31b 631 else
f340b920 632 rs->use_dma = false;
64e36824 633
634 rockchip_spi_config(rs);
635
c28be31b
AK		 636 if (rs->use_dma) {
637 if (rs->tmode == CR0_XFM_RO) {
638 /* rx: dma must be prepared first */
ea984911 639 ret = rockchip_spi_prepare_dma(rs);
c28be31b
AK		 640 spi_enable_chip(rs, 1);
641 } else {
642 /* tx or tr: spi must be enabled first */
643 spi_enable_chip(rs, 1);
ea984911 644 ret = rockchip_spi_prepare_dma(rs);
c28be31b 645 }
4dc0dd83
TV		 646 /* successful DMA prepare means the transfer is in progress */
647 ret = ret ? ret : 1;
c28be31b
AK		 648 } else {
649 spi_enable_chip(rs, 1);
64e36824 650 ret = rockchip_spi_pio_transfer(rs);
c28be31b 651 }
64e36824 652
653 return ret;
654}
655
656static bool rockchip_spi_can_dma(struct spi_master *master,
5dcc44ed
AK		 657 struct spi_device *spi,
658 struct spi_transfer *xfer)
64e36824 659{
660 struct rockchip_spi *rs = spi_master_get_devdata(master);
661
662 return (xfer->len > rs->fifo_len);
663}
664
665static int rockchip_spi_probe(struct platform_device *pdev)
666{
43de979d 667 int ret;
64e36824 668 struct rockchip_spi *rs;
669 struct spi_master *master;
670 struct resource *mem;
76b17e6e 671 u32 rsd_nsecs;
64e36824 672
673 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
5dcc44ed 674 if (!master)
64e36824 675 return -ENOMEM;
5dcc44ed 676
64e36824 677 platform_set_drvdata(pdev, master);
678
679 rs = spi_master_get_devdata(master);
64e36824 680
681 /* Get basic io resource and map it */
682 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
683 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
684 if (IS_ERR(rs->regs)) {
64e36824 685 ret = PTR_ERR(rs->regs);
c351587e 686 goto err_put_master;
64e36824 687 }
688
689 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
690 if (IS_ERR(rs->apb_pclk)) {
691 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
692 ret = PTR_ERR(rs->apb_pclk);
c351587e 693 goto err_put_master;
64e36824 694 }
695
696 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
697 if (IS_ERR(rs->spiclk)) {
698 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
699 ret = PTR_ERR(rs->spiclk);
c351587e 700 goto err_put_master;
64e36824 701 }
702
703 ret = clk_prepare_enable(rs->apb_pclk);
43de979d 704 if (ret < 0) {
64e36824 705 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
c351587e 706 goto err_put_master;
64e36824 707 }
708
709 ret = clk_prepare_enable(rs->spiclk);
43de979d 710 if (ret < 0) {
64e36824 711 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
c351587e 712 goto err_disable_apbclk;
64e36824 713 }
714
715 spi_enable_chip(rs, 0);
716
717 rs->type = SSI_MOTO_SPI;
718 rs->master = master;
719 rs->dev = &pdev->dev;
720 rs->max_freq = clk_get_rate(rs->spiclk);
721
76b17e6e
JW		 722 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
723 &rsd_nsecs))
724 rs->rsd_nsecs = rsd_nsecs;
725
64e36824 726 rs->fifo_len = get_fifo_len(rs);
727 if (!rs->fifo_len) {
728 dev_err(&pdev->dev, "Failed to get fifo length\n");
db7e8d90 729 ret = -EINVAL;
c351587e 730 goto err_disable_spiclk;
64e36824 731 }
732
733 spin_lock_init(&rs->lock);
734
735 pm_runtime_set_active(&pdev->dev);
736 pm_runtime_enable(&pdev->dev);
737
738 master->auto_runtime_pm = true;
739 master->bus_num = pdev->id;
ee780997 740 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
aa099382 741 master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
64e36824 742 master->dev.of_node = pdev->dev.of_node;
743 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
744
745 master->set_cs = rockchip_spi_set_cs;
746 master->prepare_message = rockchip_spi_prepare_message;
747 master->unprepare_message = rockchip_spi_unprepare_message;
748 master->transfer_one = rockchip_spi_transfer_one;
5185a81c 749 master->max_transfer_size = rockchip_spi_max_transfer_size;
2291793c 750 master->handle_err = rockchip_spi_handle_err;
c863795c 751 master->flags = SPI_MASTER_GPIO_SS;
64e36824 752
e4c0e06f
SL		 753 rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
754 if (IS_ERR(rs->dma_tx.ch)) {
61cadcf4
SL		 755 /* Check tx to see if we need defer probing driver */
756 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
757 ret = -EPROBE_DEFER;
c351587e 758 goto err_disable_pm_runtime;
61cadcf4 759 }
64e36824 760 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
e4c0e06f 761 rs->dma_tx.ch = NULL;
61cadcf4 762 }
64e36824 763
e4c0e06f
SL		 764 rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
765 if (IS_ERR(rs->dma_rx.ch)) {
766 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
e4c0e06f 767 ret = -EPROBE_DEFER;
5de7ed0c 768 goto err_free_dma_tx;
64e36824 769 }
770 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
e4c0e06f 771 rs->dma_rx.ch = NULL;
64e36824 772 }
773
774 if (rs->dma_tx.ch && rs->dma_rx.ch) {
775 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
776 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
64e36824 777
778 master->can_dma = rockchip_spi_can_dma;
779 master->dma_tx = rs->dma_tx.ch;
780 master->dma_rx = rs->dma_rx.ch;
781 }
782
783 ret = devm_spi_register_master(&pdev->dev, master);
43de979d 784 if (ret < 0) {
64e36824 785 dev_err(&pdev->dev, "Failed to register master\n");
c351587e 786 goto err_free_dma_rx;
64e36824 787 }
788
64e36824 789 return 0;
790
c351587e 791err_free_dma_rx:
64e36824 792 if (rs->dma_rx.ch)
793 dma_release_channel(rs->dma_rx.ch);
5de7ed0c
DC		 794err_free_dma_tx:
795 if (rs->dma_tx.ch)
796 dma_release_channel(rs->dma_tx.ch);
c351587e
JC		 797err_disable_pm_runtime:
798 pm_runtime_disable(&pdev->dev);
799err_disable_spiclk:
64e36824 800 clk_disable_unprepare(rs->spiclk);
c351587e 801err_disable_apbclk:
64e36824 802 clk_disable_unprepare(rs->apb_pclk);
c351587e 803err_put_master:
64e36824 804 spi_master_put(master);
805
806 return ret;
807}
808
809static int rockchip_spi_remove(struct platform_device *pdev)
810{
811 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
812 struct rockchip_spi *rs = spi_master_get_devdata(master);
813
6a06e895 814 pm_runtime_get_sync(&pdev->dev);
64e36824 815
816 clk_disable_unprepare(rs->spiclk);
817 clk_disable_unprepare(rs->apb_pclk);
818
6a06e895
JC		 819 pm_runtime_put_noidle(&pdev->dev);
820 pm_runtime_disable(&pdev->dev);
821 pm_runtime_set_suspended(&pdev->dev);
822
64e36824 823 if (rs->dma_tx.ch)
824 dma_release_channel(rs->dma_tx.ch);
825 if (rs->dma_rx.ch)
826 dma_release_channel(rs->dma_rx.ch);
827
844c9f47
SL		 828 spi_master_put(master);
829
64e36824 830 return 0;
831}
832
833#ifdef CONFIG_PM_SLEEP
834static int rockchip_spi_suspend(struct device *dev)
835{
43de979d 836 int ret;
64e36824 837 struct spi_master *master = dev_get_drvdata(dev);
838 struct rockchip_spi *rs = spi_master_get_devdata(master);
839
840 ret = spi_master_suspend(rs->master);
43de979d 841 if (ret < 0)
64e36824 842 return ret;
843
d38c4ae1
JC		 844 ret = pm_runtime_force_suspend(dev);
845 if (ret < 0)
846 return ret;
64e36824 847
23e291c2
BN		 848 pinctrl_pm_select_sleep_state(dev);
849
43de979d 850 return 0;
64e36824 851}
852
853static int rockchip_spi_resume(struct device *dev)
854{
43de979d 855 int ret;
64e36824 856 struct spi_master *master = dev_get_drvdata(dev);
857 struct rockchip_spi *rs = spi_master_get_devdata(master);
858
23e291c2
BN		 859 pinctrl_pm_select_default_state(dev);
860
d38c4ae1
JC		 861 ret = pm_runtime_force_resume(dev);
862 if (ret < 0)
863 return ret;
64e36824 864
865 ret = spi_master_resume(rs->master);
866 if (ret < 0) {
867 clk_disable_unprepare(rs->spiclk);
868 clk_disable_unprepare(rs->apb_pclk);
869 }
870
43de979d 871 return 0;
64e36824 872}
873#endif /* CONFIG_PM_SLEEP */
874
ec833050 875#ifdef CONFIG_PM
64e36824 876static int rockchip_spi_runtime_suspend(struct device *dev)
877{
878 struct spi_master *master = dev_get_drvdata(dev);
879 struct rockchip_spi *rs = spi_master_get_devdata(master);
880
881 clk_disable_unprepare(rs->spiclk);
882 clk_disable_unprepare(rs->apb_pclk);
883
884 return 0;
885}
886
887static int rockchip_spi_runtime_resume(struct device *dev)
888{
889 int ret;
890 struct spi_master *master = dev_get_drvdata(dev);
891 struct rockchip_spi *rs = spi_master_get_devdata(master);
892
893 ret = clk_prepare_enable(rs->apb_pclk);
43de979d 894 if (ret < 0)
64e36824 895 return ret;
896
897 ret = clk_prepare_enable(rs->spiclk);
43de979d 898 if (ret < 0)
64e36824 899 clk_disable_unprepare(rs->apb_pclk);
900
43de979d 901 return 0;
64e36824 902}
ec833050 903#endif /* CONFIG_PM */
64e36824 904
905static const struct dev_pm_ops rockchip_spi_pm = {
906 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
907 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
908 rockchip_spi_runtime_resume, NULL)
909};
910
911static const struct of_device_id rockchip_spi_dt_match[] = {
6b860e69 912 { .compatible = "rockchip,rv1108-spi", },
aa29ea3d 913 { .compatible = "rockchip,rk3036-spi", },
64e36824 914 { .compatible = "rockchip,rk3066-spi", },
b839b785 915 { .compatible = "rockchip,rk3188-spi", },
aa29ea3d 916 { .compatible = "rockchip,rk3228-spi", },
b839b785 917 { .compatible = "rockchip,rk3288-spi", },
aa29ea3d 918 { .compatible = "rockchip,rk3368-spi", },
9b7a5622 919 { .compatible = "rockchip,rk3399-spi", },
64e36824 920 { },
921};
922MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
923
924static struct platform_driver rockchip_spi_driver = {
925 .driver = {
926 .name = DRIVER_NAME,
64e36824 927 .pm = &rockchip_spi_pm,
928 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
929 },
930 .probe = rockchip_spi_probe,
931 .remove = rockchip_spi_remove,
932};
933
934module_platform_driver(rockchip_spi_driver);
935
5dcc44ed 936MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
64e36824 937MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
938MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)