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64e36824 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
64e36824 | 16 | #include <linux/clk.h> |
ec5c5d8a SL |
17 | #include <linux/dmaengine.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
23e291c2 | 20 | #include <linux/pinctrl/consumer.h> |
64e36824 | 21 | #include <linux/platform_device.h> |
64e36824 | 22 | #include <linux/spi/spi.h> |
64e36824 | 23 | #include <linux/pm_runtime.h> |
ec5c5d8a | 24 | #include <linux/scatterlist.h> |
64e36824 | 25 | |
26 | #define DRIVER_NAME "rockchip-spi" | |
27 | ||
28 | /* SPI register offsets */ | |
29 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
30 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
31 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
32 | #define ROCKCHIP_SPI_SER 0x000c | |
33 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
34 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
35 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
36 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
37 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
38 | #define ROCKCHIP_SPI_SR 0x0024 | |
39 | #define ROCKCHIP_SPI_IPR 0x0028 | |
40 | #define ROCKCHIP_SPI_IMR 0x002c | |
41 | #define ROCKCHIP_SPI_ISR 0x0030 | |
42 | #define ROCKCHIP_SPI_RISR 0x0034 | |
43 | #define ROCKCHIP_SPI_ICR 0x0038 | |
44 | #define ROCKCHIP_SPI_DMACR 0x003c | |
45 | #define ROCKCHIP_SPI_DMATDLR 0x0040 | |
46 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
47 | #define ROCKCHIP_SPI_TXDR 0x0400 | |
48 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
49 | ||
50 | /* Bit fields in CTRLR0 */ | |
51 | #define CR0_DFS_OFFSET 0 | |
52 | ||
53 | #define CR0_CFS_OFFSET 2 | |
54 | ||
55 | #define CR0_SCPH_OFFSET 6 | |
56 | ||
57 | #define CR0_SCPOL_OFFSET 7 | |
58 | ||
59 | #define CR0_CSM_OFFSET 8 | |
60 | #define CR0_CSM_KEEP 0x0 | |
61 | /* ss_n be high for half sclk_out cycles */ | |
62 | #define CR0_CSM_HALF 0X1 | |
63 | /* ss_n be high for one sclk_out cycle */ | |
64 | #define CR0_CSM_ONE 0x2 | |
65 | ||
66 | /* ss_n to sclk_out delay */ | |
67 | #define CR0_SSD_OFFSET 10 | |
68 | /* | |
69 | * The period between ss_n active and | |
70 | * sclk_out active is half sclk_out cycles | |
71 | */ | |
72 | #define CR0_SSD_HALF 0x0 | |
73 | /* | |
74 | * The period between ss_n active and | |
75 | * sclk_out active is one sclk_out cycle | |
76 | */ | |
77 | #define CR0_SSD_ONE 0x1 | |
78 | ||
79 | #define CR0_EM_OFFSET 11 | |
80 | #define CR0_EM_LITTLE 0x0 | |
81 | #define CR0_EM_BIG 0x1 | |
82 | ||
83 | #define CR0_FBM_OFFSET 12 | |
84 | #define CR0_FBM_MSB 0x0 | |
85 | #define CR0_FBM_LSB 0x1 | |
86 | ||
87 | #define CR0_BHT_OFFSET 13 | |
88 | #define CR0_BHT_16BIT 0x0 | |
89 | #define CR0_BHT_8BIT 0x1 | |
90 | ||
91 | #define CR0_RSD_OFFSET 14 | |
92 | ||
93 | #define CR0_FRF_OFFSET 16 | |
94 | #define CR0_FRF_SPI 0x0 | |
95 | #define CR0_FRF_SSP 0x1 | |
96 | #define CR0_FRF_MICROWIRE 0x2 | |
97 | ||
98 | #define CR0_XFM_OFFSET 18 | |
99 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
100 | #define CR0_XFM_TR 0x0 | |
101 | #define CR0_XFM_TO 0x1 | |
102 | #define CR0_XFM_RO 0x2 | |
103 | ||
104 | #define CR0_OPM_OFFSET 20 | |
105 | #define CR0_OPM_MASTER 0x0 | |
106 | #define CR0_OPM_SLAVE 0x1 | |
107 | ||
108 | #define CR0_MTM_OFFSET 0x21 | |
109 | ||
110 | /* Bit fields in SER, 2bit */ | |
111 | #define SER_MASK 0x3 | |
112 | ||
113 | /* Bit fields in SR, 5bit */ | |
114 | #define SR_MASK 0x1f | |
115 | #define SR_BUSY (1 << 0) | |
116 | #define SR_TF_FULL (1 << 1) | |
117 | #define SR_TF_EMPTY (1 << 2) | |
118 | #define SR_RF_EMPTY (1 << 3) | |
119 | #define SR_RF_FULL (1 << 4) | |
120 | ||
121 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
122 | #define INT_MASK 0x1f | |
123 | #define INT_TF_EMPTY (1 << 0) | |
124 | #define INT_TF_OVERFLOW (1 << 1) | |
125 | #define INT_RF_UNDERFLOW (1 << 2) | |
126 | #define INT_RF_OVERFLOW (1 << 3) | |
127 | #define INT_RF_FULL (1 << 4) | |
128 | ||
129 | /* Bit fields in ICR, 4bit */ | |
130 | #define ICR_MASK 0x0f | |
131 | #define ICR_ALL (1 << 0) | |
132 | #define ICR_RF_UNDERFLOW (1 << 1) | |
133 | #define ICR_RF_OVERFLOW (1 << 2) | |
134 | #define ICR_TF_OVERFLOW (1 << 3) | |
135 | ||
136 | /* Bit fields in DMACR */ | |
137 | #define RF_DMA_EN (1 << 0) | |
138 | #define TF_DMA_EN (1 << 1) | |
139 | ||
140 | #define RXBUSY (1 << 0) | |
141 | #define TXBUSY (1 << 1) | |
142 | ||
f9cfd522 AK |
143 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
144 | #define MAX_SCLK_OUT 50000000 | |
145 | ||
5185a81c BN |
146 | /* |
147 | * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, | |
148 | * the controller seems to hang when given 0x10000, so stick with this for now. | |
149 | */ | |
150 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff | |
151 | ||
64e36824 | 152 | enum rockchip_ssi_type { |
153 | SSI_MOTO_SPI = 0, | |
154 | SSI_TI_SSP, | |
155 | SSI_NS_MICROWIRE, | |
156 | }; | |
157 | ||
158 | struct rockchip_spi_dma_data { | |
159 | struct dma_chan *ch; | |
160 | enum dma_transfer_direction direction; | |
161 | dma_addr_t addr; | |
162 | }; | |
163 | ||
164 | struct rockchip_spi { | |
165 | struct device *dev; | |
166 | struct spi_master *master; | |
167 | ||
168 | struct clk *spiclk; | |
169 | struct clk *apb_pclk; | |
170 | ||
171 | void __iomem *regs; | |
172 | /*depth of the FIFO buffer */ | |
173 | u32 fifo_len; | |
174 | /* max bus freq supported */ | |
175 | u32 max_freq; | |
176 | /* supported slave numbers */ | |
177 | enum rockchip_ssi_type type; | |
178 | ||
179 | u16 mode; | |
180 | u8 tmode; | |
181 | u8 bpw; | |
182 | u8 n_bytes; | |
108b5c8b | 183 | u32 rsd_nsecs; |
64e36824 | 184 | unsigned len; |
185 | u32 speed; | |
186 | ||
187 | const void *tx; | |
188 | const void *tx_end; | |
189 | void *rx; | |
190 | void *rx_end; | |
191 | ||
192 | u32 state; | |
5dcc44ed | 193 | /* protect state */ |
64e36824 | 194 | spinlock_t lock; |
195 | ||
64e36824 | 196 | u32 use_dma; |
197 | struct sg_table tx_sg; | |
198 | struct sg_table rx_sg; | |
199 | struct rockchip_spi_dma_data dma_rx; | |
200 | struct rockchip_spi_dma_data dma_tx; | |
80abf888 | 201 | struct dma_slave_caps dma_caps; |
64e36824 | 202 | }; |
203 | ||
204 | static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) | |
205 | { | |
206 | writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); | |
207 | } | |
208 | ||
209 | static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) | |
210 | { | |
211 | writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); | |
212 | } | |
213 | ||
214 | static inline void flush_fifo(struct rockchip_spi *rs) | |
215 | { | |
216 | while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) | |
217 | readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
218 | } | |
219 | ||
2df08e78 AK |
220 | static inline void wait_for_idle(struct rockchip_spi *rs) |
221 | { | |
222 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
223 | ||
224 | do { | |
225 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
226 | return; | |
64bc0110 | 227 | } while (!time_after(jiffies, timeout)); |
2df08e78 AK |
228 | |
229 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
230 | } | |
231 | ||
64e36824 | 232 | static u32 get_fifo_len(struct rockchip_spi *rs) |
233 | { | |
234 | u32 fifo; | |
235 | ||
236 | for (fifo = 2; fifo < 32; fifo++) { | |
237 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
238 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) | |
239 | break; | |
240 | } | |
241 | ||
242 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
243 | ||
244 | return (fifo == 31) ? 0 : fifo; | |
245 | } | |
246 | ||
247 | static inline u32 tx_max(struct rockchip_spi *rs) | |
248 | { | |
249 | u32 tx_left, tx_room; | |
250 | ||
251 | tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; | |
252 | tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); | |
253 | ||
254 | return min(tx_left, tx_room); | |
255 | } | |
256 | ||
257 | static inline u32 rx_max(struct rockchip_spi *rs) | |
258 | { | |
259 | u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; | |
260 | u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); | |
261 | ||
262 | return min(rx_left, rx_room); | |
263 | } | |
264 | ||
265 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) | |
266 | { | |
267 | u32 ser; | |
b920cc31 HH |
268 | struct spi_master *master = spi->master; |
269 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
270 | ||
271 | pm_runtime_get_sync(rs->dev); | |
64e36824 | 272 | |
273 | ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; | |
274 | ||
275 | /* | |
276 | * drivers/spi/spi.c: | |
277 | * static void spi_set_cs(struct spi_device *spi, bool enable) | |
278 | * { | |
279 | * if (spi->mode & SPI_CS_HIGH) | |
280 | * enable = !enable; | |
281 | * | |
282 | * if (spi->cs_gpio >= 0) | |
283 | * gpio_set_value(spi->cs_gpio, !enable); | |
284 | * else if (spi->master->set_cs) | |
285 | * spi->master->set_cs(spi, !enable); | |
286 | * } | |
287 | * | |
288 | * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) | |
289 | */ | |
290 | if (!enable) | |
291 | ser |= 1 << spi->chip_select; | |
292 | else | |
293 | ser &= ~(1 << spi->chip_select); | |
294 | ||
295 | writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); | |
b920cc31 HH |
296 | |
297 | pm_runtime_put_sync(rs->dev); | |
64e36824 | 298 | } |
299 | ||
300 | static int rockchip_spi_prepare_message(struct spi_master *master, | |
5dcc44ed | 301 | struct spi_message *msg) |
64e36824 | 302 | { |
303 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
304 | struct spi_device *spi = msg->spi; | |
305 | ||
64e36824 | 306 | rs->mode = spi->mode; |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
2291793c AS |
311 | static void rockchip_spi_handle_err(struct spi_master *master, |
312 | struct spi_message *msg) | |
64e36824 | 313 | { |
314 | unsigned long flags; | |
315 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
316 | ||
317 | spin_lock_irqsave(&rs->lock, flags); | |
318 | ||
5dcc44ed AK |
319 | /* |
320 | * For DMA mode, we need terminate DMA channel and flush | |
321 | * fifo for the next transfer if DMA thansfer timeout. | |
2291793c AS |
322 | * handle_err() was called by core if transfer failed. |
323 | * Maybe it is reasonable for error handling here. | |
5dcc44ed | 324 | */ |
64e36824 | 325 | if (rs->use_dma) { |
326 | if (rs->state & RXBUSY) { | |
557b7ea3 | 327 | dmaengine_terminate_async(rs->dma_rx.ch); |
64e36824 | 328 | flush_fifo(rs); |
329 | } | |
330 | ||
331 | if (rs->state & TXBUSY) | |
557b7ea3 | 332 | dmaengine_terminate_async(rs->dma_tx.ch); |
64e36824 | 333 | } |
334 | ||
335 | spin_unlock_irqrestore(&rs->lock, flags); | |
2291793c AS |
336 | } |
337 | ||
338 | static int rockchip_spi_unprepare_message(struct spi_master *master, | |
339 | struct spi_message *msg) | |
340 | { | |
341 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
64e36824 | 342 | |
c28be31b AK |
343 | spi_enable_chip(rs, 0); |
344 | ||
64e36824 | 345 | return 0; |
346 | } | |
347 | ||
348 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
349 | { | |
350 | u32 max = tx_max(rs); | |
351 | u32 txw = 0; | |
352 | ||
353 | while (max--) { | |
354 | if (rs->n_bytes == 1) | |
355 | txw = *(u8 *)(rs->tx); | |
356 | else | |
357 | txw = *(u16 *)(rs->tx); | |
358 | ||
359 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
360 | rs->tx += rs->n_bytes; | |
361 | } | |
362 | } | |
363 | ||
364 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
365 | { | |
366 | u32 max = rx_max(rs); | |
367 | u32 rxw; | |
368 | ||
369 | while (max--) { | |
370 | rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
371 | if (rs->n_bytes == 1) | |
372 | *(u8 *)(rs->rx) = (u8)rxw; | |
373 | else | |
374 | *(u16 *)(rs->rx) = (u16)rxw; | |
375 | rs->rx += rs->n_bytes; | |
5dcc44ed | 376 | } |
64e36824 | 377 | } |
378 | ||
379 | static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) | |
380 | { | |
381 | int remain = 0; | |
382 | ||
383 | do { | |
384 | if (rs->tx) { | |
385 | remain = rs->tx_end - rs->tx; | |
386 | rockchip_spi_pio_writer(rs); | |
387 | } | |
388 | ||
389 | if (rs->rx) { | |
390 | remain = rs->rx_end - rs->rx; | |
391 | rockchip_spi_pio_reader(rs); | |
392 | } | |
393 | ||
394 | cpu_relax(); | |
395 | } while (remain); | |
396 | ||
2df08e78 AK |
397 | /* If tx, wait until the FIFO data completely. */ |
398 | if (rs->tx) | |
399 | wait_for_idle(rs); | |
400 | ||
c28be31b AK |
401 | spi_enable_chip(rs, 0); |
402 | ||
64e36824 | 403 | return 0; |
404 | } | |
405 | ||
406 | static void rockchip_spi_dma_rxcb(void *data) | |
407 | { | |
408 | unsigned long flags; | |
409 | struct rockchip_spi *rs = data; | |
410 | ||
411 | spin_lock_irqsave(&rs->lock, flags); | |
412 | ||
413 | rs->state &= ~RXBUSY; | |
c28be31b AK |
414 | if (!(rs->state & TXBUSY)) { |
415 | spi_enable_chip(rs, 0); | |
64e36824 | 416 | spi_finalize_current_transfer(rs->master); |
c28be31b | 417 | } |
64e36824 | 418 | |
419 | spin_unlock_irqrestore(&rs->lock, flags); | |
420 | } | |
421 | ||
422 | static void rockchip_spi_dma_txcb(void *data) | |
423 | { | |
424 | unsigned long flags; | |
425 | struct rockchip_spi *rs = data; | |
426 | ||
2df08e78 AK |
427 | /* Wait until the FIFO data completely. */ |
428 | wait_for_idle(rs); | |
429 | ||
64e36824 | 430 | spin_lock_irqsave(&rs->lock, flags); |
431 | ||
432 | rs->state &= ~TXBUSY; | |
2c2bc748 AK |
433 | if (!(rs->state & RXBUSY)) { |
434 | spi_enable_chip(rs, 0); | |
64e36824 | 435 | spi_finalize_current_transfer(rs->master); |
2c2bc748 | 436 | } |
64e36824 | 437 | |
438 | spin_unlock_irqrestore(&rs->lock, flags); | |
439 | } | |
440 | ||
ea984911 | 441 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs) |
64e36824 | 442 | { |
443 | unsigned long flags; | |
444 | struct dma_slave_config rxconf, txconf; | |
445 | struct dma_async_tx_descriptor *rxdesc, *txdesc; | |
446 | ||
447 | spin_lock_irqsave(&rs->lock, flags); | |
448 | rs->state &= ~RXBUSY; | |
449 | rs->state &= ~TXBUSY; | |
450 | spin_unlock_irqrestore(&rs->lock, flags); | |
451 | ||
97cf5669 | 452 | rxdesc = NULL; |
64e36824 | 453 | if (rs->rx) { |
454 | rxconf.direction = rs->dma_rx.direction; | |
455 | rxconf.src_addr = rs->dma_rx.addr; | |
456 | rxconf.src_addr_width = rs->n_bytes; | |
80abf888 AK |
457 | if (rs->dma_caps.max_burst > 4) |
458 | rxconf.src_maxburst = 4; | |
459 | else | |
460 | rxconf.src_maxburst = 1; | |
64e36824 | 461 | dmaengine_slave_config(rs->dma_rx.ch, &rxconf); |
462 | ||
5dcc44ed AK |
463 | rxdesc = dmaengine_prep_slave_sg( |
464 | rs->dma_rx.ch, | |
64e36824 | 465 | rs->rx_sg.sgl, rs->rx_sg.nents, |
466 | rs->dma_rx.direction, DMA_PREP_INTERRUPT); | |
ea984911 SL |
467 | if (!rxdesc) |
468 | return -EINVAL; | |
64e36824 | 469 | |
470 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
471 | rxdesc->callback_param = rs; | |
472 | } | |
473 | ||
97cf5669 | 474 | txdesc = NULL; |
64e36824 | 475 | if (rs->tx) { |
476 | txconf.direction = rs->dma_tx.direction; | |
477 | txconf.dst_addr = rs->dma_tx.addr; | |
478 | txconf.dst_addr_width = rs->n_bytes; | |
80abf888 AK |
479 | if (rs->dma_caps.max_burst > 4) |
480 | txconf.dst_maxburst = 4; | |
481 | else | |
482 | txconf.dst_maxburst = 1; | |
64e36824 | 483 | dmaengine_slave_config(rs->dma_tx.ch, &txconf); |
484 | ||
5dcc44ed AK |
485 | txdesc = dmaengine_prep_slave_sg( |
486 | rs->dma_tx.ch, | |
64e36824 | 487 | rs->tx_sg.sgl, rs->tx_sg.nents, |
488 | rs->dma_tx.direction, DMA_PREP_INTERRUPT); | |
ea984911 SL |
489 | if (!txdesc) { |
490 | if (rxdesc) | |
491 | dmaengine_terminate_sync(rs->dma_rx.ch); | |
492 | return -EINVAL; | |
493 | } | |
64e36824 | 494 | |
495 | txdesc->callback = rockchip_spi_dma_txcb; | |
496 | txdesc->callback_param = rs; | |
497 | } | |
498 | ||
499 | /* rx must be started before tx due to spi instinct */ | |
97cf5669 | 500 | if (rxdesc) { |
64e36824 | 501 | spin_lock_irqsave(&rs->lock, flags); |
502 | rs->state |= RXBUSY; | |
503 | spin_unlock_irqrestore(&rs->lock, flags); | |
504 | dmaengine_submit(rxdesc); | |
505 | dma_async_issue_pending(rs->dma_rx.ch); | |
506 | } | |
507 | ||
97cf5669 | 508 | if (txdesc) { |
64e36824 | 509 | spin_lock_irqsave(&rs->lock, flags); |
510 | rs->state |= TXBUSY; | |
511 | spin_unlock_irqrestore(&rs->lock, flags); | |
512 | dmaengine_submit(txdesc); | |
513 | dma_async_issue_pending(rs->dma_tx.ch); | |
514 | } | |
ea984911 SL |
515 | |
516 | return 0; | |
64e36824 | 517 | } |
518 | ||
519 | static void rockchip_spi_config(struct rockchip_spi *rs) | |
520 | { | |
521 | u32 div = 0; | |
522 | u32 dmacr = 0; | |
76b17e6e | 523 | int rsd = 0; |
64e36824 | 524 | |
525 | u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) | |
0277e01a AK |
526 | | (CR0_SSD_ONE << CR0_SSD_OFFSET) |
527 | | (CR0_EM_BIG << CR0_EM_OFFSET); | |
64e36824 | 528 | |
529 | cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); | |
530 | cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); | |
531 | cr0 |= (rs->tmode << CR0_XFM_OFFSET); | |
532 | cr0 |= (rs->type << CR0_FRF_OFFSET); | |
533 | ||
534 | if (rs->use_dma) { | |
535 | if (rs->tx) | |
536 | dmacr |= TF_DMA_EN; | |
537 | if (rs->rx) | |
538 | dmacr |= RF_DMA_EN; | |
539 | } | |
540 | ||
f9cfd522 AK |
541 | if (WARN_ON(rs->speed > MAX_SCLK_OUT)) |
542 | rs->speed = MAX_SCLK_OUT; | |
543 | ||
bb51537a | 544 | /* the minimum divisor is 2 */ |
f9cfd522 AK |
545 | if (rs->max_freq < 2 * rs->speed) { |
546 | clk_set_rate(rs->spiclk, 2 * rs->speed); | |
547 | rs->max_freq = clk_get_rate(rs->spiclk); | |
548 | } | |
549 | ||
64e36824 | 550 | /* div doesn't support odd number */ |
754ec43c | 551 | div = DIV_ROUND_UP(rs->max_freq, rs->speed); |
64e36824 | 552 | div = (div + 1) & 0xfffe; |
553 | ||
76b17e6e JW |
554 | /* Rx sample delay is expressed in parent clock cycles (max 3) */ |
555 | rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), | |
556 | 1000000000 >> 8); | |
557 | if (!rsd && rs->rsd_nsecs) { | |
558 | pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", | |
559 | rs->max_freq, rs->rsd_nsecs); | |
560 | } else if (rsd > 3) { | |
561 | rsd = 3; | |
562 | pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", | |
563 | rs->max_freq, rs->rsd_nsecs, | |
564 | rsd * 1000000000U / rs->max_freq); | |
565 | } | |
566 | cr0 |= rsd << CR0_RSD_OFFSET; | |
567 | ||
64e36824 | 568 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
569 | ||
570 | writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
571 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
572 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
573 | ||
574 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); | |
575 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); | |
576 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); | |
577 | ||
578 | spi_set_clk(rs, div); | |
579 | ||
5dcc44ed | 580 | dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); |
64e36824 | 581 | } |
582 | ||
5185a81c BN |
583 | static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) |
584 | { | |
585 | return ROCKCHIP_SPI_MAX_TRANLEN; | |
586 | } | |
587 | ||
5dcc44ed AK |
588 | static int rockchip_spi_transfer_one( |
589 | struct spi_master *master, | |
64e36824 | 590 | struct spi_device *spi, |
591 | struct spi_transfer *xfer) | |
592 | { | |
4dc0dd83 | 593 | int ret = 0; |
64e36824 | 594 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
595 | ||
62946172 DA |
596 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
597 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
64e36824 | 598 | |
599 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
600 | dev_err(rs->dev, "No buffer for transfer\n"); | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
5185a81c BN |
604 | if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { |
605 | dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
64e36824 | 609 | rs->speed = xfer->speed_hz; |
610 | rs->bpw = xfer->bits_per_word; | |
611 | rs->n_bytes = rs->bpw >> 3; | |
612 | ||
613 | rs->tx = xfer->tx_buf; | |
614 | rs->tx_end = rs->tx + xfer->len; | |
615 | rs->rx = xfer->rx_buf; | |
616 | rs->rx_end = rs->rx + xfer->len; | |
617 | rs->len = xfer->len; | |
618 | ||
619 | rs->tx_sg = xfer->tx_sg; | |
620 | rs->rx_sg = xfer->rx_sg; | |
621 | ||
64e36824 | 622 | if (rs->tx && rs->rx) |
623 | rs->tmode = CR0_XFM_TR; | |
624 | else if (rs->tx) | |
625 | rs->tmode = CR0_XFM_TO; | |
626 | else if (rs->rx) | |
627 | rs->tmode = CR0_XFM_RO; | |
628 | ||
a24e70c0 | 629 | /* we need prepare dma before spi was enabled */ |
c28be31b | 630 | if (master->can_dma && master->can_dma(master, spi, xfer)) |
64e36824 | 631 | rs->use_dma = 1; |
c28be31b | 632 | else |
64e36824 | 633 | rs->use_dma = 0; |
634 | ||
635 | rockchip_spi_config(rs); | |
636 | ||
c28be31b AK |
637 | if (rs->use_dma) { |
638 | if (rs->tmode == CR0_XFM_RO) { | |
639 | /* rx: dma must be prepared first */ | |
ea984911 | 640 | ret = rockchip_spi_prepare_dma(rs); |
c28be31b AK |
641 | spi_enable_chip(rs, 1); |
642 | } else { | |
643 | /* tx or tr: spi must be enabled first */ | |
644 | spi_enable_chip(rs, 1); | |
ea984911 | 645 | ret = rockchip_spi_prepare_dma(rs); |
c28be31b | 646 | } |
4dc0dd83 TV |
647 | /* successful DMA prepare means the transfer is in progress */ |
648 | ret = ret ? ret : 1; | |
c28be31b AK |
649 | } else { |
650 | spi_enable_chip(rs, 1); | |
64e36824 | 651 | ret = rockchip_spi_pio_transfer(rs); |
c28be31b | 652 | } |
64e36824 | 653 | |
654 | return ret; | |
655 | } | |
656 | ||
657 | static bool rockchip_spi_can_dma(struct spi_master *master, | |
5dcc44ed AK |
658 | struct spi_device *spi, |
659 | struct spi_transfer *xfer) | |
64e36824 | 660 | { |
661 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
662 | ||
663 | return (xfer->len > rs->fifo_len); | |
664 | } | |
665 | ||
666 | static int rockchip_spi_probe(struct platform_device *pdev) | |
667 | { | |
668 | int ret = 0; | |
669 | struct rockchip_spi *rs; | |
670 | struct spi_master *master; | |
671 | struct resource *mem; | |
76b17e6e | 672 | u32 rsd_nsecs; |
64e36824 | 673 | |
674 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); | |
5dcc44ed | 675 | if (!master) |
64e36824 | 676 | return -ENOMEM; |
5dcc44ed | 677 | |
64e36824 | 678 | platform_set_drvdata(pdev, master); |
679 | ||
680 | rs = spi_master_get_devdata(master); | |
64e36824 | 681 | |
682 | /* Get basic io resource and map it */ | |
683 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
684 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
685 | if (IS_ERR(rs->regs)) { | |
64e36824 | 686 | ret = PTR_ERR(rs->regs); |
687 | goto err_ioremap_resource; | |
688 | } | |
689 | ||
690 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
691 | if (IS_ERR(rs->apb_pclk)) { | |
692 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
693 | ret = PTR_ERR(rs->apb_pclk); | |
694 | goto err_ioremap_resource; | |
695 | } | |
696 | ||
697 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
698 | if (IS_ERR(rs->spiclk)) { | |
699 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
700 | ret = PTR_ERR(rs->spiclk); | |
701 | goto err_ioremap_resource; | |
702 | } | |
703 | ||
704 | ret = clk_prepare_enable(rs->apb_pclk); | |
705 | if (ret) { | |
706 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); | |
707 | goto err_ioremap_resource; | |
708 | } | |
709 | ||
710 | ret = clk_prepare_enable(rs->spiclk); | |
711 | if (ret) { | |
712 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); | |
713 | goto err_spiclk_enable; | |
714 | } | |
715 | ||
716 | spi_enable_chip(rs, 0); | |
717 | ||
718 | rs->type = SSI_MOTO_SPI; | |
719 | rs->master = master; | |
720 | rs->dev = &pdev->dev; | |
721 | rs->max_freq = clk_get_rate(rs->spiclk); | |
722 | ||
76b17e6e JW |
723 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
724 | &rsd_nsecs)) | |
725 | rs->rsd_nsecs = rsd_nsecs; | |
726 | ||
64e36824 | 727 | rs->fifo_len = get_fifo_len(rs); |
728 | if (!rs->fifo_len) { | |
729 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
db7e8d90 | 730 | ret = -EINVAL; |
64e36824 | 731 | goto err_get_fifo_len; |
732 | } | |
733 | ||
734 | spin_lock_init(&rs->lock); | |
735 | ||
736 | pm_runtime_set_active(&pdev->dev); | |
737 | pm_runtime_enable(&pdev->dev); | |
738 | ||
739 | master->auto_runtime_pm = true; | |
740 | master->bus_num = pdev->id; | |
ee780997 | 741 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
64e36824 | 742 | master->num_chipselect = 2; |
743 | master->dev.of_node = pdev->dev.of_node; | |
744 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); | |
745 | ||
746 | master->set_cs = rockchip_spi_set_cs; | |
747 | master->prepare_message = rockchip_spi_prepare_message; | |
748 | master->unprepare_message = rockchip_spi_unprepare_message; | |
749 | master->transfer_one = rockchip_spi_transfer_one; | |
5185a81c | 750 | master->max_transfer_size = rockchip_spi_max_transfer_size; |
2291793c | 751 | master->handle_err = rockchip_spi_handle_err; |
64e36824 | 752 | |
e4c0e06f SL |
753 | rs->dma_tx.ch = dma_request_chan(rs->dev, "tx"); |
754 | if (IS_ERR(rs->dma_tx.ch)) { | |
61cadcf4 SL |
755 | /* Check tx to see if we need defer probing driver */ |
756 | if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) { | |
757 | ret = -EPROBE_DEFER; | |
758 | goto err_get_fifo_len; | |
759 | } | |
64e36824 | 760 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
e4c0e06f | 761 | rs->dma_tx.ch = NULL; |
61cadcf4 | 762 | } |
64e36824 | 763 | |
e4c0e06f SL |
764 | rs->dma_rx.ch = dma_request_chan(rs->dev, "rx"); |
765 | if (IS_ERR(rs->dma_rx.ch)) { | |
766 | if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) { | |
e4c0e06f | 767 | ret = -EPROBE_DEFER; |
5de7ed0c | 768 | goto err_free_dma_tx; |
64e36824 | 769 | } |
770 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
e4c0e06f | 771 | rs->dma_rx.ch = NULL; |
64e36824 | 772 | } |
773 | ||
774 | if (rs->dma_tx.ch && rs->dma_rx.ch) { | |
80abf888 | 775 | dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps)); |
64e36824 | 776 | rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); |
777 | rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); | |
778 | rs->dma_tx.direction = DMA_MEM_TO_DEV; | |
0ac7a490 | 779 | rs->dma_rx.direction = DMA_DEV_TO_MEM; |
64e36824 | 780 | |
781 | master->can_dma = rockchip_spi_can_dma; | |
782 | master->dma_tx = rs->dma_tx.ch; | |
783 | master->dma_rx = rs->dma_rx.ch; | |
784 | } | |
785 | ||
786 | ret = devm_spi_register_master(&pdev->dev, master); | |
787 | if (ret) { | |
788 | dev_err(&pdev->dev, "Failed to register master\n"); | |
789 | goto err_register_master; | |
790 | } | |
791 | ||
64e36824 | 792 | return 0; |
793 | ||
794 | err_register_master: | |
b8659add | 795 | pm_runtime_disable(&pdev->dev); |
64e36824 | 796 | if (rs->dma_rx.ch) |
797 | dma_release_channel(rs->dma_rx.ch); | |
5de7ed0c DC |
798 | err_free_dma_tx: |
799 | if (rs->dma_tx.ch) | |
800 | dma_release_channel(rs->dma_tx.ch); | |
64e36824 | 801 | err_get_fifo_len: |
802 | clk_disable_unprepare(rs->spiclk); | |
803 | err_spiclk_enable: | |
804 | clk_disable_unprepare(rs->apb_pclk); | |
805 | err_ioremap_resource: | |
806 | spi_master_put(master); | |
807 | ||
808 | return ret; | |
809 | } | |
810 | ||
811 | static int rockchip_spi_remove(struct platform_device *pdev) | |
812 | { | |
813 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
814 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
815 | ||
816 | pm_runtime_disable(&pdev->dev); | |
817 | ||
818 | clk_disable_unprepare(rs->spiclk); | |
819 | clk_disable_unprepare(rs->apb_pclk); | |
820 | ||
821 | if (rs->dma_tx.ch) | |
822 | dma_release_channel(rs->dma_tx.ch); | |
823 | if (rs->dma_rx.ch) | |
824 | dma_release_channel(rs->dma_rx.ch); | |
825 | ||
844c9f47 SL |
826 | spi_master_put(master); |
827 | ||
64e36824 | 828 | return 0; |
829 | } | |
830 | ||
831 | #ifdef CONFIG_PM_SLEEP | |
832 | static int rockchip_spi_suspend(struct device *dev) | |
833 | { | |
834 | int ret = 0; | |
835 | struct spi_master *master = dev_get_drvdata(dev); | |
836 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
837 | ||
838 | ret = spi_master_suspend(rs->master); | |
839 | if (ret) | |
840 | return ret; | |
841 | ||
842 | if (!pm_runtime_suspended(dev)) { | |
843 | clk_disable_unprepare(rs->spiclk); | |
844 | clk_disable_unprepare(rs->apb_pclk); | |
845 | } | |
846 | ||
23e291c2 BN |
847 | pinctrl_pm_select_sleep_state(dev); |
848 | ||
64e36824 | 849 | return ret; |
850 | } | |
851 | ||
852 | static int rockchip_spi_resume(struct device *dev) | |
853 | { | |
854 | int ret = 0; | |
855 | struct spi_master *master = dev_get_drvdata(dev); | |
856 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
857 | ||
23e291c2 BN |
858 | pinctrl_pm_select_default_state(dev); |
859 | ||
64e36824 | 860 | if (!pm_runtime_suspended(dev)) { |
861 | ret = clk_prepare_enable(rs->apb_pclk); | |
862 | if (ret < 0) | |
863 | return ret; | |
864 | ||
865 | ret = clk_prepare_enable(rs->spiclk); | |
866 | if (ret < 0) { | |
867 | clk_disable_unprepare(rs->apb_pclk); | |
868 | return ret; | |
869 | } | |
870 | } | |
871 | ||
872 | ret = spi_master_resume(rs->master); | |
873 | if (ret < 0) { | |
874 | clk_disable_unprepare(rs->spiclk); | |
875 | clk_disable_unprepare(rs->apb_pclk); | |
876 | } | |
877 | ||
878 | return ret; | |
879 | } | |
880 | #endif /* CONFIG_PM_SLEEP */ | |
881 | ||
ec833050 | 882 | #ifdef CONFIG_PM |
64e36824 | 883 | static int rockchip_spi_runtime_suspend(struct device *dev) |
884 | { | |
885 | struct spi_master *master = dev_get_drvdata(dev); | |
886 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
887 | ||
888 | clk_disable_unprepare(rs->spiclk); | |
889 | clk_disable_unprepare(rs->apb_pclk); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static int rockchip_spi_runtime_resume(struct device *dev) | |
895 | { | |
896 | int ret; | |
897 | struct spi_master *master = dev_get_drvdata(dev); | |
898 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
899 | ||
900 | ret = clk_prepare_enable(rs->apb_pclk); | |
901 | if (ret) | |
902 | return ret; | |
903 | ||
904 | ret = clk_prepare_enable(rs->spiclk); | |
905 | if (ret) | |
906 | clk_disable_unprepare(rs->apb_pclk); | |
907 | ||
908 | return ret; | |
909 | } | |
ec833050 | 910 | #endif /* CONFIG_PM */ |
64e36824 | 911 | |
912 | static const struct dev_pm_ops rockchip_spi_pm = { | |
913 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
914 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
915 | rockchip_spi_runtime_resume, NULL) | |
916 | }; | |
917 | ||
918 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
aa29ea3d | 919 | { .compatible = "rockchip,rk3036-spi", }, |
64e36824 | 920 | { .compatible = "rockchip,rk3066-spi", }, |
b839b785 | 921 | { .compatible = "rockchip,rk3188-spi", }, |
aa29ea3d | 922 | { .compatible = "rockchip,rk3228-spi", }, |
b839b785 | 923 | { .compatible = "rockchip,rk3288-spi", }, |
aa29ea3d | 924 | { .compatible = "rockchip,rk3368-spi", }, |
9b7a5622 | 925 | { .compatible = "rockchip,rk3399-spi", }, |
64e36824 | 926 | { }, |
927 | }; | |
928 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
929 | ||
930 | static struct platform_driver rockchip_spi_driver = { | |
931 | .driver = { | |
932 | .name = DRIVER_NAME, | |
64e36824 | 933 | .pm = &rockchip_spi_pm, |
934 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
935 | }, | |
936 | .probe = rockchip_spi_probe, | |
937 | .remove = rockchip_spi_remove, | |
938 | }; | |
939 | ||
940 | module_platform_driver(rockchip_spi_driver); | |
941 | ||
5dcc44ed | 942 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 943 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
944 | MODULE_LICENSE("GPL v2"); |