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Merge drm/drm-next into drm-misc-next
[linux-block.git] / drivers / spi / spi-rockchip.c
CommitLineData
2025cf9e 1// SPDX-License-Identifier: GPL-2.0-only
64e36824 2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5dcc44ed 4 * Author: Addy Ke <addy.ke@rock-chips.com>
64e36824 5 */
6
64e36824 7#include <linux/clk.h>
ec5c5d8a 8#include <linux/dmaengine.h>
8af0c18a 9#include <linux/interrupt.h>
ec5c5d8a
SL		 10#include <linux/module.h>
11#include <linux/of.h>
23e291c2 12#include <linux/pinctrl/consumer.h>
64e36824 13#include <linux/platform_device.h>
64e36824 14#include <linux/spi/spi.h>
64e36824 15#include <linux/pm_runtime.h>
ec5c5d8a 16#include <linux/scatterlist.h>
64e36824 17
18#define DRIVER_NAME "rockchip-spi"
19
aa099382
JC		 20#define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
22#define ROCKCHIP_SPI_SET_BITS(reg, bits) \
23 writel_relaxed(readl_relaxed(reg) | (bits), reg)
24
64e36824 25/* SPI register offsets */
26#define ROCKCHIP_SPI_CTRLR0 0x0000
27#define ROCKCHIP_SPI_CTRLR1 0x0004
28#define ROCKCHIP_SPI_SSIENR 0x0008
29#define ROCKCHIP_SPI_SER 0x000c
30#define ROCKCHIP_SPI_BAUDR 0x0010
31#define ROCKCHIP_SPI_TXFTLR 0x0014
32#define ROCKCHIP_SPI_RXFTLR 0x0018
33#define ROCKCHIP_SPI_TXFLR 0x001c
34#define ROCKCHIP_SPI_RXFLR 0x0020
35#define ROCKCHIP_SPI_SR 0x0024
36#define ROCKCHIP_SPI_IPR 0x0028
37#define ROCKCHIP_SPI_IMR 0x002c
38#define ROCKCHIP_SPI_ISR 0x0030
39#define ROCKCHIP_SPI_RISR 0x0034
40#define ROCKCHIP_SPI_ICR 0x0038
41#define ROCKCHIP_SPI_DMACR 0x003c
13a96935
JL		 42#define ROCKCHIP_SPI_DMATDLR 0x0040
43#define ROCKCHIP_SPI_DMARDLR 0x0044
44#define ROCKCHIP_SPI_VERSION 0x0048
64e36824 45#define ROCKCHIP_SPI_TXDR 0x0400
46#define ROCKCHIP_SPI_RXDR 0x0800
47
48/* Bit fields in CTRLR0 */
49#define CR0_DFS_OFFSET 0
65498c6a
ERB		 50#define CR0_DFS_4BIT 0x0
51#define CR0_DFS_8BIT 0x1
52#define CR0_DFS_16BIT 0x2
64e36824 53
54#define CR0_CFS_OFFSET 2
55
56#define CR0_SCPH_OFFSET 6
57
58#define CR0_SCPOL_OFFSET 7
59
60#define CR0_CSM_OFFSET 8
61#define CR0_CSM_KEEP 0x0
62/* ss_n be high for half sclk_out cycles */
63#define CR0_CSM_HALF 0X1
64/* ss_n be high for one sclk_out cycle */
65#define CR0_CSM_ONE 0x2
66
67/* ss_n to sclk_out delay */
68#define CR0_SSD_OFFSET 10
69/*
70 * The period between ss_n active and
71 * sclk_out active is half sclk_out cycles
72 */
73#define CR0_SSD_HALF 0x0
74/*
75 * The period between ss_n active and
76 * sclk_out active is one sclk_out cycle
77 */
78#define CR0_SSD_ONE 0x1
79
80#define CR0_EM_OFFSET 11
81#define CR0_EM_LITTLE 0x0
82#define CR0_EM_BIG 0x1
83
84#define CR0_FBM_OFFSET 12
85#define CR0_FBM_MSB 0x0
86#define CR0_FBM_LSB 0x1
87
88#define CR0_BHT_OFFSET 13
89#define CR0_BHT_16BIT 0x0
90#define CR0_BHT_8BIT 0x1
91
92#define CR0_RSD_OFFSET 14
74b7efa8 93#define CR0_RSD_MAX 0x3
64e36824 94
95#define CR0_FRF_OFFSET 16
96#define CR0_FRF_SPI 0x0
97#define CR0_FRF_SSP 0x1
98#define CR0_FRF_MICROWIRE 0x2
99
100#define CR0_XFM_OFFSET 18
101#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
102#define CR0_XFM_TR 0x0
103#define CR0_XFM_TO 0x1
104#define CR0_XFM_RO 0x2
105
106#define CR0_OPM_OFFSET 20
107#define CR0_OPM_MASTER 0x0
108#define CR0_OPM_SLAVE 0x1
109
736b81e0
JL		 110#define CR0_SOI_OFFSET 23
111
64e36824 112#define CR0_MTM_OFFSET 0x21
113
114/* Bit fields in SER, 2bit */
115#define SER_MASK 0x3
116
420b82f8
ERB		 117/* Bit fields in BAUDR */
118#define BAUDR_SCKDV_MIN 2
119#define BAUDR_SCKDV_MAX 65534
120
2758bd09
JL		 121/* Bit fields in SR, 6bit */
122#define SR_MASK 0x3f
64e36824 123#define SR_BUSY (1 << 0)
124#define SR_TF_FULL (1 << 1)
125#define SR_TF_EMPTY (1 << 2)
126#define SR_RF_EMPTY (1 << 3)
127#define SR_RF_FULL (1 << 4)
2758bd09 128#define SR_SLAVE_TX_BUSY (1 << 5)
64e36824 129
130/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
131#define INT_MASK 0x1f
132#define INT_TF_EMPTY (1 << 0)
133#define INT_TF_OVERFLOW (1 << 1)
134#define INT_RF_UNDERFLOW (1 << 2)
135#define INT_RF_OVERFLOW (1 << 3)
869f2c94
JL		 136#define INT_RF_FULL (1 << 4)
137#define INT_CS_INACTIVE (1 << 6)
64e36824 138
139/* Bit fields in ICR, 4bit */
140#define ICR_MASK 0x0f
141#define ICR_ALL (1 << 0)
142#define ICR_RF_UNDERFLOW (1 << 1)
143#define ICR_RF_OVERFLOW (1 << 2)
144#define ICR_TF_OVERFLOW (1 << 3)
145
146/* Bit fields in DMACR */
147#define RF_DMA_EN (1 << 0)
148#define TF_DMA_EN (1 << 1)
149
fab3e487
ERB		 150/* Driver state flags */
151#define RXDMA (1 << 0)
152#define TXDMA (1 << 1)
64e36824 153
f9cfd522 154/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
420b82f8 155#define MAX_SCLK_OUT 50000000U
f9cfd522 156
5185a81c
BN		 157/*
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
159 * the controller seems to hang when given 0x10000, so stick with this for now.
160 */
161#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
162
b8d42371
JL		 163/* 2 for native cs, 2 for cs-gpio */
164#define ROCKCHIP_SPI_MAX_CS_NUM 4
13a96935
JL		 165#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
166#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
aa099382 167
940f3bbf
AK		 168#define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000
169
64e36824 170struct rockchip_spi {
171 struct device *dev;
64e36824 172
173 struct clk *spiclk;
174 struct clk *apb_pclk;
175
176 void __iomem *regs;
eee06a9e
ERB		 177 dma_addr_t dma_addr_rx;
178 dma_addr_t dma_addr_tx;
fab3e487 179
01b59ce5
ERB		 180 const void *tx;
181 void *rx;
182 unsigned int tx_left;
183 unsigned int rx_left;
184
fab3e487
ERB		 185 atomic_t state;
186
64e36824 187 /*depth of the FIFO buffer */
188 u32 fifo_len;
420b82f8
ERB		 189 /* frequency of spiclk */
190 u32 freq;
64e36824 191
64e36824 192 u8 n_bytes;
74b7efa8 193 u8 rsd;
64e36824 194
aa099382 195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
d065f41a
CR		 196
197 bool slave_abort;
869f2c94 198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */
d5d933f0
LC		 199 bool cs_high_supported; /* native CS supports active-high polarity */
200
869f2c94 201 struct spi_transfer *xfer; /* Store xfer temporarily */
64e36824 202};
203
30688e4e 204static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
64e36824 205{
30688e4e 206 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
64e36824 207}
208
2758bd09 209static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
2df08e78
AK		 210{
211 unsigned long timeout = jiffies + msecs_to_jiffies(5);
212
213 do {
2758bd09
JL		 214 if (slave_mode) {
215 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
216 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
217 return;
218 } else {
219 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
220 return;
221 }
64bc0110 222 } while (!time_after(jiffies, timeout));
2df08e78
AK		 223
224 dev_warn(rs->dev, "spi controller is in busy state!\n");
225}
226
64e36824 227static u32 get_fifo_len(struct rockchip_spi *rs)
228{
13a96935 229 u32 ver;
64e36824 230
13a96935 231 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
64e36824 232
13a96935
JL		 233 switch (ver) {
234 case ROCKCHIP_SPI_VER2_TYPE1:
235 case ROCKCHIP_SPI_VER2_TYPE2:
236 return 64;
237 default:
238 return 32;
239 }
64e36824 240}
241
64e36824 242static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
243{
d66571a2
CR		 244 struct spi_controller *ctlr = spi->controller;
245 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
736b81e0 246 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
b920cc31 247
aa099382
JC		 248 /* Return immediately for no-op */
249 if (cs_asserted == rs->cs_asserted[spi->chip_select])
250 return;
64e36824 251
aa099382
JC		 252 if (cs_asserted) {
253 /* Keep things powered as long as CS is asserted */
254 pm_runtime_get_sync(rs->dev);
64e36824 255
b8d42371
JL		 256 if (spi->cs_gpiod)
257 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
258 else
259 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
aa099382 260 } else {
b8d42371
JL		 261 if (spi->cs_gpiod)
262 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
263 else
264 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
64e36824 265
aa099382
JC		 266 /* Drop reference from when we first asserted CS */
267 pm_runtime_put(rs->dev);
268 }
b920cc31 269
aa099382 270 rs->cs_asserted[spi->chip_select] = cs_asserted;
64e36824 271}
272
d66571a2 273static void rockchip_spi_handle_err(struct spi_controller *ctlr,
2291793c 274 struct spi_message *msg)
64e36824 275{
d66571a2 276 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 277
ce386100
ERB		 278 /* stop running spi transfer
279 * this also flushes both rx and tx fifos
5dcc44ed 280 */
ce386100
ERB		 281 spi_enable_chip(rs, false);
282
2fcdde56 283 /* make sure all interrupts are masked and status cleared */
01b59ce5 284 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
2fcdde56 285 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
01b59ce5 286
fab3e487 287 if (atomic_read(&rs->state) & TXDMA)
d66571a2 288 dmaengine_terminate_async(ctlr->dma_tx);
64e36824 289
ce386100 290 if (atomic_read(&rs->state) & RXDMA)
d66571a2 291 dmaengine_terminate_async(ctlr->dma_rx);
64e36824 292}
293
294static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
295{
01b59ce5
ERB		 296 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
297 u32 words = min(rs->tx_left, tx_free);
298
299 rs->tx_left -= words;
300 for (; words; words--) {
301 u32 txw;
64e36824 302
64e36824 303 if (rs->n_bytes == 1)
01b59ce5 304 txw = *(u8 *)rs->tx;
64e36824 305 else
01b59ce5 306 txw = *(u16 *)rs->tx;
64e36824 307
308 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
309 rs->tx += rs->n_bytes;
310 }
311}
312
313static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
314{
01b59ce5 315 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
4294e4ac 316 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
01b59ce5
ERB		 317
318 /* the hardware doesn't allow us to change fifo threshold
319 * level while spi is enabled, so instead make sure to leave
320 * enough words in the rx fifo to get the last interrupt
321 * exactly when all words have been received
322 */
323 if (rx_left) {
324 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
325
326 if (rx_left < ftl) {
327 rx_left = ftl;
328 words = rs->rx_left - rx_left;
329 }
330 }
331
332 rs->rx_left = rx_left;
333 for (; words; words--) {
334 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
335
336 if (!rs->rx)
337 continue;
64e36824 338
64e36824 339 if (rs->n_bytes == 1)
01b59ce5 340 *(u8 *)rs->rx = (u8)rxw;
64e36824 341 else
01b59ce5 342 *(u16 *)rs->rx = (u16)rxw;
64e36824 343 rs->rx += rs->n_bytes;
5dcc44ed 344 }
64e36824 345}
346
01b59ce5 347static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
64e36824 348{
d66571a2
CR		 349 struct spi_controller *ctlr = dev_id;
350 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 351
869f2c94
JL		 352 /* When int_cs_inactive comes, spi slave abort */
353 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
354 ctlr->slave_abort(ctlr);
355 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
356 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
357
358 return IRQ_HANDLED;
359 }
360
01b59ce5
ERB		 361 if (rs->tx_left)
362 rockchip_spi_pio_writer(rs);
a3c17402 363
01b59ce5
ERB		 364 rockchip_spi_pio_reader(rs);
365 if (!rs->rx_left) {
366 spi_enable_chip(rs, false);
367 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
869f2c94 368 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
d66571a2 369 spi_finalize_current_transfer(ctlr);
01b59ce5 370 }
64e36824 371
01b59ce5
ERB		 372 return IRQ_HANDLED;
373}
64e36824 374
01b59ce5 375static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
869f2c94
JL		 376 struct spi_controller *ctlr,
377 struct spi_transfer *xfer)
01b59ce5
ERB		 378{
379 rs->tx = xfer->tx_buf;
380 rs->rx = xfer->rx_buf;
381 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
382 rs->rx_left = xfer->len / rs->n_bytes;
64e36824 383
419bc8f6
JL		 384 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
385
01b59ce5 386 spi_enable_chip(rs, true);
2df08e78 387
01b59ce5
ERB		 388 if (rs->tx_left)
389 rockchip_spi_pio_writer(rs);
c28be31b 390
419bc8f6
JL		 391 if (rs->cs_inactive)
392 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
393 else
394 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
395
01b59ce5
ERB		 396 /* 1 means the transfer is in progress */
397 return 1;
64e36824 398}
399
400static void rockchip_spi_dma_rxcb(void *data)
401{
d66571a2
CR		 402 struct spi_controller *ctlr = data;
403 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
fab3e487 404 int state = atomic_fetch_andnot(RXDMA, &rs->state);
64e36824 405
d065f41a 406 if (state & TXDMA && !rs->slave_abort)
fab3e487 407 return;
64e36824 408
869f2c94
JL		 409 if (rs->cs_inactive)
410 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
411
fab3e487 412 spi_enable_chip(rs, false);
d66571a2 413 spi_finalize_current_transfer(ctlr);
64e36824 414}
415
416static void rockchip_spi_dma_txcb(void *data)
417{
d66571a2
CR		 418 struct spi_controller *ctlr = data;
419 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
fab3e487
ERB		 420 int state = atomic_fetch_andnot(TXDMA, &rs->state);
421
d065f41a 422 if (state & RXDMA && !rs->slave_abort)
fab3e487 423 return;
64e36824 424
2df08e78 425 /* Wait until the FIFO data completely. */
2758bd09 426 wait_for_tx_idle(rs, ctlr->slave);
2df08e78 427
fab3e487 428 spi_enable_chip(rs, false);
d66571a2 429 spi_finalize_current_transfer(ctlr);
64e36824 430}
431
4d9ca632
JL		 432static u32 rockchip_spi_calc_burst_size(u32 data_len)
433{
434 u32 i;
435
436 /* burst size: 1, 2, 4, 8 */
437 for (i = 1; i < 8; i <<= 1) {
438 if (data_len & i)
439 break;
440 }
441
442 return i;
443}
444
fc1ad8ee 445static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
d66571a2 446 struct spi_controller *ctlr, struct spi_transfer *xfer)
64e36824 447{
64e36824 448 struct dma_async_tx_descriptor *rxdesc, *txdesc;
449
fab3e487 450 atomic_set(&rs->state, 0);
64e36824 451
869f2c94
JL		 452 rs->tx = xfer->tx_buf;
453 rs->rx = xfer->rx_buf;
454
97cf5669 455 rxdesc = NULL;
fc1ad8ee 456 if (xfer->rx_buf) {
31bcb57b
ERB		 457 struct dma_slave_config rxconf = {
458 .direction = DMA_DEV_TO_MEM,
eee06a9e 459 .src_addr = rs->dma_addr_rx,
31bcb57b 460 .src_addr_width = rs->n_bytes,
869f2c94 461 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
31bcb57b
ERB		 462 };
463
d66571a2 464 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
64e36824 465
5dcc44ed 466 rxdesc = dmaengine_prep_slave_sg(
d66571a2 467 ctlr->dma_rx,
fc1ad8ee 468 xfer->rx_sg.sgl, xfer->rx_sg.nents,
d9071b7e 469 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
ea984911
SL		 470 if (!rxdesc)
471 return -EINVAL;
64e36824 472
473 rxdesc->callback = rockchip_spi_dma_rxcb;
d66571a2 474 rxdesc->callback_param = ctlr;
64e36824 475 }
476
97cf5669 477 txdesc = NULL;
fc1ad8ee 478 if (xfer->tx_buf) {
31bcb57b
ERB		 479 struct dma_slave_config txconf = {
480 .direction = DMA_MEM_TO_DEV,
eee06a9e 481 .dst_addr = rs->dma_addr_tx,
31bcb57b 482 .dst_addr_width = rs->n_bytes,
47300728 483 .dst_maxburst = rs->fifo_len / 4,
31bcb57b
ERB		 484 };
485
d66571a2 486 dmaengine_slave_config(ctlr->dma_tx, &txconf);
64e36824 487
5dcc44ed 488 txdesc = dmaengine_prep_slave_sg(
d66571a2 489 ctlr->dma_tx,
fc1ad8ee 490 xfer->tx_sg.sgl, xfer->tx_sg.nents,
d9071b7e 491 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
ea984911
SL		 492 if (!txdesc) {
493 if (rxdesc)
d66571a2 494 dmaengine_terminate_sync(ctlr->dma_rx);
ea984911
SL		 495 return -EINVAL;
496 }
64e36824 497
498 txdesc->callback = rockchip_spi_dma_txcb;
d66571a2 499 txdesc->callback_param = ctlr;
64e36824 500 }
501
502 /* rx must be started before tx due to spi instinct */
97cf5669 503 if (rxdesc) {
fab3e487 504 atomic_or(RXDMA, &rs->state);
869f2c94 505 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
d66571a2 506 dma_async_issue_pending(ctlr->dma_rx);
64e36824 507 }
508
869f2c94
JL		 509 if (rs->cs_inactive)
510 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
511
30688e4e 512 spi_enable_chip(rs, true);
a3c17402 513
97cf5669 514 if (txdesc) {
fab3e487 515 atomic_or(TXDMA, &rs->state);
64e36824 516 dmaengine_submit(txdesc);
d66571a2 517 dma_async_issue_pending(ctlr->dma_tx);
64e36824 518 }
ea984911 519
a3c17402
ERB		 520 /* 1 means the transfer is in progress */
521 return 1;
64e36824 522}
523
e5098952 524static int rockchip_spi_config(struct rockchip_spi *rs,
eff0275e 525 struct spi_device *spi, struct spi_transfer *xfer,
d065f41a 526 bool use_dma, bool slave_mode)
64e36824 527{
2410d6a3 528 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
02621799
JF		 529 | CR0_BHT_8BIT << CR0_BHT_OFFSET
530 | CR0_SSD_ONE << CR0_SSD_OFFSET
531 | CR0_EM_BIG << CR0_EM_OFFSET;
65498c6a
ERB		 532 u32 cr1;
533 u32 dmacr = 0;
64e36824 534
d065f41a
CR		 535 if (slave_mode)
536 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
537 rs->slave_abort = false;
538
74b7efa8 539 cr0 |= rs->rsd << CR0_RSD_OFFSET;
fc1ad8ee 540 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
04290192
ERB		 541 if (spi->mode & SPI_LSB_FIRST)
542 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
736b81e0
JL		 543 if (spi->mode & SPI_CS_HIGH)
544 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
fc1ad8ee
ERB		 545
546 if (xfer->rx_buf && xfer->tx_buf)
547 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
548 else if (xfer->rx_buf)
549 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
01b59ce5 550 else if (use_dma)
fc1ad8ee 551 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
64e36824 552
65498c6a
ERB		 553 switch (xfer->bits_per_word) {
554 case 4:
555 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
556 cr1 = xfer->len - 1;
557 break;
558 case 8:
559 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
560 cr1 = xfer->len - 1;
561 break;
562 case 16:
563 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
564 cr1 = xfer->len / 2 - 1;
565 break;
566 default:
567 /* we only whitelist 4, 8 and 16 bit words in
d66571a2 568 * ctlr->bits_per_word_mask, so this shouldn't
65498c6a
ERB		 569 * happen
570 */
e5098952
AB		 571 dev_err(rs->dev, "unknown bits per word: %d\n",
572 xfer->bits_per_word);
573 return -EINVAL;
65498c6a
ERB		 574 }
575
eff0275e 576 if (use_dma) {
fc1ad8ee 577 if (xfer->tx_buf)
64e36824 578 dmacr |= TF_DMA_EN;
fc1ad8ee 579 if (xfer->rx_buf)
64e36824 580 dmacr |= RF_DMA_EN;
581 }
582
64e36824 583 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
65498c6a 584 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
04b37d2d 585
01b59ce5
ERB		 586 /* unfortunately setting the fifo threshold level to generate an
587 * interrupt exactly when the fifo is full doesn't seem to work,
588 * so we need the strict inequality here
589 */
4a47fcdb
JL		 590 if ((xfer->len / rs->n_bytes) < rs->fifo_len)
591 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
01b59ce5
ERB		 592 else
593 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
64e36824 594
2758bd09 595 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
4d9ca632
JL		 596 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
597 rs->regs + ROCKCHIP_SPI_DMARDLR);
64e36824 598 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
599
420b82f8
ERB		 600 /* the hardware only supports an even clock divisor, so
601 * round divisor = spiclk / speed up to nearest even number
602 * so that the resulting speed is <= the requested speed
603 */
604 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
605 rs->regs + ROCKCHIP_SPI_BAUDR);
e5098952
AB		 606
607 return 0;
64e36824 608}
609
5185a81c
BN		 610static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
611{
612 return ROCKCHIP_SPI_MAX_TRANLEN;
613}
614
d065f41a
CR		 615static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
616{
617 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
869f2c94
JL		 618 u32 rx_fifo_left;
619 struct dma_tx_state state;
620 enum dma_status status;
621
622 /* Get current dma rx point */
623 if (atomic_read(&rs->state) & RXDMA) {
624 dmaengine_pause(ctlr->dma_rx);
625 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
626 if (status == DMA_ERROR) {
627 rs->rx = rs->xfer->rx_buf;
628 rs->xfer->len = 0;
629 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
630 for (; rx_fifo_left; rx_fifo_left--)
631 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
632 goto out;
633 } else {
634 rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
635 }
636 }
d065f41a 637
869f2c94
JL		 638 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
639 if (rs->rx) {
640 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
641 for (; rx_fifo_left; rx_fifo_left--) {
642 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
643
644 if (rs->n_bytes == 1)
645 *(u8 *)rs->rx = (u8)rxw;
646 else
647 *(u16 *)rs->rx = (u16)rxw;
648 rs->rx += rs->n_bytes;
649 }
650 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
651 }
652
653out:
80808768
JL		 654 if (atomic_read(&rs->state) & RXDMA)
655 dmaengine_terminate_sync(ctlr->dma_rx);
656 if (atomic_read(&rs->state) & TXDMA)
657 dmaengine_terminate_sync(ctlr->dma_tx);
658 atomic_set(&rs->state, 0);
659 spi_enable_chip(rs, false);
d065f41a 660 rs->slave_abort = true;
6bd2c867 661 spi_finalize_current_transfer(ctlr);
d065f41a
CR		 662
663 return 0;
664}
665
5dcc44ed 666static int rockchip_spi_transfer_one(
d66571a2 667 struct spi_controller *ctlr,
64e36824 668 struct spi_device *spi,
669 struct spi_transfer *xfer)
670{
d66571a2 671 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
e5098952 672 int ret;
eff0275e 673 bool use_dma;
64e36824 674
5457773e
TS		 675 /* Zero length transfers won't trigger an interrupt on completion */
676 if (!xfer->len) {
677 spi_finalize_current_transfer(ctlr);
678 return 1;
679 }
680
62946172
DA		 681 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
682 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
64e36824 683
684 if (!xfer->tx_buf && !xfer->rx_buf) {
685 dev_err(rs->dev, "No buffer for transfer\n");
686 return -EINVAL;
687 }
688
5185a81c
BN		 689 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
690 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
691 return -EINVAL;
692 }
693
65498c6a 694 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
869f2c94 695 rs->xfer = xfer;
d66571a2 696 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
64e36824 697
e5098952
AB		 698 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
699 if (ret)
700 return ret;
64e36824 701
eff0275e 702 if (use_dma)
d66571a2 703 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
64e36824 704
869f2c94 705 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
64e36824 706}
707
d66571a2 708static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
5dcc44ed
AK		 709 struct spi_device *spi,
710 struct spi_transfer *xfer)
64e36824 711{
d66571a2 712 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
01b59ce5 713 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
64e36824 714
01b59ce5
ERB		 715 /* if the numbor of spi words to transfer is less than the fifo
716 * length we can just fill the fifo and wait for a single irq,
717 * so don't bother setting up dma
718 */
719 return xfer->len / bytes_per_word >= rs->fifo_len;
64e36824 720}
721
3a4bf922
JL		 722static int rockchip_spi_setup(struct spi_device *spi)
723{
724 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
725 u32 cr0;
726
d5d933f0
LC		 727 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
728 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
729 return -EINVAL;
730 }
731
3a4bf922
JL		 732 pm_runtime_get_sync(rs->dev);
733
734 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
735
736 cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
737 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
738 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
739 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
740 else if (spi->chip_select <= 1)
741 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
742
743 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
744
745 pm_runtime_put(rs->dev);
746
747 return 0;
748}
749
64e36824 750static int rockchip_spi_probe(struct platform_device *pdev)
751{
43de979d 752 int ret;
64e36824 753 struct rockchip_spi *rs;
d66571a2 754 struct spi_controller *ctlr;
64e36824 755 struct resource *mem;
d065f41a 756 struct device_node *np = pdev->dev.of_node;
9382df0a 757 u32 rsd_nsecs, num_cs;
d065f41a
CR		 758 bool slave_mode;
759
760 slave_mode = of_property_read_bool(np, "spi-slave");
761
762 if (slave_mode)
763 ctlr = spi_alloc_slave(&pdev->dev,
764 sizeof(struct rockchip_spi));
765 else
766 ctlr = spi_alloc_master(&pdev->dev,
767 sizeof(struct rockchip_spi));
64e36824 768
d66571a2 769 if (!ctlr)
64e36824 770 return -ENOMEM;
5dcc44ed 771
d66571a2 772 platform_set_drvdata(pdev, ctlr);
64e36824 773
d66571a2 774 rs = spi_controller_get_devdata(ctlr);
d065f41a 775 ctlr->slave = slave_mode;
64e36824 776
777 /* Get basic io resource and map it */
778 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
779 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
780 if (IS_ERR(rs->regs)) {
64e36824 781 ret = PTR_ERR(rs->regs);
d66571a2 782 goto err_put_ctlr;
64e36824 783 }
784
785 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
786 if (IS_ERR(rs->apb_pclk)) {
787 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
788 ret = PTR_ERR(rs->apb_pclk);
d66571a2 789 goto err_put_ctlr;
64e36824 790 }
791
792 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
793 if (IS_ERR(rs->spiclk)) {
794 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
795 ret = PTR_ERR(rs->spiclk);
d66571a2 796 goto err_put_ctlr;
64e36824 797 }
798
799 ret = clk_prepare_enable(rs->apb_pclk);
43de979d 800 if (ret < 0) {
64e36824 801 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
d66571a2 802 goto err_put_ctlr;
64e36824 803 }
804
805 ret = clk_prepare_enable(rs->spiclk);
43de979d 806 if (ret < 0) {
64e36824 807 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
c351587e 808 goto err_disable_apbclk;
64e36824 809 }
810
30688e4e 811 spi_enable_chip(rs, false);
64e36824 812
01b59ce5
ERB		 813 ret = platform_get_irq(pdev, 0);
814 if (ret < 0)
815 goto err_disable_spiclk;
816
817 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
d66571a2 818 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
01b59ce5
ERB		 819 if (ret)
820 goto err_disable_spiclk;
821
64e36824 822 rs->dev = &pdev->dev;
420b82f8 823 rs->freq = clk_get_rate(rs->spiclk);
64e36824 824
76b17e6e 825 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
74b7efa8
ERB		 826 &rsd_nsecs)) {
827 /* rx sample delay is expressed in parent clock cycles (max 3) */
828 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
829 1000000000 >> 8);
830 if (!rsd) {
831 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
832 rs->freq, rsd_nsecs);
833 } else if (rsd > CR0_RSD_MAX) {
834 rsd = CR0_RSD_MAX;
835 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
836 rs->freq, rsd_nsecs,
837 CR0_RSD_MAX * 1000000000U / rs->freq);
838 }
839 rs->rsd = rsd;
840 }
76b17e6e 841
64e36824 842 rs->fifo_len = get_fifo_len(rs);
843 if (!rs->fifo_len) {
844 dev_err(&pdev->dev, "Failed to get fifo length\n");
db7e8d90 845 ret = -EINVAL;
c351587e 846 goto err_disable_spiclk;
64e36824 847 }
848
940f3bbf
AK		 849 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
850 pm_runtime_use_autosuspend(&pdev->dev);
64e36824 851 pm_runtime_set_active(&pdev->dev);
852 pm_runtime_enable(&pdev->dev);
853
d66571a2
CR		 854 ctlr->auto_runtime_pm = true;
855 ctlr->bus_num = pdev->id;
856 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
d065f41a
CR		 857 if (slave_mode) {
858 ctlr->mode_bits |= SPI_NO_CS;
859 ctlr->slave_abort = rockchip_spi_slave_abort;
860 } else {
861 ctlr->flags = SPI_MASTER_GPIO_SS;
eb1262e3
CR		 862 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
863 /*
864 * rk spi0 has two native cs, spi1..5 one cs only
865 * if num-cs is missing in the dts, default to 1
866 */
9382df0a
JL		 867 if (of_property_read_u32(np, "num-cs", &num_cs))
868 num_cs = 1;
869 ctlr->num_chipselect = num_cs;
eb1262e3 870 ctlr->use_gpio_descriptors = true;
d065f41a 871 }
d66571a2
CR		 872 ctlr->dev.of_node = pdev->dev.of_node;
873 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
874 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
875 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
876
3a4bf922 877 ctlr->setup = rockchip_spi_setup;
d66571a2
CR		 878 ctlr->set_cs = rockchip_spi_set_cs;
879 ctlr->transfer_one = rockchip_spi_transfer_one;
880 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
881 ctlr->handle_err = rockchip_spi_handle_err;
d66571a2
CR		 882
883 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
884 if (IS_ERR(ctlr->dma_tx)) {
61cadcf4 885 /* Check tx to see if we need defer probing driver */
d66571a2 886 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
61cadcf4 887 ret = -EPROBE_DEFER;
c351587e 888 goto err_disable_pm_runtime;
61cadcf4 889 }
64e36824 890 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
d66571a2 891 ctlr->dma_tx = NULL;
61cadcf4 892 }
64e36824 893
d66571a2
CR		 894 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
895 if (IS_ERR(ctlr->dma_rx)) {
896 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
e4c0e06f 897 ret = -EPROBE_DEFER;
5de7ed0c 898 goto err_free_dma_tx;
64e36824 899 }
900 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
d66571a2 901 ctlr->dma_rx = NULL;
64e36824 902 }
903
d66571a2 904 if (ctlr->dma_tx && ctlr->dma_rx) {
eee06a9e
ERB		 905 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
906 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
d66571a2 907 ctlr->can_dma = rockchip_spi_can_dma;
64e36824 908 }
909
736b81e0
JL		 910 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
911 case ROCKCHIP_SPI_VER2_TYPE2:
d5d933f0 912 rs->cs_high_supported = true;
736b81e0 913 ctlr->mode_bits |= SPI_CS_HIGH;
869f2c94
JL		 914 if (ctlr->can_dma && slave_mode)
915 rs->cs_inactive = true;
916 else
917 rs->cs_inactive = false;
736b81e0
JL		 918 break;
919 default:
869f2c94 920 rs->cs_inactive = false;
736b81e0
JL		 921 break;
922 }
923
d66571a2 924 ret = devm_spi_register_controller(&pdev->dev, ctlr);
43de979d 925 if (ret < 0) {
d66571a2 926 dev_err(&pdev->dev, "Failed to register controller\n");
c351587e 927 goto err_free_dma_rx;
64e36824 928 }
929
64e36824 930 return 0;
931
c351587e 932err_free_dma_rx:
d66571a2
CR		 933 if (ctlr->dma_rx)
934 dma_release_channel(ctlr->dma_rx);
5de7ed0c 935err_free_dma_tx:
d66571a2
CR		 936 if (ctlr->dma_tx)
937 dma_release_channel(ctlr->dma_tx);
c351587e
JC		 938err_disable_pm_runtime:
939 pm_runtime_disable(&pdev->dev);
940err_disable_spiclk:
64e36824 941 clk_disable_unprepare(rs->spiclk);
c351587e 942err_disable_apbclk:
64e36824 943 clk_disable_unprepare(rs->apb_pclk);
d66571a2
CR		 944err_put_ctlr:
945 spi_controller_put(ctlr);
64e36824 946
947 return ret;
948}
949
950static int rockchip_spi_remove(struct platform_device *pdev)
951{
d66571a2
CR		 952 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
953 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 954
6a06e895 955 pm_runtime_get_sync(&pdev->dev);
64e36824 956
957 clk_disable_unprepare(rs->spiclk);
958 clk_disable_unprepare(rs->apb_pclk);
959
6a06e895
JC		 960 pm_runtime_put_noidle(&pdev->dev);
961 pm_runtime_disable(&pdev->dev);
962 pm_runtime_set_suspended(&pdev->dev);
963
d66571a2
CR		 964 if (ctlr->dma_tx)
965 dma_release_channel(ctlr->dma_tx);
966 if (ctlr->dma_rx)
967 dma_release_channel(ctlr->dma_rx);
64e36824 968
d66571a2 969 spi_controller_put(ctlr);
844c9f47 970
64e36824 971 return 0;
972}
973
974#ifdef CONFIG_PM_SLEEP
975static int rockchip_spi_suspend(struct device *dev)
976{
43de979d 977 int ret;
d66571a2 978 struct spi_controller *ctlr = dev_get_drvdata(dev);
e882575e 979 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 980
d66571a2 981 ret = spi_controller_suspend(ctlr);
43de979d 982 if (ret < 0)
64e36824 983 return ret;
984
e882575e
X		 985 clk_disable_unprepare(rs->spiclk);
986 clk_disable_unprepare(rs->apb_pclk);
64e36824 987
23e291c2
BN		 988 pinctrl_pm_select_sleep_state(dev);
989
43de979d 990 return 0;
64e36824 991}
992
993static int rockchip_spi_resume(struct device *dev)
994{
43de979d 995 int ret;
d66571a2
CR		 996 struct spi_controller *ctlr = dev_get_drvdata(dev);
997 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 998
23e291c2
BN		 999 pinctrl_pm_select_default_state(dev);
1000
e882575e 1001 ret = clk_prepare_enable(rs->apb_pclk);
d38c4ae1
JC		 1002 if (ret < 0)
1003 return ret;
64e36824 1004
e882575e
X		 1005 ret = clk_prepare_enable(rs->spiclk);
1006 if (ret < 0)
1007 clk_disable_unprepare(rs->apb_pclk);
1008
d66571a2 1009 ret = spi_controller_resume(ctlr);
64e36824 1010 if (ret < 0) {
1011 clk_disable_unprepare(rs->spiclk);
1012 clk_disable_unprepare(rs->apb_pclk);
1013 }
1014
43de979d 1015 return 0;
64e36824 1016}
1017#endif /* CONFIG_PM_SLEEP */
1018
ec833050 1019#ifdef CONFIG_PM
64e36824 1020static int rockchip_spi_runtime_suspend(struct device *dev)
1021{
d66571a2
CR		 1022 struct spi_controller *ctlr = dev_get_drvdata(dev);
1023 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 1024
1025 clk_disable_unprepare(rs->spiclk);
1026 clk_disable_unprepare(rs->apb_pclk);
1027
1028 return 0;
1029}
1030
1031static int rockchip_spi_runtime_resume(struct device *dev)
1032{
1033 int ret;
d66571a2
CR		 1034 struct spi_controller *ctlr = dev_get_drvdata(dev);
1035 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
64e36824 1036
1037 ret = clk_prepare_enable(rs->apb_pclk);
43de979d 1038 if (ret < 0)
64e36824 1039 return ret;
1040
1041 ret = clk_prepare_enable(rs->spiclk);
43de979d 1042 if (ret < 0)
64e36824 1043 clk_disable_unprepare(rs->apb_pclk);
1044
43de979d 1045 return 0;
64e36824 1046}
ec833050 1047#endif /* CONFIG_PM */
64e36824 1048
1049static const struct dev_pm_ops rockchip_spi_pm = {
e882575e 1050 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
64e36824 1051 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1052 rockchip_spi_runtime_resume, NULL)
1053};
1054
1055static const struct of_device_id rockchip_spi_dt_match[] = {
c6486ead 1056 { .compatible = "rockchip,px30-spi", },
aa29ea3d 1057 { .compatible = "rockchip,rk3036-spi", },
64e36824 1058 { .compatible = "rockchip,rk3066-spi", },
b839b785 1059 { .compatible = "rockchip,rk3188-spi", },
aa29ea3d 1060 { .compatible = "rockchip,rk3228-spi", },
b839b785 1061 { .compatible = "rockchip,rk3288-spi", },
c6486ead
JJ		 1062 { .compatible = "rockchip,rk3308-spi", },
1063 { .compatible = "rockchip,rk3328-spi", },
aa29ea3d 1064 { .compatible = "rockchip,rk3368-spi", },
9b7a5622 1065 { .compatible = "rockchip,rk3399-spi", },
c6486ead 1066 { .compatible = "rockchip,rv1108-spi", },
0f4f58b8 1067 { .compatible = "rockchip,rv1126-spi", },
64e36824 1068 { },
1069};
1070MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1071
1072static struct platform_driver rockchip_spi_driver = {
1073 .driver = {
1074 .name = DRIVER_NAME,
64e36824 1075 .pm = &rockchip_spi_pm,
1076 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1077 },
1078 .probe = rockchip_spi_probe,
1079 .remove = rockchip_spi_remove,
1080};
1081
1082module_platform_driver(rockchip_spi_driver);
1083
5dcc44ed 1084MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
64e36824 1085MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1086MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)