[linux-2.6-block.git] / drivers / spi / spi-rb4xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPI controller driver for the Mikrotik RB4xx boards
 *
 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
 *
 * This file was based on the patches for Linux 2.6.27.39 published by
 * MikroTik for their RouterBoard 4xx series devices.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>

#include <asm/mach-ath79/ar71xx_regs.h>

struct rb4xx_spi {
	void __iomem *base;
	struct clk *clk;
};

static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
{
	return __raw_readl(rbspi->base + reg);
}

static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
{
	__raw_writel(value, rbspi->base + reg);
}

static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
{
	u32 regval;

	regval = spi_ioc;
	if (value & BIT(0))
		regval |= AR71XX_SPI_IOC_DO;

	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
}

static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
{
	int i;

	for (i = 7; i >= 0; i--)
		do_spi_clk(rbspi, spi_ioc, byte >> i);
}

/* The CS2 pin is used to clock in a second bit per clock cycle. */
static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
				   u8 value)
{
	u32 regval;

	regval = spi_ioc;
	if (value & BIT(1))
		regval |= AR71XX_SPI_IOC_DO;
	if (value & BIT(0))
		regval |= AR71XX_SPI_IOC_CS2;

	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
}

/* Two bits at a time, msb first */
static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
{
	do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
	do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
	do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
	do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
}

static void rb4xx_set_cs(struct spi_device *spi, bool enable)
{
	struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);

	/*
	 * Setting CS is done along with bitbanging the actual values,
	 * since it's all on the same hardware register. However the
	 * CPLD needs CS deselected after every command.
	 */
	if (enable)
		rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
			    AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
}

static int rb4xx_transfer_one(struct spi_master *master,
			      struct spi_device *spi, struct spi_transfer *t)
{
	struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
	int i;
	u32 spi_ioc;
	u8 *rx_buf;
	const u8 *tx_buf;

	/*
	 * Prime the SPI register with the SPI device selected. The m25p80 boot
	 * flash and CPLD share the CS0 pin. This works because the CPLD's
	 * command set was designed to almost not clash with that of the
	 * boot flash.
	 */
	if (spi->chip_select == 2)
		/* MMC */
		spi_ioc = AR71XX_SPI_IOC_CS0;
	else
		/* Boot flash and CPLD */
		spi_ioc = AR71XX_SPI_IOC_CS1;

	tx_buf = t->tx_buf;
	rx_buf = t->rx_buf;
	for (i = 0; i < t->len; ++i) {
		if (t->tx_nbits == SPI_NBITS_DUAL)
			/* CPLD can use two-wire transfers */
			do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
		else
			do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
		if (!rx_buf)
			continue;
		rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
	}
	spi_finalize_current_transfer(master);

	return 0;
}

static int rb4xx_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct clk *ahb_clk;
	struct rb4xx_spi *rbspi;
	struct resource *r;
	int err;
	void __iomem *spi_base;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi_base))
		return PTR_ERR(spi_base);

	master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
	if (!master)
		return -ENOMEM;

	ahb_clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(ahb_clk))
		return PTR_ERR(ahb_clk);

	master->bus_num = 0;
	master->num_chipselect = 3;
	master->mode_bits = SPI_TX_DUAL;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->flags = SPI_MASTER_MUST_TX;
	master->transfer_one = rb4xx_transfer_one;
	master->set_cs = rb4xx_set_cs;

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "failed to register SPI master\n");
		return err;
	}

	err = clk_prepare_enable(ahb_clk);
	if (err)
		return err;

	rbspi = spi_master_get_devdata(master);
	rbspi->base = spi_base;
	rbspi->clk = ahb_clk;
	platform_set_drvdata(pdev, rbspi);

	/* Enable SPI */
	rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	return 0;
}

static int rb4xx_spi_remove(struct platform_device *pdev)
{
	struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);

	clk_disable_unprepare(rbspi->clk);

	return 0;
}

static struct platform_driver rb4xx_spi_drv = {
	.probe = rb4xx_spi_probe,
	.remove = rb4xx_spi_remove,
	.driver = {
		.name = "rb4xx-spi",
	},
};

module_platform_driver(rb4xx_spi_drv);

MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
05aec357 BV	2	/*
	3	* SPI controller driver for the Mikrotik RB4xx boards
	4	*
	5	* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
	7	*
	8	* This file was based on the patches for Linux 2.6.27.39 published by
	9	* MikroTik for their RouterBoard 4xx series devices.
05aec357 BV	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/clk.h>
	16	#include <linux/spi/spi.h>
	17
	18	#include <asm/mach-ath79/ar71xx_regs.h>
	19
	20	struct rb4xx_spi {
	21	void __iomem *base;
	22	struct clk *clk;
	23	};
	24
	25	static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
	26	{
	27	return __raw_readl(rbspi->base + reg);
	28	}
	29
	30	static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
	31	{
	32	__raw_writel(value, rbspi->base + reg);
	33	}
	34
	35	static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
	36	{
	37	u32 regval;
	38
	39	regval = spi_ioc;
	40	if (value & BIT(0))
	41	regval \|= AR71XX_SPI_IOC_DO;
	42
	43	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
	44	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval \| AR71XX_SPI_IOC_CLK);
	45	}
	46
	47	static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
	48	{
	49	int i;
	50
	51	for (i = 7; i >= 0; i--)
	52	do_spi_clk(rbspi, spi_ioc, byte >> i);
	53	}
	54
	55	/* The CS2 pin is used to clock in a second bit per clock cycle. */
	56	static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
	57	u8 value)
	58	{
	59	u32 regval;
	60
	61	regval = spi_ioc;
	62	if (value & BIT(1))
	63	regval \|= AR71XX_SPI_IOC_DO;
	64	if (value & BIT(0))
	65	regval \|= AR71XX_SPI_IOC_CS2;
	66
	67	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
	68	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval \| AR71XX_SPI_IOC_CLK);
	69	}
	70
	71	/* Two bits at a time, msb first */
	72	static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
	73	{
74	do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
75	do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
76	do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
77	do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
78	}
79
80	static void rb4xx_set_cs(struct spi_device *spi, bool enable)
81	{
82	struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
83
84	/*
85	* Setting CS is done along with bitbanging the actual values,
86	* since it's all on the same hardware register. However the
87	* CPLD needs CS deselected after every command.
88	*/
4a1ae8be	89	if (enable)
05aec357 BV	90	rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
	91	AR71XX_SPI_IOC_CS0 \| AR71XX_SPI_IOC_CS1);
	92	}
	93
	94	static int rb4xx_transfer_one(struct spi_master *master,
	95	struct spi_device spi, struct spi_transfer t)
	96	{
	97	struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
	98	int i;
	99	u32 spi_ioc;
	100	u8 *rx_buf;
	101	const u8 *tx_buf;
	102
	103	/*
	104	* Prime the SPI register with the SPI device selected. The m25p80 boot
	105	* flash and CPLD share the CS0 pin. This works because the CPLD's
	106	* command set was designed to almost not clash with that of the
	107	* boot flash.
	108	*/
	109	if (spi->chip_select == 2)
	110	/* MMC */
	111	spi_ioc = AR71XX_SPI_IOC_CS0;
	112	else
	113	/* Boot flash and CPLD */
	114	spi_ioc = AR71XX_SPI_IOC_CS1;
	115
	116	tx_buf = t->tx_buf;
	117	rx_buf = t->rx_buf;
	118	for (i = 0; i < t->len; ++i) {
	119	if (t->tx_nbits == SPI_NBITS_DUAL)
	120	/* CPLD can use two-wire transfers */
	121	do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
	122	else
	123	do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
	124	if (!rx_buf)
	125	continue;
	126	rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
	127	}
	128	spi_finalize_current_transfer(master);
	129
	130	return 0;
	131	}
	132
	133	static int rb4xx_spi_probe(struct platform_device *pdev)
	134	{
	135	struct spi_master *master;
	136	struct clk *ahb_clk;
	137	struct rb4xx_spi *rbspi;
	138	struct resource *r;
	139	int err;
	140	void __iomem *spi_base;
	141
	142	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	143	spi_base = devm_ioremap_resource(&pdev->dev, r);
b2b3024c	144	if (IS_ERR(spi_base))
05aec357 BV	145	return PTR_ERR(spi_base);
	146
	147	master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
	148	if (!master)
	149	return -ENOMEM;
	150
	151	ahb_clk = devm_clk_get(&pdev->dev, "ahb");
	152	if (IS_ERR(ahb_clk))
	153	return PTR_ERR(ahb_clk);
	154
	155	master->bus_num = 0;
	156	master->num_chipselect = 3;
	157	master->mode_bits = SPI_TX_DUAL;
bed2e8f4	158	master->bits_per_word_mask = SPI_BPW_MASK(8);
05aec357 BV	159	master->flags = SPI_MASTER_MUST_TX;
	160	master->transfer_one = rb4xx_transfer_one;
	161	master->set_cs = rb4xx_set_cs;
	162
	163	err = devm_spi_register_master(&pdev->dev, master);
	164	if (err) {
	165	dev_err(&pdev->dev, "failed to register SPI master\n");
	166	return err;
	167	}
	168
	169	err = clk_prepare_enable(ahb_clk);
	170	if (err)
	171	return err;
	172
	173	rbspi = spi_master_get_devdata(master);
	174	rbspi->base = spi_base;
	175	rbspi->clk = ahb_clk;
	176	platform_set_drvdata(pdev, rbspi);
	177
	178	/* Enable SPI */
	179	rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	180
	181	return 0;
	182	}
	183
	184	static int rb4xx_spi_remove(struct platform_device *pdev)
	185	{
	186	struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
	187
	188	clk_disable_unprepare(rbspi->clk);
	189
	190	return 0;
	191	}
	192
	193	static struct platform_driver rb4xx_spi_drv = {
	194	.probe = rb4xx_spi_probe,
	195	.remove = rb4xx_spi_remove,
	196	.driver = {
	197	.name = "rb4xx-spi",
	198	},
	199	};
	200
	201	module_platform_driver(rb4xx_spi_drv);
	202
	203	MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
	204	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	205	MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
	206	MODULE_LICENSE("GPL v2");