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64ff247a II |
1 | /* |
2 | * Copyright (c) 2008-2014, The Linux foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License rev 2 and | |
6 | * only rev 2 as published by the free Software foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/spi/spi.h> | |
612762e8 AG |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/dma-mapping.h> | |
64ff247a II |
27 | |
28 | #define QUP_CONFIG 0x0000 | |
29 | #define QUP_STATE 0x0004 | |
30 | #define QUP_IO_M_MODES 0x0008 | |
31 | #define QUP_SW_RESET 0x000c | |
32 | #define QUP_OPERATIONAL 0x0018 | |
33 | #define QUP_ERROR_FLAGS 0x001c | |
34 | #define QUP_ERROR_FLAGS_EN 0x0020 | |
35 | #define QUP_OPERATIONAL_MASK 0x0028 | |
36 | #define QUP_HW_VERSION 0x0030 | |
37 | #define QUP_MX_OUTPUT_CNT 0x0100 | |
38 | #define QUP_OUTPUT_FIFO 0x0110 | |
39 | #define QUP_MX_WRITE_CNT 0x0150 | |
40 | #define QUP_MX_INPUT_CNT 0x0200 | |
41 | #define QUP_MX_READ_CNT 0x0208 | |
42 | #define QUP_INPUT_FIFO 0x0218 | |
43 | ||
44 | #define SPI_CONFIG 0x0300 | |
45 | #define SPI_IO_CONTROL 0x0304 | |
46 | #define SPI_ERROR_FLAGS 0x0308 | |
47 | #define SPI_ERROR_FLAGS_EN 0x030c | |
48 | ||
49 | /* QUP_CONFIG fields */ | |
50 | #define QUP_CONFIG_SPI_MODE (1 << 8) | |
51 | #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) | |
52 | #define QUP_CONFIG_NO_INPUT BIT(7) | |
53 | #define QUP_CONFIG_NO_OUTPUT BIT(6) | |
54 | #define QUP_CONFIG_N 0x001f | |
55 | ||
56 | /* QUP_STATE fields */ | |
57 | #define QUP_STATE_VALID BIT(2) | |
58 | #define QUP_STATE_RESET 0 | |
59 | #define QUP_STATE_RUN 1 | |
60 | #define QUP_STATE_PAUSE 3 | |
61 | #define QUP_STATE_MASK 3 | |
62 | #define QUP_STATE_CLEAR 2 | |
63 | ||
64 | #define QUP_HW_VERSION_2_1_1 0x20010001 | |
65 | ||
66 | /* QUP_IO_M_MODES fields */ | |
67 | #define QUP_IO_M_PACK_EN BIT(15) | |
68 | #define QUP_IO_M_UNPACK_EN BIT(14) | |
69 | #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12 | |
70 | #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10 | |
71 | #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT) | |
72 | #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT) | |
73 | ||
74 | #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0) | |
75 | #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2) | |
76 | #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5) | |
77 | #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7) | |
78 | ||
79 | #define QUP_IO_M_MODE_FIFO 0 | |
80 | #define QUP_IO_M_MODE_BLOCK 1 | |
81 | #define QUP_IO_M_MODE_DMOV 2 | |
82 | #define QUP_IO_M_MODE_BAM 3 | |
83 | ||
84 | /* QUP_OPERATIONAL fields */ | |
85 | #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) | |
86 | #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) | |
87 | #define QUP_OP_IN_SERVICE_FLAG BIT(9) | |
88 | #define QUP_OP_OUT_SERVICE_FLAG BIT(8) | |
89 | #define QUP_OP_IN_FIFO_FULL BIT(7) | |
90 | #define QUP_OP_OUT_FIFO_FULL BIT(6) | |
91 | #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) | |
92 | #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) | |
93 | ||
94 | /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */ | |
95 | #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) | |
96 | #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) | |
97 | #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) | |
98 | #define QUP_ERROR_INPUT_OVER_RUN BIT(2) | |
99 | ||
100 | /* SPI_CONFIG fields */ | |
101 | #define SPI_CONFIG_HS_MODE BIT(10) | |
102 | #define SPI_CONFIG_INPUT_FIRST BIT(9) | |
103 | #define SPI_CONFIG_LOOPBACK BIT(8) | |
104 | ||
105 | /* SPI_IO_CONTROL fields */ | |
106 | #define SPI_IO_C_FORCE_CS BIT(11) | |
107 | #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) | |
108 | #define SPI_IO_C_MX_CS_MODE BIT(8) | |
109 | #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) | |
110 | #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2) | |
111 | #define SPI_IO_C_CS_SELECT_MASK 0x000c | |
112 | #define SPI_IO_C_TRISTATE_CS BIT(1) | |
113 | #define SPI_IO_C_NO_TRI_STATE BIT(0) | |
114 | ||
115 | /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */ | |
116 | #define SPI_ERROR_CLK_OVER_RUN BIT(1) | |
117 | #define SPI_ERROR_CLK_UNDER_RUN BIT(0) | |
118 | ||
119 | #define SPI_NUM_CHIPSELECTS 4 | |
120 | ||
612762e8 AG |
121 | #define SPI_MAX_DMA_XFER (SZ_64K - 64) |
122 | ||
64ff247a II |
123 | /* high speed mode is when bus rate is greater then 26MHz */ |
124 | #define SPI_HS_MIN_RATE 26000000 | |
125 | #define SPI_MAX_RATE 50000000 | |
126 | ||
127 | #define SPI_DELAY_THRESHOLD 1 | |
128 | #define SPI_DELAY_RETRY 10 | |
129 | ||
64ff247a II |
130 | struct spi_qup { |
131 | void __iomem *base; | |
132 | struct device *dev; | |
133 | struct clk *cclk; /* core clock */ | |
134 | struct clk *iclk; /* interface clock */ | |
135 | int irq; | |
64ff247a II |
136 | spinlock_t lock; |
137 | ||
138 | int in_fifo_sz; | |
139 | int out_fifo_sz; | |
140 | int in_blk_sz; | |
141 | int out_blk_sz; | |
142 | ||
143 | struct spi_transfer *xfer; | |
144 | struct completion done; | |
145 | int error; | |
146 | int w_size; /* bytes per SPI word */ | |
612762e8 | 147 | int n_words; |
64ff247a II |
148 | int tx_bytes; |
149 | int rx_bytes; | |
70cea0a9 | 150 | int qup_v1; |
612762e8 | 151 | |
32ecab99 | 152 | int mode; |
612762e8 AG |
153 | struct dma_slave_config rx_conf; |
154 | struct dma_slave_config tx_conf; | |
64ff247a II |
155 | }; |
156 | ||
32ecab99 VN |
157 | static inline bool spi_qup_is_dma_xfer(int mode) |
158 | { | |
159 | if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM) | |
160 | return true; | |
161 | ||
162 | return false; | |
163 | } | |
64ff247a II |
164 | |
165 | static inline bool spi_qup_is_valid_state(struct spi_qup *controller) | |
166 | { | |
167 | u32 opstate = readl_relaxed(controller->base + QUP_STATE); | |
168 | ||
169 | return opstate & QUP_STATE_VALID; | |
170 | } | |
171 | ||
172 | static int spi_qup_set_state(struct spi_qup *controller, u32 state) | |
173 | { | |
174 | unsigned long loop; | |
175 | u32 cur_state; | |
176 | ||
177 | loop = 0; | |
178 | while (!spi_qup_is_valid_state(controller)) { | |
179 | ||
180 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
181 | ||
182 | if (++loop > SPI_DELAY_RETRY) | |
183 | return -EIO; | |
184 | } | |
185 | ||
186 | if (loop) | |
187 | dev_dbg(controller->dev, "invalid state for %ld,us %d\n", | |
188 | loop, state); | |
189 | ||
190 | cur_state = readl_relaxed(controller->base + QUP_STATE); | |
191 | /* | |
192 | * Per spec: for PAUSE_STATE to RESET_STATE, two writes | |
193 | * of (b10) are required | |
194 | */ | |
195 | if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) && | |
196 | (state == QUP_STATE_RESET)) { | |
197 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
198 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
199 | } else { | |
200 | cur_state &= ~QUP_STATE_MASK; | |
201 | cur_state |= state; | |
202 | writel_relaxed(cur_state, controller->base + QUP_STATE); | |
203 | } | |
204 | ||
205 | loop = 0; | |
206 | while (!spi_qup_is_valid_state(controller)) { | |
207 | ||
208 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
209 | ||
210 | if (++loop > SPI_DELAY_RETRY) | |
211 | return -EIO; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
64ff247a II |
217 | static void spi_qup_fifo_read(struct spi_qup *controller, |
218 | struct spi_transfer *xfer) | |
219 | { | |
220 | u8 *rx_buf = xfer->rx_buf; | |
221 | u32 word, state; | |
222 | int idx, shift, w_size; | |
223 | ||
224 | w_size = controller->w_size; | |
225 | ||
226 | while (controller->rx_bytes < xfer->len) { | |
227 | ||
228 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
229 | if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) | |
230 | break; | |
231 | ||
232 | word = readl_relaxed(controller->base + QUP_INPUT_FIFO); | |
233 | ||
234 | if (!rx_buf) { | |
235 | controller->rx_bytes += w_size; | |
236 | continue; | |
237 | } | |
238 | ||
239 | for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) { | |
240 | /* | |
241 | * The data format depends on bytes per SPI word: | |
242 | * 4 bytes: 0x12345678 | |
243 | * 2 bytes: 0x00001234 | |
244 | * 1 byte : 0x00000012 | |
245 | */ | |
246 | shift = BITS_PER_BYTE; | |
247 | shift *= (w_size - idx - 1); | |
248 | rx_buf[controller->rx_bytes] = word >> shift; | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
253 | static void spi_qup_fifo_write(struct spi_qup *controller, | |
254 | struct spi_transfer *xfer) | |
255 | { | |
256 | const u8 *tx_buf = xfer->tx_buf; | |
257 | u32 word, state, data; | |
258 | int idx, w_size; | |
259 | ||
260 | w_size = controller->w_size; | |
261 | ||
262 | while (controller->tx_bytes < xfer->len) { | |
263 | ||
264 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
265 | if (state & QUP_OP_OUT_FIFO_FULL) | |
266 | break; | |
267 | ||
268 | word = 0; | |
269 | for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) { | |
270 | ||
271 | if (!tx_buf) { | |
272 | controller->tx_bytes += w_size; | |
273 | break; | |
274 | } | |
275 | ||
276 | data = tx_buf[controller->tx_bytes]; | |
277 | word |= data << (BITS_PER_BYTE * (3 - idx)); | |
278 | } | |
279 | ||
280 | writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); | |
281 | } | |
282 | } | |
283 | ||
612762e8 AG |
284 | static void spi_qup_dma_done(void *data) |
285 | { | |
286 | struct spi_qup *qup = data; | |
287 | ||
288 | complete(&qup->done); | |
289 | } | |
290 | ||
291 | static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer, | |
292 | enum dma_transfer_direction dir, | |
293 | dma_async_tx_callback callback) | |
294 | { | |
295 | struct spi_qup *qup = spi_master_get_devdata(master); | |
296 | unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE; | |
297 | struct dma_async_tx_descriptor *desc; | |
298 | struct scatterlist *sgl; | |
299 | struct dma_chan *chan; | |
300 | dma_cookie_t cookie; | |
301 | unsigned int nents; | |
302 | ||
303 | if (dir == DMA_MEM_TO_DEV) { | |
304 | chan = master->dma_tx; | |
305 | nents = xfer->tx_sg.nents; | |
306 | sgl = xfer->tx_sg.sgl; | |
307 | } else { | |
308 | chan = master->dma_rx; | |
309 | nents = xfer->rx_sg.nents; | |
310 | sgl = xfer->rx_sg.sgl; | |
311 | } | |
312 | ||
313 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
d9a09a6c VN |
314 | if (IS_ERR_OR_NULL(desc)) |
315 | return desc ? PTR_ERR(desc) : -EINVAL; | |
612762e8 AG |
316 | |
317 | desc->callback = callback; | |
318 | desc->callback_param = qup; | |
319 | ||
320 | cookie = dmaengine_submit(desc); | |
321 | ||
322 | return dma_submit_error(cookie); | |
323 | } | |
324 | ||
325 | static void spi_qup_dma_terminate(struct spi_master *master, | |
326 | struct spi_transfer *xfer) | |
327 | { | |
328 | if (xfer->tx_buf) | |
329 | dmaengine_terminate_all(master->dma_tx); | |
330 | if (xfer->rx_buf) | |
331 | dmaengine_terminate_all(master->dma_rx); | |
332 | } | |
333 | ||
5f13fd60 VN |
334 | static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer, |
335 | unsigned long timeout) | |
612762e8 | 336 | { |
5f13fd60 | 337 | struct spi_qup *qup = spi_master_get_devdata(master); |
612762e8 AG |
338 | dma_async_tx_callback rx_done = NULL, tx_done = NULL; |
339 | int ret; | |
340 | ||
341 | if (xfer->rx_buf) | |
342 | rx_done = spi_qup_dma_done; | |
343 | else if (xfer->tx_buf) | |
344 | tx_done = spi_qup_dma_done; | |
345 | ||
ce00bab3 VN |
346 | /* before issuing the descriptors, set the QUP to run */ |
347 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); | |
348 | if (ret) { | |
349 | dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", | |
350 | __func__, __LINE__); | |
351 | return ret; | |
352 | } | |
353 | ||
612762e8 AG |
354 | if (xfer->rx_buf) { |
355 | ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done); | |
356 | if (ret) | |
357 | return ret; | |
358 | ||
359 | dma_async_issue_pending(master->dma_rx); | |
360 | } | |
361 | ||
362 | if (xfer->tx_buf) { | |
363 | ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done); | |
364 | if (ret) | |
365 | return ret; | |
366 | ||
367 | dma_async_issue_pending(master->dma_tx); | |
368 | } | |
369 | ||
5f13fd60 VN |
370 | if (!wait_for_completion_timeout(&qup->done, timeout)) |
371 | return -ETIMEDOUT; | |
372 | ||
612762e8 AG |
373 | return 0; |
374 | } | |
375 | ||
5f13fd60 VN |
376 | static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer, |
377 | unsigned long timeout) | |
612762e8 AG |
378 | { |
379 | struct spi_qup *qup = spi_master_get_devdata(master); | |
380 | int ret; | |
381 | ||
382 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); | |
383 | if (ret) { | |
384 | dev_warn(qup->dev, "cannot set RUN state\n"); | |
385 | return ret; | |
386 | } | |
387 | ||
388 | ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); | |
389 | if (ret) { | |
390 | dev_warn(qup->dev, "cannot set PAUSE state\n"); | |
391 | return ret; | |
392 | } | |
393 | ||
394 | spi_qup_fifo_write(qup, xfer); | |
395 | ||
ce00bab3 VN |
396 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); |
397 | if (ret) { | |
398 | dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", | |
399 | __func__, __LINE__); | |
400 | return ret; | |
401 | } | |
402 | ||
5f13fd60 VN |
403 | if (!wait_for_completion_timeout(&qup->done, timeout)) |
404 | return -ETIMEDOUT; | |
405 | ||
612762e8 AG |
406 | return 0; |
407 | } | |
408 | ||
64ff247a II |
409 | static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) |
410 | { | |
411 | struct spi_qup *controller = dev_id; | |
412 | struct spi_transfer *xfer; | |
413 | u32 opflags, qup_err, spi_err; | |
414 | unsigned long flags; | |
415 | int error = 0; | |
416 | ||
417 | spin_lock_irqsave(&controller->lock, flags); | |
418 | xfer = controller->xfer; | |
419 | controller->xfer = NULL; | |
420 | spin_unlock_irqrestore(&controller->lock, flags); | |
421 | ||
422 | qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); | |
423 | spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); | |
424 | opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
425 | ||
426 | writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); | |
427 | writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); | |
428 | writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); | |
429 | ||
430 | if (!xfer) { | |
8f391222 | 431 | dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n", |
64ff247a II |
432 | qup_err, spi_err, opflags); |
433 | return IRQ_HANDLED; | |
434 | } | |
435 | ||
436 | if (qup_err) { | |
437 | if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) | |
438 | dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); | |
439 | if (qup_err & QUP_ERROR_INPUT_UNDER_RUN) | |
440 | dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); | |
441 | if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN) | |
442 | dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); | |
443 | if (qup_err & QUP_ERROR_INPUT_OVER_RUN) | |
444 | dev_warn(controller->dev, "INPUT_OVER_RUN\n"); | |
445 | ||
446 | error = -EIO; | |
447 | } | |
448 | ||
449 | if (spi_err) { | |
450 | if (spi_err & SPI_ERROR_CLK_OVER_RUN) | |
451 | dev_warn(controller->dev, "CLK_OVER_RUN\n"); | |
452 | if (spi_err & SPI_ERROR_CLK_UNDER_RUN) | |
453 | dev_warn(controller->dev, "CLK_UNDER_RUN\n"); | |
454 | ||
455 | error = -EIO; | |
456 | } | |
457 | ||
32ecab99 | 458 | if (!spi_qup_is_dma_xfer(controller->mode)) { |
612762e8 AG |
459 | if (opflags & QUP_OP_IN_SERVICE_FLAG) |
460 | spi_qup_fifo_read(controller, xfer); | |
64ff247a | 461 | |
612762e8 AG |
462 | if (opflags & QUP_OP_OUT_SERVICE_FLAG) |
463 | spi_qup_fifo_write(controller, xfer); | |
464 | } | |
64ff247a II |
465 | |
466 | spin_lock_irqsave(&controller->lock, flags); | |
467 | controller->error = error; | |
468 | controller->xfer = xfer; | |
469 | spin_unlock_irqrestore(&controller->lock, flags); | |
470 | ||
471 | if (controller->rx_bytes == xfer->len || error) | |
472 | complete(&controller->done); | |
473 | ||
474 | return IRQ_HANDLED; | |
475 | } | |
476 | ||
64ff247a | 477 | /* set clock freq ... bits per word */ |
00cce74d | 478 | static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) |
64ff247a | 479 | { |
00cce74d | 480 | struct spi_qup *controller = spi_master_get_devdata(spi->master); |
32ecab99 | 481 | u32 config, iomode, control; |
612762e8 | 482 | int ret, n_words; |
64ff247a | 483 | |
00cce74d | 484 | if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { |
64ff247a II |
485 | dev_err(controller->dev, "too big size for loopback %d > %d\n", |
486 | xfer->len, controller->in_fifo_sz); | |
487 | return -EIO; | |
488 | } | |
489 | ||
490 | ret = clk_set_rate(controller->cclk, xfer->speed_hz); | |
491 | if (ret) { | |
492 | dev_err(controller->dev, "fail to set frequency %d", | |
493 | xfer->speed_hz); | |
494 | return -EIO; | |
495 | } | |
496 | ||
497 | if (spi_qup_set_state(controller, QUP_STATE_RESET)) { | |
498 | dev_err(controller->dev, "cannot set RESET state\n"); | |
499 | return -EIO; | |
500 | } | |
501 | ||
32ecab99 VN |
502 | controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); |
503 | controller->n_words = xfer->len / controller->w_size; | |
612762e8 | 504 | n_words = controller->n_words; |
64ff247a | 505 | |
32ecab99 VN |
506 | if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { |
507 | ||
508 | controller->mode = QUP_IO_M_MODE_FIFO; | |
509 | ||
64ff247a II |
510 | writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); |
511 | writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); | |
512 | /* must be zero for FIFO */ | |
513 | writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); | |
514 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); | |
32ecab99 VN |
515 | } else if (spi->master->can_dma && |
516 | spi->master->can_dma(spi->master, spi, xfer) && | |
517 | spi->master->cur_msg_mapped) { | |
518 | ||
519 | controller->mode = QUP_IO_M_MODE_BAM; | |
520 | ||
64ff247a II |
521 | writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); |
522 | writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); | |
523 | /* must be zero for BLOCK and BAM */ | |
524 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | |
525 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | |
612762e8 AG |
526 | |
527 | if (!controller->qup_v1) { | |
528 | void __iomem *input_cnt; | |
529 | ||
530 | input_cnt = controller->base + QUP_MX_INPUT_CNT; | |
531 | /* | |
532 | * for DMA transfers, both QUP_MX_INPUT_CNT and | |
533 | * QUP_MX_OUTPUT_CNT must be zero to all cases but one. | |
534 | * That case is a non-balanced transfer when there is | |
535 | * only a rx_buf. | |
536 | */ | |
537 | if (xfer->tx_buf) | |
538 | writel_relaxed(0, input_cnt); | |
539 | else | |
540 | writel_relaxed(n_words, input_cnt); | |
541 | ||
542 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); | |
543 | } | |
32ecab99 VN |
544 | } else { |
545 | ||
546 | controller->mode = QUP_IO_M_MODE_BLOCK; | |
547 | ||
548 | writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); | |
549 | writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); | |
550 | /* must be zero for BLOCK and BAM */ | |
551 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | |
552 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | |
64ff247a II |
553 | } |
554 | ||
555 | iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); | |
556 | /* Set input and output transfer mode */ | |
557 | iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); | |
612762e8 | 558 | |
32ecab99 | 559 | if (!spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
560 | iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); |
561 | else | |
562 | iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; | |
563 | ||
32ecab99 VN |
564 | iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); |
565 | iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); | |
64ff247a II |
566 | |
567 | writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); | |
568 | ||
0667dd5f II |
569 | control = readl_relaxed(controller->base + SPI_IO_CONTROL); |
570 | ||
571 | if (spi->mode & SPI_CPOL) | |
572 | control |= SPI_IO_C_CLK_IDLE_HIGH; | |
573 | else | |
574 | control &= ~SPI_IO_C_CLK_IDLE_HIGH; | |
575 | ||
576 | writel_relaxed(control, controller->base + SPI_IO_CONTROL); | |
577 | ||
64ff247a II |
578 | config = readl_relaxed(controller->base + SPI_CONFIG); |
579 | ||
00cce74d | 580 | if (spi->mode & SPI_LOOP) |
64ff247a II |
581 | config |= SPI_CONFIG_LOOPBACK; |
582 | else | |
583 | config &= ~SPI_CONFIG_LOOPBACK; | |
584 | ||
00cce74d | 585 | if (spi->mode & SPI_CPHA) |
64ff247a II |
586 | config &= ~SPI_CONFIG_INPUT_FIRST; |
587 | else | |
588 | config |= SPI_CONFIG_INPUT_FIRST; | |
589 | ||
590 | /* | |
591 | * HS_MODE improves signal stability for spi-clk high rates, | |
592 | * but is invalid in loop back mode. | |
593 | */ | |
00cce74d | 594 | if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) |
64ff247a II |
595 | config |= SPI_CONFIG_HS_MODE; |
596 | else | |
597 | config &= ~SPI_CONFIG_HS_MODE; | |
598 | ||
599 | writel_relaxed(config, controller->base + SPI_CONFIG); | |
600 | ||
601 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
602 | config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); | |
603 | config |= xfer->bits_per_word - 1; | |
604 | config |= QUP_CONFIG_SPI_MODE; | |
612762e8 | 605 | |
32ecab99 | 606 | if (spi_qup_is_dma_xfer(controller->mode)) { |
612762e8 AG |
607 | if (!xfer->tx_buf) |
608 | config |= QUP_CONFIG_NO_OUTPUT; | |
609 | if (!xfer->rx_buf) | |
610 | config |= QUP_CONFIG_NO_INPUT; | |
611 | } | |
612 | ||
64ff247a II |
613 | writel_relaxed(config, controller->base + QUP_CONFIG); |
614 | ||
70cea0a9 | 615 | /* only write to OPERATIONAL_MASK when register is present */ |
612762e8 AG |
616 | if (!controller->qup_v1) { |
617 | u32 mask = 0; | |
618 | ||
619 | /* | |
620 | * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO | |
621 | * status change in BAM mode | |
622 | */ | |
623 | ||
32ecab99 | 624 | if (spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
625 | mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG; |
626 | ||
627 | writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); | |
628 | } | |
629 | ||
64ff247a II |
630 | return 0; |
631 | } | |
632 | ||
64ff247a II |
633 | static int spi_qup_transfer_one(struct spi_master *master, |
634 | struct spi_device *spi, | |
635 | struct spi_transfer *xfer) | |
636 | { | |
637 | struct spi_qup *controller = spi_master_get_devdata(master); | |
64ff247a II |
638 | unsigned long timeout, flags; |
639 | int ret = -EIO; | |
640 | ||
00cce74d | 641 | ret = spi_qup_io_config(spi, xfer); |
64ff247a II |
642 | if (ret) |
643 | return ret; | |
644 | ||
645 | timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); | |
646 | timeout = DIV_ROUND_UP(xfer->len * 8, timeout); | |
647 | timeout = 100 * msecs_to_jiffies(timeout); | |
648 | ||
649 | reinit_completion(&controller->done); | |
650 | ||
651 | spin_lock_irqsave(&controller->lock, flags); | |
652 | controller->xfer = xfer; | |
653 | controller->error = 0; | |
654 | controller->rx_bytes = 0; | |
655 | controller->tx_bytes = 0; | |
656 | spin_unlock_irqrestore(&controller->lock, flags); | |
657 | ||
32ecab99 | 658 | if (spi_qup_is_dma_xfer(controller->mode)) |
5f13fd60 | 659 | ret = spi_qup_do_dma(master, xfer, timeout); |
612762e8 | 660 | else |
5f13fd60 | 661 | ret = spi_qup_do_pio(master, xfer, timeout); |
64ff247a | 662 | |
612762e8 | 663 | if (ret) |
64ff247a | 664 | goto exit; |
64ff247a | 665 | |
64ff247a II |
666 | exit: |
667 | spi_qup_set_state(controller, QUP_STATE_RESET); | |
668 | spin_lock_irqsave(&controller->lock, flags); | |
669 | controller->xfer = NULL; | |
670 | if (!ret) | |
671 | ret = controller->error; | |
672 | spin_unlock_irqrestore(&controller->lock, flags); | |
612762e8 | 673 | |
32ecab99 | 674 | if (ret && spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
675 | spi_qup_dma_terminate(master, xfer); |
676 | ||
677 | return ret; | |
678 | } | |
679 | ||
680 | static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi, | |
681 | struct spi_transfer *xfer) | |
682 | { | |
683 | struct spi_qup *qup = spi_master_get_devdata(master); | |
684 | size_t dma_align = dma_get_cache_alignment(); | |
32ecab99 | 685 | int n_words; |
612762e8 | 686 | |
32ecab99 VN |
687 | if (xfer->rx_buf) { |
688 | if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || | |
689 | IS_ERR_OR_NULL(master->dma_rx)) | |
690 | return false; | |
691 | if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) | |
692 | return false; | |
693 | } | |
612762e8 | 694 | |
32ecab99 VN |
695 | if (xfer->tx_buf) { |
696 | if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || | |
697 | IS_ERR_OR_NULL(master->dma_tx)) | |
698 | return false; | |
699 | if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) | |
700 | return false; | |
701 | } | |
612762e8 | 702 | |
32ecab99 VN |
703 | n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); |
704 | if (n_words <= (qup->in_fifo_sz / sizeof(u32))) | |
612762e8 AG |
705 | return false; |
706 | ||
612762e8 AG |
707 | return true; |
708 | } | |
709 | ||
710 | static void spi_qup_release_dma(struct spi_master *master) | |
711 | { | |
712 | if (!IS_ERR_OR_NULL(master->dma_rx)) | |
713 | dma_release_channel(master->dma_rx); | |
714 | if (!IS_ERR_OR_NULL(master->dma_tx)) | |
715 | dma_release_channel(master->dma_tx); | |
716 | } | |
717 | ||
718 | static int spi_qup_init_dma(struct spi_master *master, resource_size_t base) | |
719 | { | |
720 | struct spi_qup *spi = spi_master_get_devdata(master); | |
721 | struct dma_slave_config *rx_conf = &spi->rx_conf, | |
722 | *tx_conf = &spi->tx_conf; | |
723 | struct device *dev = spi->dev; | |
724 | int ret; | |
725 | ||
726 | /* allocate dma resources, if available */ | |
727 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); | |
728 | if (IS_ERR(master->dma_rx)) | |
729 | return PTR_ERR(master->dma_rx); | |
730 | ||
731 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); | |
732 | if (IS_ERR(master->dma_tx)) { | |
733 | ret = PTR_ERR(master->dma_tx); | |
734 | goto err_tx; | |
735 | } | |
736 | ||
737 | /* set DMA parameters */ | |
738 | rx_conf->direction = DMA_DEV_TO_MEM; | |
739 | rx_conf->device_fc = 1; | |
740 | rx_conf->src_addr = base + QUP_INPUT_FIFO; | |
741 | rx_conf->src_maxburst = spi->in_blk_sz; | |
742 | ||
743 | tx_conf->direction = DMA_MEM_TO_DEV; | |
744 | tx_conf->device_fc = 1; | |
745 | tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; | |
746 | tx_conf->dst_maxburst = spi->out_blk_sz; | |
747 | ||
748 | ret = dmaengine_slave_config(master->dma_rx, rx_conf); | |
749 | if (ret) { | |
750 | dev_err(dev, "failed to configure RX channel\n"); | |
751 | goto err; | |
752 | } | |
753 | ||
754 | ret = dmaengine_slave_config(master->dma_tx, tx_conf); | |
755 | if (ret) { | |
756 | dev_err(dev, "failed to configure TX channel\n"); | |
757 | goto err; | |
758 | } | |
759 | ||
760 | return 0; | |
761 | ||
762 | err: | |
763 | dma_release_channel(master->dma_tx); | |
764 | err_tx: | |
765 | dma_release_channel(master->dma_rx); | |
64ff247a II |
766 | return ret; |
767 | } | |
768 | ||
b702b9fb VN |
769 | static void spi_qup_set_cs(struct spi_device *spi, bool val) |
770 | { | |
771 | struct spi_qup *controller; | |
772 | u32 spi_ioc; | |
773 | u32 spi_ioc_orig; | |
774 | ||
775 | controller = spi_master_get_devdata(spi->master); | |
776 | spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); | |
777 | spi_ioc_orig = spi_ioc; | |
778 | if (!val) | |
779 | spi_ioc |= SPI_IO_C_FORCE_CS; | |
780 | else | |
781 | spi_ioc &= ~SPI_IO_C_FORCE_CS; | |
782 | ||
783 | if (spi_ioc != spi_ioc_orig) | |
784 | writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); | |
785 | } | |
786 | ||
64ff247a II |
787 | static int spi_qup_probe(struct platform_device *pdev) |
788 | { | |
789 | struct spi_master *master; | |
790 | struct clk *iclk, *cclk; | |
791 | struct spi_qup *controller; | |
792 | struct resource *res; | |
793 | struct device *dev; | |
794 | void __iomem *base; | |
12cb89e3 | 795 | u32 max_freq, iomode, num_cs; |
64ff247a II |
796 | int ret, irq, size; |
797 | ||
798 | dev = &pdev->dev; | |
799 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
800 | base = devm_ioremap_resource(dev, res); | |
801 | if (IS_ERR(base)) | |
802 | return PTR_ERR(base); | |
803 | ||
804 | irq = platform_get_irq(pdev, 0); | |
64ff247a II |
805 | if (irq < 0) |
806 | return irq; | |
807 | ||
808 | cclk = devm_clk_get(dev, "core"); | |
809 | if (IS_ERR(cclk)) | |
810 | return PTR_ERR(cclk); | |
811 | ||
812 | iclk = devm_clk_get(dev, "iface"); | |
813 | if (IS_ERR(iclk)) | |
814 | return PTR_ERR(iclk); | |
815 | ||
816 | /* This is optional parameter */ | |
817 | if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) | |
818 | max_freq = SPI_MAX_RATE; | |
819 | ||
820 | if (!max_freq || max_freq > SPI_MAX_RATE) { | |
821 | dev_err(dev, "invalid clock frequency %d\n", max_freq); | |
822 | return -ENXIO; | |
823 | } | |
824 | ||
825 | ret = clk_prepare_enable(cclk); | |
826 | if (ret) { | |
827 | dev_err(dev, "cannot enable core clock\n"); | |
828 | return ret; | |
829 | } | |
830 | ||
831 | ret = clk_prepare_enable(iclk); | |
832 | if (ret) { | |
833 | clk_disable_unprepare(cclk); | |
834 | dev_err(dev, "cannot enable iface clock\n"); | |
835 | return ret; | |
836 | } | |
837 | ||
64ff247a II |
838 | master = spi_alloc_master(dev, sizeof(struct spi_qup)); |
839 | if (!master) { | |
840 | clk_disable_unprepare(cclk); | |
841 | clk_disable_unprepare(iclk); | |
842 | dev_err(dev, "cannot allocate master\n"); | |
843 | return -ENOMEM; | |
844 | } | |
845 | ||
4a8573ab | 846 | /* use num-cs unless not present or out of range */ |
12cb89e3 II |
847 | if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || |
848 | num_cs > SPI_NUM_CHIPSELECTS) | |
4a8573ab | 849 | master->num_chipselect = SPI_NUM_CHIPSELECTS; |
12cb89e3 II |
850 | else |
851 | master->num_chipselect = num_cs; | |
4a8573ab | 852 | |
64ff247a II |
853 | master->bus_num = pdev->id; |
854 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
64ff247a | 855 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
cb64ca54 | 856 | master->max_speed_hz = max_freq; |
64ff247a II |
857 | master->transfer_one = spi_qup_transfer_one; |
858 | master->dev.of_node = pdev->dev.of_node; | |
859 | master->auto_runtime_pm = true; | |
612762e8 AG |
860 | master->dma_alignment = dma_get_cache_alignment(); |
861 | master->max_dma_len = SPI_MAX_DMA_XFER; | |
64ff247a II |
862 | |
863 | platform_set_drvdata(pdev, master); | |
864 | ||
865 | controller = spi_master_get_devdata(master); | |
866 | ||
867 | controller->dev = dev; | |
868 | controller->base = base; | |
869 | controller->iclk = iclk; | |
870 | controller->cclk = cclk; | |
871 | controller->irq = irq; | |
64ff247a | 872 | |
612762e8 AG |
873 | ret = spi_qup_init_dma(master, res->start); |
874 | if (ret == -EPROBE_DEFER) | |
875 | goto error; | |
876 | else if (!ret) | |
877 | master->can_dma = spi_qup_can_dma; | |
878 | ||
70cea0a9 AG |
879 | /* set v1 flag if device is version 1 */ |
880 | if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) | |
881 | controller->qup_v1 = 1; | |
882 | ||
b702b9fb VN |
883 | if (!controller->qup_v1) |
884 | master->set_cs = spi_qup_set_cs; | |
885 | ||
64ff247a II |
886 | spin_lock_init(&controller->lock); |
887 | init_completion(&controller->done); | |
888 | ||
889 | iomode = readl_relaxed(base + QUP_IO_M_MODES); | |
890 | ||
891 | size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); | |
892 | if (size) | |
893 | controller->out_blk_sz = size * 16; | |
894 | else | |
895 | controller->out_blk_sz = 4; | |
896 | ||
897 | size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); | |
898 | if (size) | |
899 | controller->in_blk_sz = size * 16; | |
900 | else | |
901 | controller->in_blk_sz = 4; | |
902 | ||
903 | size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); | |
904 | controller->out_fifo_sz = controller->out_blk_sz * (2 << size); | |
905 | ||
906 | size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); | |
907 | controller->in_fifo_sz = controller->in_blk_sz * (2 << size); | |
908 | ||
70cea0a9 AG |
909 | dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", |
910 | controller->in_blk_sz, controller->in_fifo_sz, | |
64ff247a II |
911 | controller->out_blk_sz, controller->out_fifo_sz); |
912 | ||
913 | writel_relaxed(1, base + QUP_SW_RESET); | |
914 | ||
915 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
916 | if (ret) { | |
917 | dev_err(dev, "cannot set RESET state\n"); | |
612762e8 | 918 | goto error_dma; |
64ff247a II |
919 | } |
920 | ||
921 | writel_relaxed(0, base + QUP_OPERATIONAL); | |
922 | writel_relaxed(0, base + QUP_IO_M_MODES); | |
70cea0a9 AG |
923 | |
924 | if (!controller->qup_v1) | |
925 | writel_relaxed(0, base + QUP_OPERATIONAL_MASK); | |
926 | ||
64ff247a II |
927 | writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, |
928 | base + SPI_ERROR_FLAGS_EN); | |
929 | ||
70cea0a9 AG |
930 | /* if earlier version of the QUP, disable INPUT_OVERRUN */ |
931 | if (controller->qup_v1) | |
932 | writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN | | |
933 | QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, | |
934 | base + QUP_ERROR_FLAGS_EN); | |
935 | ||
64ff247a II |
936 | writel_relaxed(0, base + SPI_CONFIG); |
937 | writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); | |
938 | ||
939 | ret = devm_request_irq(dev, irq, spi_qup_qup_irq, | |
940 | IRQF_TRIGGER_HIGH, pdev->name, controller); | |
941 | if (ret) | |
612762e8 | 942 | goto error_dma; |
64ff247a | 943 | |
64ff247a II |
944 | pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); |
945 | pm_runtime_use_autosuspend(dev); | |
946 | pm_runtime_set_active(dev); | |
947 | pm_runtime_enable(dev); | |
045c243a AG |
948 | |
949 | ret = devm_spi_register_master(dev, master); | |
950 | if (ret) | |
951 | goto disable_pm; | |
952 | ||
64ff247a II |
953 | return 0; |
954 | ||
045c243a AG |
955 | disable_pm: |
956 | pm_runtime_disable(&pdev->dev); | |
612762e8 AG |
957 | error_dma: |
958 | spi_qup_release_dma(master); | |
64ff247a II |
959 | error: |
960 | clk_disable_unprepare(cclk); | |
961 | clk_disable_unprepare(iclk); | |
962 | spi_master_put(master); | |
963 | return ret; | |
964 | } | |
965 | ||
ec833050 | 966 | #ifdef CONFIG_PM |
64ff247a II |
967 | static int spi_qup_pm_suspend_runtime(struct device *device) |
968 | { | |
969 | struct spi_master *master = dev_get_drvdata(device); | |
970 | struct spi_qup *controller = spi_master_get_devdata(master); | |
971 | u32 config; | |
972 | ||
973 | /* Enable clocks auto gaiting */ | |
974 | config = readl(controller->base + QUP_CONFIG); | |
f0ceb114 | 975 | config |= QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a | 976 | writel_relaxed(config, controller->base + QUP_CONFIG); |
dae1a770 PG |
977 | |
978 | clk_disable_unprepare(controller->cclk); | |
979 | clk_disable_unprepare(controller->iclk); | |
980 | ||
64ff247a II |
981 | return 0; |
982 | } | |
983 | ||
984 | static int spi_qup_pm_resume_runtime(struct device *device) | |
985 | { | |
986 | struct spi_master *master = dev_get_drvdata(device); | |
987 | struct spi_qup *controller = spi_master_get_devdata(master); | |
988 | u32 config; | |
dae1a770 PG |
989 | int ret; |
990 | ||
991 | ret = clk_prepare_enable(controller->iclk); | |
992 | if (ret) | |
993 | return ret; | |
994 | ||
995 | ret = clk_prepare_enable(controller->cclk); | |
996 | if (ret) | |
997 | return ret; | |
64ff247a II |
998 | |
999 | /* Disable clocks auto gaiting */ | |
1000 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
f0ceb114 | 1001 | config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a II |
1002 | writel_relaxed(config, controller->base + QUP_CONFIG); |
1003 | return 0; | |
1004 | } | |
ec833050 | 1005 | #endif /* CONFIG_PM */ |
64ff247a II |
1006 | |
1007 | #ifdef CONFIG_PM_SLEEP | |
1008 | static int spi_qup_suspend(struct device *device) | |
1009 | { | |
1010 | struct spi_master *master = dev_get_drvdata(device); | |
1011 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1012 | int ret; | |
1013 | ||
1014 | ret = spi_master_suspend(master); | |
1015 | if (ret) | |
1016 | return ret; | |
1017 | ||
1018 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1019 | if (ret) | |
1020 | return ret; | |
1021 | ||
9d04d8bc SH |
1022 | if (!pm_runtime_suspended(device)) { |
1023 | clk_disable_unprepare(controller->cclk); | |
1024 | clk_disable_unprepare(controller->iclk); | |
1025 | } | |
64ff247a II |
1026 | return 0; |
1027 | } | |
1028 | ||
1029 | static int spi_qup_resume(struct device *device) | |
1030 | { | |
1031 | struct spi_master *master = dev_get_drvdata(device); | |
1032 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1033 | int ret; | |
1034 | ||
1035 | ret = clk_prepare_enable(controller->iclk); | |
1036 | if (ret) | |
1037 | return ret; | |
1038 | ||
1039 | ret = clk_prepare_enable(controller->cclk); | |
1040 | if (ret) | |
1041 | return ret; | |
1042 | ||
1043 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1044 | if (ret) | |
1045 | return ret; | |
1046 | ||
1047 | return spi_master_resume(master); | |
1048 | } | |
1049 | #endif /* CONFIG_PM_SLEEP */ | |
1050 | ||
1051 | static int spi_qup_remove(struct platform_device *pdev) | |
1052 | { | |
1053 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | |
1054 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1055 | int ret; | |
1056 | ||
1057 | ret = pm_runtime_get_sync(&pdev->dev); | |
3d89e141 | 1058 | if (ret < 0) |
64ff247a II |
1059 | return ret; |
1060 | ||
1061 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1062 | if (ret) | |
1063 | return ret; | |
1064 | ||
612762e8 AG |
1065 | spi_qup_release_dma(master); |
1066 | ||
64ff247a II |
1067 | clk_disable_unprepare(controller->cclk); |
1068 | clk_disable_unprepare(controller->iclk); | |
1069 | ||
1070 | pm_runtime_put_noidle(&pdev->dev); | |
1071 | pm_runtime_disable(&pdev->dev); | |
d2442287 | 1072 | |
64ff247a II |
1073 | return 0; |
1074 | } | |
1075 | ||
113b1a07 | 1076 | static const struct of_device_id spi_qup_dt_match[] = { |
70cea0a9 | 1077 | { .compatible = "qcom,spi-qup-v1.1.1", }, |
64ff247a II |
1078 | { .compatible = "qcom,spi-qup-v2.1.1", }, |
1079 | { .compatible = "qcom,spi-qup-v2.2.1", }, | |
1080 | { } | |
1081 | }; | |
1082 | MODULE_DEVICE_TABLE(of, spi_qup_dt_match); | |
1083 | ||
1084 | static const struct dev_pm_ops spi_qup_dev_pm_ops = { | |
1085 | SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume) | |
1086 | SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime, | |
1087 | spi_qup_pm_resume_runtime, | |
1088 | NULL) | |
1089 | }; | |
1090 | ||
1091 | static struct platform_driver spi_qup_driver = { | |
1092 | .driver = { | |
1093 | .name = "spi_qup", | |
64ff247a II |
1094 | .pm = &spi_qup_dev_pm_ops, |
1095 | .of_match_table = spi_qup_dt_match, | |
1096 | }, | |
1097 | .probe = spi_qup_probe, | |
1098 | .remove = spi_qup_remove, | |
1099 | }; | |
1100 | module_platform_driver(spi_qup_driver); | |
1101 | ||
1102 | MODULE_LICENSE("GPL v2"); | |
64ff247a | 1103 | MODULE_ALIAS("platform:spi_qup"); |