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Merge tag 'trace-v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux...
[linux-block.git] / drivers / spi / spi-qup.c
CommitLineData
ce718dfb 1// SPDX-License-Identifier: GPL-2.0-only
64ff247a
II		 2/*
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
64ff247a
II		 4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/list.h>
12#include <linux/module.h>
13#include <linux/of.h>
4d023737 14#include <linux/of_device.h>
64ff247a
II		 15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/spi/spi.h>
612762e8
AG		 18#include <linux/dmaengine.h>
19#include <linux/dma-mapping.h>
64ff247a
II		 20
21#define QUP_CONFIG 0x0000
22#define QUP_STATE 0x0004
23#define QUP_IO_M_MODES 0x0008
24#define QUP_SW_RESET 0x000c
25#define QUP_OPERATIONAL 0x0018
26#define QUP_ERROR_FLAGS 0x001c
27#define QUP_ERROR_FLAGS_EN 0x0020
28#define QUP_OPERATIONAL_MASK 0x0028
29#define QUP_HW_VERSION 0x0030
30#define QUP_MX_OUTPUT_CNT 0x0100
31#define QUP_OUTPUT_FIFO 0x0110
32#define QUP_MX_WRITE_CNT 0x0150
33#define QUP_MX_INPUT_CNT 0x0200
34#define QUP_MX_READ_CNT 0x0208
35#define QUP_INPUT_FIFO 0x0218
36
37#define SPI_CONFIG 0x0300
38#define SPI_IO_CONTROL 0x0304
39#define SPI_ERROR_FLAGS 0x0308
40#define SPI_ERROR_FLAGS_EN 0x030c
41
42/* QUP_CONFIG fields */
43#define QUP_CONFIG_SPI_MODE (1 << 8)
44#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
45#define QUP_CONFIG_NO_INPUT BIT(7)
46#define QUP_CONFIG_NO_OUTPUT BIT(6)
47#define QUP_CONFIG_N 0x001f
48
49/* QUP_STATE fields */
50#define QUP_STATE_VALID BIT(2)
51#define QUP_STATE_RESET 0
52#define QUP_STATE_RUN 1
53#define QUP_STATE_PAUSE 3
54#define QUP_STATE_MASK 3
55#define QUP_STATE_CLEAR 2
56
57#define QUP_HW_VERSION_2_1_1 0x20010001
58
59/* QUP_IO_M_MODES fields */
60#define QUP_IO_M_PACK_EN BIT(15)
61#define QUP_IO_M_UNPACK_EN BIT(14)
62#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
63#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
64#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
65#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
66
67#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
68#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
69#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
70#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
71
72#define QUP_IO_M_MODE_FIFO 0
73#define QUP_IO_M_MODE_BLOCK 1
74#define QUP_IO_M_MODE_DMOV 2
75#define QUP_IO_M_MODE_BAM 3
76
77/* QUP_OPERATIONAL fields */
7538726f
VN		 78#define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
79#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
64ff247a
II		 80#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
81#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
82#define QUP_OP_IN_SERVICE_FLAG BIT(9)
83#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
84#define QUP_OP_IN_FIFO_FULL BIT(7)
85#define QUP_OP_OUT_FIFO_FULL BIT(6)
86#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
87#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
88
89/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
90#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
91#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
92#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
93#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
94
95/* SPI_CONFIG fields */
96#define SPI_CONFIG_HS_MODE BIT(10)
97#define SPI_CONFIG_INPUT_FIRST BIT(9)
98#define SPI_CONFIG_LOOPBACK BIT(8)
99
100/* SPI_IO_CONTROL fields */
101#define SPI_IO_C_FORCE_CS BIT(11)
102#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
103#define SPI_IO_C_MX_CS_MODE BIT(8)
104#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
105#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
106#define SPI_IO_C_CS_SELECT_MASK 0x000c
107#define SPI_IO_C_TRISTATE_CS BIT(1)
108#define SPI_IO_C_NO_TRI_STATE BIT(0)
109
110/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
111#define SPI_ERROR_CLK_OVER_RUN BIT(1)
112#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
113
114#define SPI_NUM_CHIPSELECTS 4
115
5dc47fef 116#define SPI_MAX_XFER (SZ_64K - 64)
612762e8 117
64ff247a
II		 118/* high speed mode is when bus rate is greater then 26MHz */
119#define SPI_HS_MIN_RATE 26000000
120#define SPI_MAX_RATE 50000000
121
122#define SPI_DELAY_THRESHOLD 1
123#define SPI_DELAY_RETRY 10
124
64ff247a
II		 125struct spi_qup {
126 void __iomem *base;
127 struct device *dev;
128 struct clk *cclk; /* core clock */
129 struct clk *iclk; /* interface clock */
130 int irq;
64ff247a
II		 131 spinlock_t lock;
132
133 int in_fifo_sz;
134 int out_fifo_sz;
135 int in_blk_sz;
136 int out_blk_sz;
137
138 struct spi_transfer *xfer;
139 struct completion done;
140 int error;
141 int w_size; /* bytes per SPI word */
612762e8 142 int n_words;
64ff247a
II		 143 int tx_bytes;
144 int rx_bytes;
5dc47fef
VN		 145 const u8 *tx_buf;
146 u8 *rx_buf;
70cea0a9 147 int qup_v1;
612762e8 148
32ecab99 149 int mode;
612762e8
AG		 150 struct dma_slave_config rx_conf;
151 struct dma_slave_config tx_conf;
64ff247a
II		 152};
153
3b5ea2c9
VN		 154static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
155
7538726f
VN		 156static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
157{
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
159
160 return (opflag & flag) != 0;
161}
162
32ecab99
VN		 163static inline bool spi_qup_is_dma_xfer(int mode)
164{
165 if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
166 return true;
167
168 return false;
169}
64ff247a 170
5dc47fef
VN		 171/* get's the transaction size length */
172static inline unsigned int spi_qup_len(struct spi_qup *controller)
173{
174 return controller->n_words * controller->w_size;
175}
176
64ff247a
II		 177static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
178{
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
180
181 return opstate & QUP_STATE_VALID;
182}
183
184static int spi_qup_set_state(struct spi_qup *controller, u32 state)
185{
186 unsigned long loop;
187 u32 cur_state;
188
189 loop = 0;
190 while (!spi_qup_is_valid_state(controller)) {
191
192 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
193
194 if (++loop > SPI_DELAY_RETRY)
195 return -EIO;
196 }
197
198 if (loop)
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
200 loop, state);
201
202 cur_state = readl_relaxed(controller->base + QUP_STATE);
203 /*
204 * Per spec: for PAUSE_STATE to RESET_STATE, two writes
205 * of (b10) are required
206 */
207 if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
208 (state == QUP_STATE_RESET)) {
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
211 } else {
212 cur_state &= ~QUP_STATE_MASK;
213 cur_state |= state;
214 writel_relaxed(cur_state, controller->base + QUP_STATE);
215 }
216
217 loop = 0;
218 while (!spi_qup_is_valid_state(controller)) {
219
220 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
221
222 if (++loop > SPI_DELAY_RETRY)
223 return -EIO;
224 }
225
226 return 0;
227}
228
5dc47fef 229static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
64ff247a 230{
5dc47fef 231 u8 *rx_buf = controller->rx_buf;
7538726f
VN		 232 int i, shift, num_bytes;
233 u32 word;
64ff247a 234
7538726f 235 for (; num_words; num_words--) {
64ff247a
II		 236
237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
238
5dc47fef
VN		 239 num_bytes = min_t(int, spi_qup_len(controller) -
240 controller->rx_bytes,
241 controller->w_size);
7538726f 242
64ff247a 243 if (!rx_buf) {
7538726f 244 controller->rx_bytes += num_bytes;
64ff247a
II		 245 continue;
246 }
247
7538726f 248 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
64ff247a
II		 249 /*
250 * The data format depends on bytes per SPI word:
251 * 4 bytes: 0x12345678
252 * 2 bytes: 0x00001234
253 * 1 byte : 0x00000012
254 */
255 shift = BITS_PER_BYTE;
7538726f 256 shift *= (controller->w_size - i - 1);
64ff247a
II		 257 rx_buf[controller->rx_bytes] = word >> shift;
258 }
259 }
260}
261
cd595b99 262static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
64ff247a 263{
7538726f
VN		 264 u32 remainder, words_per_block, num_words;
265 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
266
5dc47fef 267 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
7538726f
VN		 268 controller->w_size);
269 words_per_block = controller->in_blk_sz >> 2;
270
271 do {
272 /* ACK by clearing service flag */
273 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
274 controller->base + QUP_OPERATIONAL);
275
a75e91ba
JRO		 276 if (!remainder)
277 goto exit;
278
7538726f
VN		 279 if (is_block_mode) {
280 num_words = (remainder > words_per_block) ?
281 words_per_block : remainder;
282 } else {
283 if (!spi_qup_is_flag_set(controller,
284 QUP_OP_IN_FIFO_NOT_EMPTY))
285 break;
64ff247a 286
7538726f
VN		 287 num_words = 1;
288 }
64ff247a 289
7538726f 290 /* read up to the maximum transfer size available */
5dc47fef 291 spi_qup_read_from_fifo(controller, num_words);
64ff247a 292
7538726f
VN		 293 remainder -= num_words;
294
295 /* if block mode, check to see if next block is available */
296 if (is_block_mode && !spi_qup_is_flag_set(controller,
297 QUP_OP_IN_BLOCK_READ_REQ))
64ff247a
II		 298 break;
299
7538726f
VN		 300 } while (remainder);
301
302 /*
303 * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
cd595b99
VN		 304 * reads, it has to be cleared again at the very end. However, be sure
305 * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
306 * present and this is used to determine if transaction is complete
7538726f 307 */
a75e91ba
JRO		 308exit:
309 if (!remainder) {
310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
311 if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
312 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
313 controller->base + QUP_OPERATIONAL);
314 }
7538726f
VN		 315}
316
5dc47fef 317static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
7538726f 318{
5dc47fef 319 const u8 *tx_buf = controller->tx_buf;
7538726f
VN		 320 int i, num_bytes;
321 u32 word, data;
322
323 for (; num_words; num_words--) {
64ff247a 324 word = 0;
64ff247a 325
5dc47fef
VN		 326 num_bytes = min_t(int, spi_qup_len(controller) -
327 controller->tx_bytes,
328 controller->w_size);
7538726f
VN		 329 if (tx_buf)
330 for (i = 0; i < num_bytes; i++) {
331 data = tx_buf[controller->tx_bytes + i];
332 word |= data << (BITS_PER_BYTE * (3 - i));
64ff247a
II		 333 }
334
7538726f 335 controller->tx_bytes += num_bytes;
64ff247a
II		 336
337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
338 }
339}
340
612762e8
AG		 341static void spi_qup_dma_done(void *data)
342{
343 struct spi_qup *qup = data;
344
345 complete(&qup->done);
346}
347
5dc47fef 348static void spi_qup_write(struct spi_qup *controller)
7538726f
VN		 349{
350 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
351 u32 remainder, words_per_block, num_words;
352
5dc47fef 353 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
7538726f
VN		 354 controller->w_size);
355 words_per_block = controller->out_blk_sz >> 2;
356
357 do {
358 /* ACK by clearing service flag */
359 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
360 controller->base + QUP_OPERATIONAL);
361
a75e91ba
JRO		 362 /* make sure the interrupt is valid */
363 if (!remainder)
364 return;
365
7538726f
VN		 366 if (is_block_mode) {
367 num_words = (remainder > words_per_block) ?
368 words_per_block : remainder;
369 } else {
370 if (spi_qup_is_flag_set(controller,
371 QUP_OP_OUT_FIFO_FULL))
372 break;
373
374 num_words = 1;
375 }
376
5dc47fef 377 spi_qup_write_to_fifo(controller, num_words);
7538726f
VN		 378
379 remainder -= num_words;
380
381 /* if block mode, check to see if next block is available */
382 if (is_block_mode && !spi_qup_is_flag_set(controller,
383 QUP_OP_OUT_BLOCK_WRITE_REQ))
384 break;
385
386 } while (remainder);
387}
388
a841b24e
VN		 389static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
390 unsigned int nents, enum dma_transfer_direction dir,
612762e8
AG		 391 dma_async_tx_callback callback)
392{
393 struct spi_qup *qup = spi_master_get_devdata(master);
394 unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
395 struct dma_async_tx_descriptor *desc;
612762e8
AG		 396 struct dma_chan *chan;
397 dma_cookie_t cookie;
612762e8 398
a841b24e 399 if (dir == DMA_MEM_TO_DEV)
612762e8 400 chan = master->dma_tx;
a841b24e 401 else
612762e8 402 chan = master->dma_rx;
612762e8
AG		 403
404 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
d9a09a6c
VN		 405 if (IS_ERR_OR_NULL(desc))
406 return desc ? PTR_ERR(desc) : -EINVAL;
612762e8
AG		 407
408 desc->callback = callback;
409 desc->callback_param = qup;
410
411 cookie = dmaengine_submit(desc);
412
413 return dma_submit_error(cookie);
414}
415
416static void spi_qup_dma_terminate(struct spi_master *master,
417 struct spi_transfer *xfer)
418{
419 if (xfer->tx_buf)
420 dmaengine_terminate_all(master->dma_tx);
421 if (xfer->rx_buf)
422 dmaengine_terminate_all(master->dma_rx);
423}
424
5884e17e
VN		 425static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
426 u32 *nents)
427{
428 struct scatterlist *sg;
429 u32 total = 0;
430
5884e17e
VN		 431 for (sg = sgl; sg; sg = sg_next(sg)) {
432 unsigned int len = sg_dma_len(sg);
433
434 /* check for overflow as well as limit */
435 if (((total + len) < total) || ((total + len) > max))
436 break;
437
438 total += len;
439 (*nents)++;
440 }
441
442 return total;
443}
444
3b5ea2c9 445static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
5f13fd60 446 unsigned long timeout)
612762e8
AG		 447{
448 dma_async_tx_callback rx_done = NULL, tx_done = NULL;
3b5ea2c9
VN		 449 struct spi_master *master = spi->master;
450 struct spi_qup *qup = spi_master_get_devdata(master);
5884e17e 451 struct scatterlist *tx_sgl, *rx_sgl;
612762e8
AG		 452 int ret;
453
454 if (xfer->rx_buf)
455 rx_done = spi_qup_dma_done;
456 else if (xfer->tx_buf)
457 tx_done = spi_qup_dma_done;
458
5884e17e
VN		 459 rx_sgl = xfer->rx_sg.sgl;
460 tx_sgl = xfer->tx_sg.sgl;
3b5ea2c9 461
5884e17e 462 do {
6f38f125 463 u32 rx_nents = 0, tx_nents = 0;
5884e17e
VN		 464
465 if (rx_sgl)
466 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl,
467 SPI_MAX_XFER, &rx_nents) / qup->w_size;
468 if (tx_sgl)
469 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl,
470 SPI_MAX_XFER, &tx_nents) / qup->w_size;
471 if (!qup->n_words)
472 return -EIO;
ce00bab3 473
5884e17e 474 ret = spi_qup_io_config(spi, xfer);
612762e8
AG		 475 if (ret)
476 return ret;
477
5884e17e
VN		 478 /* before issuing the descriptors, set the QUP to run */
479 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
480 if (ret) {
481 dev_warn(qup->dev, "cannot set RUN state\n");
612762e8 482 return ret;
5884e17e
VN		 483 }
484 if (rx_sgl) {
485 ret = spi_qup_prep_sg(master, rx_sgl, rx_nents,
486 DMA_DEV_TO_MEM, rx_done);
487 if (ret)
488 return ret;
489 dma_async_issue_pending(master->dma_rx);
490 }
612762e8 491
5884e17e
VN		 492 if (tx_sgl) {
493 ret = spi_qup_prep_sg(master, tx_sgl, tx_nents,
494 DMA_MEM_TO_DEV, tx_done);
495 if (ret)
496 return ret;
497
498 dma_async_issue_pending(master->dma_tx);
499 }
500
501 if (!wait_for_completion_timeout(&qup->done, timeout))
502 return -ETIMEDOUT;
503
504 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
505 ;
506 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
507 ;
612762e8 508
5884e17e 509 } while (rx_sgl || tx_sgl);
5f13fd60 510
612762e8
AG		 511 return 0;
512}
513
3b5ea2c9 514static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
5f13fd60 515 unsigned long timeout)
612762e8 516{
3b5ea2c9 517 struct spi_master *master = spi->master;
612762e8 518 struct spi_qup *qup = spi_master_get_devdata(master);
5dc47fef 519 int ret, n_words, iterations, offset = 0;
612762e8 520
5dc47fef
VN		 521 n_words = qup->n_words;
522 iterations = n_words / SPI_MAX_XFER; /* round down */
523 qup->rx_buf = xfer->rx_buf;
524 qup->tx_buf = xfer->tx_buf;
3b5ea2c9 525
5dc47fef
VN		 526 do {
527 if (iterations)
528 qup->n_words = SPI_MAX_XFER;
529 else
530 qup->n_words = n_words % SPI_MAX_XFER;
612762e8 531
5dc47fef
VN		 532 if (qup->tx_buf && offset)
533 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
612762e8 534
5dc47fef
VN		 535 if (qup->rx_buf && offset)
536 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
612762e8 537
5dc47fef
VN		 538 /*
539 * if the transaction is small enough, we need
540 * to fallback to FIFO mode
541 */
542 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
543 qup->mode = QUP_IO_M_MODE_FIFO;
ce00bab3 544
5dc47fef
VN		 545 ret = spi_qup_io_config(spi, xfer);
546 if (ret)
547 return ret;
548
549 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
550 if (ret) {
551 dev_warn(qup->dev, "cannot set RUN state\n");
552 return ret;
553 }
554
555 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
556 if (ret) {
557 dev_warn(qup->dev, "cannot set PAUSE state\n");
558 return ret;
559 }
560
561 if (qup->mode == QUP_IO_M_MODE_FIFO)
562 spi_qup_write(qup);
563
564 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
565 if (ret) {
566 dev_warn(qup->dev, "cannot set RUN state\n");
567 return ret;
568 }
569
570 if (!wait_for_completion_timeout(&qup->done, timeout))
571 return -ETIMEDOUT;
572
573 offset++;
574 } while (iterations--);
5f13fd60 575
612762e8
AG		 576 return 0;
577}
578
a75e91ba
JRO		 579static bool spi_qup_data_pending(struct spi_qup *controller)
580{
581 unsigned int remainder_tx, remainder_rx;
582
583 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) -
584 controller->tx_bytes, controller->w_size);
585
586 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) -
587 controller->rx_bytes, controller->w_size);
588
589 return remainder_tx || remainder_rx;
590}
591
64ff247a
II		 592static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
593{
594 struct spi_qup *controller = dev_id;
64ff247a 595 u32 opflags, qup_err, spi_err;
64ff247a
II		 596 int error = 0;
597
64ff247a
II		 598 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
599 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
600 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
601
602 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
603 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
64ff247a
II		 604
605 if (qup_err) {
606 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
607 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
608 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
609 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
610 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
611 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
612 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
613 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
614
615 error = -EIO;
616 }
617
618 if (spi_err) {
619 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
620 dev_warn(controller->dev, "CLK_OVER_RUN\n");
621 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
622 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
623
624 error = -EIO;
625 }
626
fa0f3db4 627 spin_lock(&controller->lock);
a75e91ba
JRO		 628 if (!controller->error)
629 controller->error = error;
fa0f3db4 630 spin_unlock(&controller->lock);
a75e91ba 631
ce7dfc71
VN		 632 if (spi_qup_is_dma_xfer(controller->mode)) {
633 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
634 } else {
612762e8 635 if (opflags & QUP_OP_IN_SERVICE_FLAG)
cd595b99 636 spi_qup_read(controller, &opflags);
64ff247a 637
612762e8 638 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
5dc47fef 639 spi_qup_write(controller);
a75e91ba
JRO		 640
641 if (!spi_qup_data_pending(controller))
642 complete(&controller->done);
612762e8 643 }
64ff247a 644
a75e91ba 645 if (error)
64ff247a
II		 646 complete(&controller->done);
647
a75e91ba
JRO		 648 if (opflags & QUP_OP_MAX_INPUT_DONE_FLAG) {
649 if (!spi_qup_is_dma_xfer(controller->mode)) {
650 if (spi_qup_data_pending(controller))
651 return IRQ_HANDLED;
652 }
653 complete(&controller->done);
654 }
655
64ff247a
II		 656 return IRQ_HANDLED;
657}
658
94b9149f
VN		 659/* set clock freq ... bits per word, determine mode */
660static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
64ff247a 661{
00cce74d 662 struct spi_qup *controller = spi_master_get_devdata(spi->master);
94b9149f 663 int ret;
64ff247a 664
00cce74d 665 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
64ff247a
II		 666 dev_err(controller->dev, "too big size for loopback %d > %d\n",
667 xfer->len, controller->in_fifo_sz);
668 return -EIO;
669 }
670
671 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
672 if (ret) {
673 dev_err(controller->dev, "fail to set frequency %d",
674 xfer->speed_hz);
675 return -EIO;
676 }
677
32ecab99
VN		 678 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
679 controller->n_words = xfer->len / controller->w_size;
32ecab99 680
94b9149f 681 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
32ecab99 682 controller->mode = QUP_IO_M_MODE_FIFO;
94b9149f
VN		 683 else if (spi->master->can_dma &&
684 spi->master->can_dma(spi->master, spi, xfer) &&
685 spi->master->cur_msg_mapped)
686 controller->mode = QUP_IO_M_MODE_BAM;
687 else
688 controller->mode = QUP_IO_M_MODE_BLOCK;
689
690 return 0;
691}
692
693/* prep qup for another spi transaction of specific type */
694static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
695{
696 struct spi_qup *controller = spi_master_get_devdata(spi->master);
697 u32 config, iomode, control;
698 unsigned long flags;
32ecab99 699
94b9149f
VN		 700 spin_lock_irqsave(&controller->lock, flags);
701 controller->xfer = xfer;
702 controller->error = 0;
703 controller->rx_bytes = 0;
704 controller->tx_bytes = 0;
705 spin_unlock_irqrestore(&controller->lock, flags);
706
707
708 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
709 dev_err(controller->dev, "cannot set RESET state\n");
710 return -EIO;
711 }
712
713 switch (controller->mode) {
714 case QUP_IO_M_MODE_FIFO:
715 writel_relaxed(controller->n_words,
716 controller->base + QUP_MX_READ_CNT);
717 writel_relaxed(controller->n_words,
718 controller->base + QUP_MX_WRITE_CNT);
64ff247a
II		 719 /* must be zero for FIFO */
720 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
721 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
94b9149f
VN		 722 break;
723 case QUP_IO_M_MODE_BAM:
724 writel_relaxed(controller->n_words,
725 controller->base + QUP_MX_INPUT_CNT);
726 writel_relaxed(controller->n_words,
727 controller->base + QUP_MX_OUTPUT_CNT);
64ff247a
II		 728 /* must be zero for BLOCK and BAM */
729 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
730 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
612762e8
AG		 731
732 if (!controller->qup_v1) {
733 void __iomem *input_cnt;
734
735 input_cnt = controller->base + QUP_MX_INPUT_CNT;
736 /*
737 * for DMA transfers, both QUP_MX_INPUT_CNT and
738 * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
739 * That case is a non-balanced transfer when there is
740 * only a rx_buf.
741 */
742 if (xfer->tx_buf)
743 writel_relaxed(0, input_cnt);
744 else
94b9149f 745 writel_relaxed(controller->n_words, input_cnt);
612762e8
AG		 746
747 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
748 }
94b9149f
VN		 749 break;
750 case QUP_IO_M_MODE_BLOCK:
751 reinit_completion(&controller->done);
752 writel_relaxed(controller->n_words,
753 controller->base + QUP_MX_INPUT_CNT);
754 writel_relaxed(controller->n_words,
755 controller->base + QUP_MX_OUTPUT_CNT);
32ecab99
VN		 756 /* must be zero for BLOCK and BAM */
757 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
758 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
94b9149f
VN		 759 break;
760 default:
761 dev_err(controller->dev, "unknown mode = %d\n",
762 controller->mode);
763 return -EIO;
64ff247a
II		 764 }
765
766 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
767 /* Set input and output transfer mode */
768 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
612762e8 769
32ecab99 770 if (!spi_qup_is_dma_xfer(controller->mode))
612762e8
AG		 771 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
772 else
773 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
774
32ecab99
VN		 775 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
776 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
64ff247a
II		 777
778 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
779
0667dd5f
II		 780 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
781
782 if (spi->mode & SPI_CPOL)
783 control |= SPI_IO_C_CLK_IDLE_HIGH;
784 else
785 control &= ~SPI_IO_C_CLK_IDLE_HIGH;
786
787 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
788
64ff247a
II		 789 config = readl_relaxed(controller->base + SPI_CONFIG);
790
00cce74d 791 if (spi->mode & SPI_LOOP)
64ff247a
II		 792 config |= SPI_CONFIG_LOOPBACK;
793 else
794 config &= ~SPI_CONFIG_LOOPBACK;
795
00cce74d 796 if (spi->mode & SPI_CPHA)
64ff247a
II		 797 config &= ~SPI_CONFIG_INPUT_FIRST;
798 else
799 config |= SPI_CONFIG_INPUT_FIRST;
800
801 /*
802 * HS_MODE improves signal stability for spi-clk high rates,
803 * but is invalid in loop back mode.
804 */
00cce74d 805 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
64ff247a
II		 806 config |= SPI_CONFIG_HS_MODE;
807 else
808 config &= ~SPI_CONFIG_HS_MODE;
809
810 writel_relaxed(config, controller->base + SPI_CONFIG);
811
812 config = readl_relaxed(controller->base + QUP_CONFIG);
813 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
814 config |= xfer->bits_per_word - 1;
815 config |= QUP_CONFIG_SPI_MODE;
612762e8 816
32ecab99 817 if (spi_qup_is_dma_xfer(controller->mode)) {
612762e8
AG		 818 if (!xfer->tx_buf)
819 config |= QUP_CONFIG_NO_OUTPUT;
820 if (!xfer->rx_buf)
821 config |= QUP_CONFIG_NO_INPUT;
822 }
823
64ff247a
II		 824 writel_relaxed(config, controller->base + QUP_CONFIG);
825
70cea0a9 826 /* only write to OPERATIONAL_MASK when register is present */
612762e8
AG		 827 if (!controller->qup_v1) {
828 u32 mask = 0;
829
830 /*
831 * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
832 * status change in BAM mode
833 */
834
32ecab99 835 if (spi_qup_is_dma_xfer(controller->mode))
612762e8
AG		 836 mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
837
838 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
839 }
840
64ff247a
II		 841 return 0;
842}
843
64ff247a
II		 844static int spi_qup_transfer_one(struct spi_master *master,
845 struct spi_device *spi,
846 struct spi_transfer *xfer)
847{
848 struct spi_qup *controller = spi_master_get_devdata(master);
64ff247a 849 unsigned long timeout, flags;
4a6c7d6f 850 int ret;
64ff247a 851
94b9149f
VN		 852 ret = spi_qup_io_prep(spi, xfer);
853 if (ret)
854 return ret;
855
64ff247a 856 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
5dc47fef
VN		 857 timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
858 xfer->len) * 8, timeout);
64ff247a
II		 859 timeout = 100 * msecs_to_jiffies(timeout);
860
861 reinit_completion(&controller->done);
862
863 spin_lock_irqsave(&controller->lock, flags);
864 controller->xfer = xfer;
865 controller->error = 0;
866 controller->rx_bytes = 0;
867 controller->tx_bytes = 0;
868 spin_unlock_irqrestore(&controller->lock, flags);
869
32ecab99 870 if (spi_qup_is_dma_xfer(controller->mode))
3b5ea2c9 871 ret = spi_qup_do_dma(spi, xfer, timeout);
612762e8 872 else
3b5ea2c9 873 ret = spi_qup_do_pio(spi, xfer, timeout);
64ff247a 874
64ff247a
II		 875 spi_qup_set_state(controller, QUP_STATE_RESET);
876 spin_lock_irqsave(&controller->lock, flags);
64ff247a
II		 877 if (!ret)
878 ret = controller->error;
879 spin_unlock_irqrestore(&controller->lock, flags);
612762e8 880
32ecab99 881 if (ret && spi_qup_is_dma_xfer(controller->mode))
612762e8
AG		 882 spi_qup_dma_terminate(master, xfer);
883
884 return ret;
885}
886
887static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
888 struct spi_transfer *xfer)
889{
890 struct spi_qup *qup = spi_master_get_devdata(master);
891 size_t dma_align = dma_get_cache_alignment();
32ecab99 892 int n_words;
612762e8 893
32ecab99
VN		 894 if (xfer->rx_buf) {
895 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
896 IS_ERR_OR_NULL(master->dma_rx))
897 return false;
898 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
899 return false;
900 }
612762e8 901
32ecab99
VN		 902 if (xfer->tx_buf) {
903 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
904 IS_ERR_OR_NULL(master->dma_tx))
905 return false;
906 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
907 return false;
908 }
612762e8 909
32ecab99
VN		 910 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
911 if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
612762e8
AG		 912 return false;
913
612762e8
AG		 914 return true;
915}
916
917static void spi_qup_release_dma(struct spi_master *master)
918{
919 if (!IS_ERR_OR_NULL(master->dma_rx))
920 dma_release_channel(master->dma_rx);
921 if (!IS_ERR_OR_NULL(master->dma_tx))
922 dma_release_channel(master->dma_tx);
923}
924
925static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
926{
927 struct spi_qup *spi = spi_master_get_devdata(master);
928 struct dma_slave_config *rx_conf = &spi->rx_conf,
929 *tx_conf = &spi->tx_conf;
930 struct device *dev = spi->dev;
931 int ret;
932
933 /* allocate dma resources, if available */
194e1d4b 934 master->dma_rx = dma_request_chan(dev, "rx");
612762e8
AG		 935 if (IS_ERR(master->dma_rx))
936 return PTR_ERR(master->dma_rx);
937
194e1d4b 938 master->dma_tx = dma_request_chan(dev, "tx");
612762e8
AG		 939 if (IS_ERR(master->dma_tx)) {
940 ret = PTR_ERR(master->dma_tx);
941 goto err_tx;
942 }
943
944 /* set DMA parameters */
945 rx_conf->direction = DMA_DEV_TO_MEM;
946 rx_conf->device_fc = 1;
947 rx_conf->src_addr = base + QUP_INPUT_FIFO;
948 rx_conf->src_maxburst = spi->in_blk_sz;
949
950 tx_conf->direction = DMA_MEM_TO_DEV;
951 tx_conf->device_fc = 1;
952 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
953 tx_conf->dst_maxburst = spi->out_blk_sz;
954
955 ret = dmaengine_slave_config(master->dma_rx, rx_conf);
956 if (ret) {
957 dev_err(dev, "failed to configure RX channel\n");
958 goto err;
959 }
960
961 ret = dmaengine_slave_config(master->dma_tx, tx_conf);
962 if (ret) {
963 dev_err(dev, "failed to configure TX channel\n");
964 goto err;
965 }
966
967 return 0;
968
969err:
970 dma_release_channel(master->dma_tx);
971err_tx:
972 dma_release_channel(master->dma_rx);
64ff247a
II		 973 return ret;
974}
975
b702b9fb
VN		 976static void spi_qup_set_cs(struct spi_device *spi, bool val)
977{
978 struct spi_qup *controller;
979 u32 spi_ioc;
980 u32 spi_ioc_orig;
981
982 controller = spi_master_get_devdata(spi->master);
983 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
984 spi_ioc_orig = spi_ioc;
985 if (!val)
986 spi_ioc |= SPI_IO_C_FORCE_CS;
987 else
988 spi_ioc &= ~SPI_IO_C_FORCE_CS;
989
990 if (spi_ioc != spi_ioc_orig)
991 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
992}
993
64ff247a
II		 994static int spi_qup_probe(struct platform_device *pdev)
995{
996 struct spi_master *master;
997 struct clk *iclk, *cclk;
998 struct spi_qup *controller;
999 struct resource *res;
1000 struct device *dev;
1001 void __iomem *base;
12cb89e3 1002 u32 max_freq, iomode, num_cs;
64ff247a
II		 1003 int ret, irq, size;
1004
1005 dev = &pdev->dev;
dc2eb794 1006 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
64ff247a
II		 1007 if (IS_ERR(base))
1008 return PTR_ERR(base);
1009
1010 irq = platform_get_irq(pdev, 0);
64ff247a
II		 1011 if (irq < 0)
1012 return irq;
1013
1014 cclk = devm_clk_get(dev, "core");
1015 if (IS_ERR(cclk))
1016 return PTR_ERR(cclk);
1017
1018 iclk = devm_clk_get(dev, "iface");
1019 if (IS_ERR(iclk))
1020 return PTR_ERR(iclk);
1021
1022 /* This is optional parameter */
1023 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
1024 max_freq = SPI_MAX_RATE;
1025
1026 if (!max_freq || max_freq > SPI_MAX_RATE) {
1027 dev_err(dev, "invalid clock frequency %d\n", max_freq);
1028 return -ENXIO;
1029 }
1030
64ff247a
II		 1031 master = spi_alloc_master(dev, sizeof(struct spi_qup));
1032 if (!master) {
64ff247a
II		 1033 dev_err(dev, "cannot allocate master\n");
1034 return -ENOMEM;
1035 }
1036
4a8573ab 1037 /* use num-cs unless not present or out of range */
12cb89e3
II		 1038 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
1039 num_cs > SPI_NUM_CHIPSELECTS)
4a8573ab 1040 master->num_chipselect = SPI_NUM_CHIPSELECTS;
12cb89e3
II		 1041 else
1042 master->num_chipselect = num_cs;
4a8573ab 1043
b40af618
RM		 1044 master->use_gpio_descriptors = true;
1045 master->max_native_cs = SPI_NUM_CHIPSELECTS;
64ff247a
II		 1046 master->bus_num = pdev->id;
1047 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
64ff247a 1048 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
cb64ca54 1049 master->max_speed_hz = max_freq;
64ff247a
II		 1050 master->transfer_one = spi_qup_transfer_one;
1051 master->dev.of_node = pdev->dev.of_node;
1052 master->auto_runtime_pm = true;
612762e8 1053 master->dma_alignment = dma_get_cache_alignment();
5dc47fef 1054 master->max_dma_len = SPI_MAX_XFER;
64ff247a
II		 1055
1056 platform_set_drvdata(pdev, master);
1057
1058 controller = spi_master_get_devdata(master);
1059
1060 controller->dev = dev;
1061 controller->base = base;
1062 controller->iclk = iclk;
1063 controller->cclk = cclk;
1064 controller->irq = irq;
64ff247a 1065
612762e8
AG		 1066 ret = spi_qup_init_dma(master, res->start);
1067 if (ret == -EPROBE_DEFER)
1068 goto error;
1069 else if (!ret)
1070 master->can_dma = spi_qup_can_dma;
1071
88a19814 1072 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
70cea0a9 1073
b702b9fb
VN		 1074 if (!controller->qup_v1)
1075 master->set_cs = spi_qup_set_cs;
1076
64ff247a
II		 1077 spin_lock_init(&controller->lock);
1078 init_completion(&controller->done);
1079
0c331fd1
SG		 1080 ret = clk_prepare_enable(cclk);
1081 if (ret) {
1082 dev_err(dev, "cannot enable core clock\n");
1083 goto error_dma;
1084 }
1085
1086 ret = clk_prepare_enable(iclk);
1087 if (ret) {
1088 clk_disable_unprepare(cclk);
1089 dev_err(dev, "cannot enable iface clock\n");
1090 goto error_dma;
1091 }
1092
64ff247a
II		 1093 iomode = readl_relaxed(base + QUP_IO_M_MODES);
1094
1095 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
1096 if (size)
1097 controller->out_blk_sz = size * 16;
1098 else
1099 controller->out_blk_sz = 4;
1100
1101 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
1102 if (size)
1103 controller->in_blk_sz = size * 16;
1104 else
1105 controller->in_blk_sz = 4;
1106
1107 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
1108 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
1109
1110 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
1111 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
1112
70cea0a9
AG		 1113 dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1114 controller->in_blk_sz, controller->in_fifo_sz,
64ff247a
II		 1115 controller->out_blk_sz, controller->out_fifo_sz);
1116
1117 writel_relaxed(1, base + QUP_SW_RESET);
1118
1119 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1120 if (ret) {
1121 dev_err(dev, "cannot set RESET state\n");
0c331fd1 1122 goto error_clk;
64ff247a
II		 1123 }
1124
1125 writel_relaxed(0, base + QUP_OPERATIONAL);
1126 writel_relaxed(0, base + QUP_IO_M_MODES);
70cea0a9
AG		 1127
1128 if (!controller->qup_v1)
1129 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
1130
64ff247a
II		 1131 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
1132 base + SPI_ERROR_FLAGS_EN);
1133
70cea0a9
AG		 1134 /* if earlier version of the QUP, disable INPUT_OVERRUN */
1135 if (controller->qup_v1)
1136 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
1137 QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
1138 base + QUP_ERROR_FLAGS_EN);
1139
64ff247a
II		 1140 writel_relaxed(0, base + SPI_CONFIG);
1141 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
1142
1143 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
1144 IRQF_TRIGGER_HIGH, pdev->name, controller);
1145 if (ret)
0c331fd1 1146 goto error_clk;
64ff247a 1147
64ff247a
II		 1148 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
1149 pm_runtime_use_autosuspend(dev);
1150 pm_runtime_set_active(dev);
1151 pm_runtime_enable(dev);
045c243a
AG		 1152
1153 ret = devm_spi_register_master(dev, master);
1154 if (ret)
1155 goto disable_pm;
1156
64ff247a
II		 1157 return 0;
1158
045c243a
AG		 1159disable_pm:
1160 pm_runtime_disable(&pdev->dev);
0c331fd1
SG		 1161error_clk:
1162 clk_disable_unprepare(cclk);
1163 clk_disable_unprepare(iclk);
612762e8
AG		 1164error_dma:
1165 spi_qup_release_dma(master);
64ff247a 1166error:
64ff247a
II		 1167 spi_master_put(master);
1168 return ret;
1169}
1170
ec833050 1171#ifdef CONFIG_PM
64ff247a
II		 1172static int spi_qup_pm_suspend_runtime(struct device *device)
1173{
1174 struct spi_master *master = dev_get_drvdata(device);
1175 struct spi_qup *controller = spi_master_get_devdata(master);
1176 u32 config;
1177
1178 /* Enable clocks auto gaiting */
1179 config = readl(controller->base + QUP_CONFIG);
f0ceb114 1180 config |= QUP_CONFIG_CLOCK_AUTO_GATE;
64ff247a 1181 writel_relaxed(config, controller->base + QUP_CONFIG);
dae1a770
PG		 1182
1183 clk_disable_unprepare(controller->cclk);
1184 clk_disable_unprepare(controller->iclk);
1185
64ff247a
II		 1186 return 0;
1187}
1188
1189static int spi_qup_pm_resume_runtime(struct device *device)
1190{
1191 struct spi_master *master = dev_get_drvdata(device);
1192 struct spi_qup *controller = spi_master_get_devdata(master);
1193 u32 config;
dae1a770
PG		 1194 int ret;
1195
1196 ret = clk_prepare_enable(controller->iclk);
1197 if (ret)
1198 return ret;
1199
1200 ret = clk_prepare_enable(controller->cclk);
494a2276
XQ		 1201 if (ret) {
1202 clk_disable_unprepare(controller->iclk);
dae1a770 1203 return ret;
494a2276 1204 }
64ff247a
II		 1205
1206 /* Disable clocks auto gaiting */
1207 config = readl_relaxed(controller->base + QUP_CONFIG);
f0ceb114 1208 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
64ff247a
II		 1209 writel_relaxed(config, controller->base + QUP_CONFIG);
1210 return 0;
1211}
ec833050 1212#endif /* CONFIG_PM */
64ff247a
II		 1213
1214#ifdef CONFIG_PM_SLEEP
1215static int spi_qup_suspend(struct device *device)
1216{
1217 struct spi_master *master = dev_get_drvdata(device);
1218 struct spi_qup *controller = spi_master_get_devdata(master);
1219 int ret;
1220
136b5cd2
YS		 1221 if (pm_runtime_suspended(device)) {
1222 ret = spi_qup_pm_resume_runtime(device);
1223 if (ret)
1224 return ret;
1225 }
64ff247a
II		 1226 ret = spi_master_suspend(master);
1227 if (ret)
1228 return ret;
1229
1230 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1231 if (ret)
1232 return ret;
1233
136b5cd2
YS		 1234 clk_disable_unprepare(controller->cclk);
1235 clk_disable_unprepare(controller->iclk);
64ff247a
II		 1236 return 0;
1237}
1238
1239static int spi_qup_resume(struct device *device)
1240{
1241 struct spi_master *master = dev_get_drvdata(device);
1242 struct spi_qup *controller = spi_master_get_devdata(master);
1243 int ret;
1244
1245 ret = clk_prepare_enable(controller->iclk);
1246 if (ret)
1247 return ret;
1248
1249 ret = clk_prepare_enable(controller->cclk);
70034320
XQ		 1250 if (ret) {
1251 clk_disable_unprepare(controller->iclk);
64ff247a 1252 return ret;
70034320 1253 }
64ff247a
II		 1254
1255 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1256 if (ret)
70034320
XQ		 1257 goto disable_clk;
1258
1259 ret = spi_master_resume(master);
1260 if (ret)
1261 goto disable_clk;
64ff247a 1262
70034320
XQ		 1263 return 0;
1264
1265disable_clk:
1266 clk_disable_unprepare(controller->cclk);
1267 clk_disable_unprepare(controller->iclk);
1268 return ret;
64ff247a
II		 1269}
1270#endif /* CONFIG_PM_SLEEP */
1271
dea8e70f 1272static void spi_qup_remove(struct platform_device *pdev)
64ff247a
II		 1273{
1274 struct spi_master *master = dev_get_drvdata(&pdev->dev);
1275 struct spi_qup *controller = spi_master_get_devdata(master);
1276 int ret;
1277
61f49171 1278 ret = pm_runtime_get_sync(&pdev->dev);
64ff247a 1279
61f49171
UKK		 1280 if (ret >= 0) {
1281 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1282 if (ret)
1283 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n",
1284 ERR_PTR(ret));
64ff247a 1285
61f49171
UKK		 1286 clk_disable_unprepare(controller->cclk);
1287 clk_disable_unprepare(controller->iclk);
1288 } else {
1289 dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n",
1290 ERR_PTR(ret));
1291 }
612762e8 1292
61f49171 1293 spi_qup_release_dma(master);
64ff247a
II		 1294
1295 pm_runtime_put_noidle(&pdev->dev);
1296 pm_runtime_disable(&pdev->dev);
64ff247a
II		 1297}
1298
113b1a07 1299static const struct of_device_id spi_qup_dt_match[] = {
4d023737 1300 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
64ff247a
II		 1301 { .compatible = "qcom,spi-qup-v2.1.1", },
1302 { .compatible = "qcom,spi-qup-v2.2.1", },
1303 { }
1304};
1305MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
1306
1307static const struct dev_pm_ops spi_qup_dev_pm_ops = {
1308 SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
1309 SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
1310 spi_qup_pm_resume_runtime,
1311 NULL)
1312};
1313
1314static struct platform_driver spi_qup_driver = {
1315 .driver = {
1316 .name = "spi_qup",
64ff247a
II		 1317 .pm = &spi_qup_dev_pm_ops,
1318 .of_match_table = spi_qup_dt_match,
1319 },
1320 .probe = spi_qup_probe,
dea8e70f 1321 .remove_new = spi_qup_remove,
64ff247a
II		 1322};
1323module_platform_driver(spi_qup_driver);
1324
1325MODULE_LICENSE("GPL v2");
64ff247a 1326MODULE_ALIAS("platform:spi_qup");
Linux 6.x block layer and io_uring tree(s)