[linux-2.6-block.git] / drivers / spi / spi-pxa2xx.h

/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 * Copyright (C) 2013, Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef SPI_PXA2XX_H
#define SPI_PXA2XX_H

#include <linux/atomic.h>
#include <linux/dmaengine.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/pxa2xx_ssp.h>
#include <linux/scatterlist.h>
#include <linux/sizes.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>

struct driver_data {
	/* Driver model hookup */
	struct platform_device *pdev;

	/* SSP Info */
	struct ssp_device *ssp;

	/* SPI framework hookup */
	enum pxa_ssp_type ssp_type;
	struct spi_controller *controller;

	/* PXA hookup */
	struct pxa2xx_spi_controller *controller_info;

	/* SSP register addresses */
	void __iomem *ioaddr;
	phys_addr_t ssdr_physical;

	/* SSP masks*/
	u32 dma_cr1;
	u32 int_cr1;
	u32 clear_sr;
	u32 mask_sr;

	/* DMA engine support */
	atomic_t dma_running;

	/* Current transfer state info */
	void *tx;
	void *tx_end;
	void *rx;
	void *rx_end;
	u8 n_bytes;
	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);
	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
	void (*cs_control)(u32 command);

	void __iomem *lpss_base;

	/* GPIOs for chip selects */
	struct gpio_desc **cs_gpiods;

	/* Optional slave FIFO ready signal */
	struct gpio_desc *gpiod_ready;
};

struct chip_data {
	u32 cr1;
	u32 dds_rate;
	u32 timeout;
	u8 n_bytes;
	u32 dma_burst_size;
	u32 threshold;
	u32 dma_threshold;
	u16 lpss_rx_threshold;
	u16 lpss_tx_threshold;
	u8 enable_dma;
	union {
		struct gpio_desc *gpiod_cs;
		unsigned int frm;
	};
	int gpio_cs_inverted;
	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);
	void (*cs_control)(u32 command);
};

static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
				  unsigned reg)
{
	return __raw_readl(drv_data->ioaddr + reg);
}

static  inline void pxa2xx_spi_write(const struct driver_data *drv_data,
				     unsigned reg, u32 val)
{
	__raw_writel(val, drv_data->ioaddr + reg);
}

#define DMA_ALIGNMENT		8

static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
{
	switch (drv_data->ssp_type) {
	case PXA25x_SSP:
	case CE4100_SSP:
	case QUARK_X1000_SSP:
		return 1;
	default:
		return 0;
	}
}

static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
{
	if (drv_data->ssp_type == CE4100_SSP ||
	    drv_data->ssp_type == QUARK_X1000_SSP)
		val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;

	pxa2xx_spi_write(drv_data, SSSR, val);
}

extern int pxa2xx_spi_flush(struct driver_data *drv_data);

#define MAX_DMA_LEN		SZ_64K
#define DEFAULT_DMA_CR1		(SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)

extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
				  struct spi_transfer *xfer);
extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
						  struct spi_device *spi,
						  u8 bits_per_word,
						  u32 *burst_code,
						  u32 *threshold);

#endif /* SPI_PXA2XX_H */
Commit	Line	Data
cd7bed00 MW	1	/*
	2	* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
	3	* Copyright (C) 2013, Intel Corporation
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
	10	#ifndef SPI_PXA2XX_H
	11	#define SPI_PXA2XX_H
	12
5928808e MW	13	#include <linux/atomic.h>
5928808e MW	14	#include <linux/dmaengine.h>
cd7bed00 MW	15	#include <linux/errno.h>
	16	#include <linux/io.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/pxa2xx_ssp.h>
5928808e MW	20	#include <linux/scatterlist.h>
5928808e MW	21	#include <linux/sizes.h>
cd7bed00 MW	22	#include <linux/spi/spi.h>
	23	#include <linux/spi/pxa2xx_spi.h>
	24
	25	struct driver_data {
	26	/* Driver model hookup */
	27	struct platform_device *pdev;
	28
	29	/* SSP Info */
	30	struct ssp_device *ssp;
	31
	32	/* SPI framework hookup */
	33	enum pxa_ssp_type ssp_type;
51eea52d	34	struct spi_controller *controller;
cd7bed00 MW	35
cd7bed00 MW	36	/* PXA hookup */
51eea52d	37	struct pxa2xx_spi_controller *controller_info;
cd7bed00	38
cd7bed00 MW	39	/* SSP register addresses */
cd7bed00 MW	40	void __iomem *ioaddr;
7956fadd	41	phys_addr_t ssdr_physical;
cd7bed00 MW	42
	43	/* SSP masks*/
	44	u32 dma_cr1;
	45	u32 int_cr1;
	46	u32 clear_sr;
	47	u32 mask_sr;
	48
5928808e	49	/* DMA engine support */
5928808e MW	50	atomic_t dma_running;
5928808e MW	51
d5898e19	52	/* Current transfer state info */
cd7bed00 MW	53	void *tx;
	54	void *tx_end;
	55	void *rx;
	56	void *rx_end;
cd7bed00 MW	57	u8 n_bytes;
	58	int (write)(struct driver_data drv_data);
	59	int (read)(struct driver_data drv_data);
	60	irqreturn_t (transfer_handler)(struct driver_data drv_data);
	61	void (*cs_control)(u32 command);
a0d2642e MW	62
a0d2642e MW	63	void __iomem *lpss_base;
99f499cd MW	64
	65	/* GPIOs for chip selects */
	66	struct gpio_desc **cs_gpiods;
77d33897 LR	67
	68	/* Optional slave FIFO ready signal */
	69	struct gpio_desc *gpiod_ready;
cd7bed00 MW	70	};
	71
	72	struct chip_data {
cd7bed00	73	u32 cr1;
e5262d05	74	u32 dds_rate;
cd7bed00 MW	75	u32 timeout;
	76	u8 n_bytes;
	77	u32 dma_burst_size;
	78	u32 threshold;
	79	u32 dma_threshold;
a0d2642e MW	80	u16 lpss_rx_threshold;
a0d2642e MW	81	u16 lpss_tx_threshold;
cd7bed00	82	u8 enable_dma;
cd7bed00	83	union {
c18d925f	84	struct gpio_desc *gpiod_cs;
cd7bed00 MW	85	unsigned int frm;
	86	};
	87	int gpio_cs_inverted;
	88	int (write)(struct driver_data drv_data);
	89	int (read)(struct driver_data drv_data);
	90	void (*cs_control)(u32 command);
	91	};
	92
c039dd27 JN	93	static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
	94	unsigned reg)
	95	{
	96	return __raw_readl(drv_data->ioaddr + reg);
	97	}
	98
	99	static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
	100	unsigned reg, u32 val)
	101	{
	102	__raw_writel(val, drv_data->ioaddr + reg);
	103	}
cd7bed00	104
cd7bed00 MW	105	#define DMA_ALIGNMENT 8
	106
	107	static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
	108	{
e5262d05 WC	109	switch (drv_data->ssp_type) {
	110	case PXA25x_SSP:
	111	case CE4100_SSP:
	112	case QUARK_X1000_SSP:
cd7bed00	113	return 1;
e5262d05 WC	114	default:
	115	return 0;
	116	}
cd7bed00 MW	117	}
	118
	119	static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
	120	{
e5262d05 WC	121	if (drv_data->ssp_type == CE4100_SSP \|\|
e5262d05 WC	122	drv_data->ssp_type == QUARK_X1000_SSP)
c039dd27	123	val \|= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
cd7bed00	124
c039dd27	125	pxa2xx_spi_write(drv_data, SSSR, val);
cd7bed00 MW	126	}
	127
	128	extern int pxa2xx_spi_flush(struct driver_data *drv_data);
cd7bed00	129
5928808e MW	130	#define MAX_DMA_LEN SZ_64K
5928808e MW	131	#define DEFAULT_DMA_CR1 (SSCR1_TSRE \| SSCR1_RSRE \| SSCR1_TRAIL)
5928808e	132
cd7bed00	133	extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
d5898e19 JN	134	extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
d5898e19 JN	135	struct spi_transfer *xfer);
cd7bed00	136	extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
d5898e19	137	extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
cd7bed00 MW	138	extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
cd7bed00 MW	139	extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
cd7bed00 MW	140	extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
	141	struct spi_device *spi,
	142	u8 bits_per_word,
	143	u32 *burst_code,
	144	u32 *threshold);
cd7bed00 MW	145
cd7bed00 MW	146	#endif /* SPI_PXA2XX_H */