Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e0c9905e SS |
2 | /* |
3 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 4 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
5 | */ |
6 | ||
8b136baa | 7 | #include <linux/bitops.h> |
e0c9905e SS |
8 | #include <linux/init.h> |
9 | #include <linux/module.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/ioport.h> | |
12 | #include <linux/errno.h> | |
cbfd6a21 | 13 | #include <linux/err.h> |
e0c9905e | 14 | #include <linux/interrupt.h> |
9df461ec | 15 | #include <linux/kernel.h> |
34cadd9c | 16 | #include <linux/pci.h> |
e0c9905e | 17 | #include <linux/platform_device.h> |
8348c259 | 18 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 19 | #include <linux/spi/spi.h> |
e0c9905e | 20 | #include <linux/delay.h> |
a7bb3909 | 21 | #include <linux/gpio.h> |
089bd46d | 22 | #include <linux/gpio/consumer.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3343b7a6 | 24 | #include <linux/clk.h> |
7d94a505 | 25 | #include <linux/pm_runtime.h> |
a3496855 | 26 | #include <linux/acpi.h> |
87ae1d2d | 27 | #include <linux/of_device.h> |
e0c9905e | 28 | |
cd7bed00 | 29 | #include "spi-pxa2xx.h" |
e0c9905e SS |
30 | |
31 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 32 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 33 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 34 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 35 | |
f1f640a9 VS |
36 | #define TIMOUT_DFLT 1000 |
37 | ||
b97c74bd NF |
38 | /* |
39 | * for testing SSCR1 changes that require SSP restart, basically | |
40 | * everything except the service and interrupt enables, the pxa270 developer | |
41 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
42 | * list, but the PXA255 dev man says all bits without really meaning the | |
43 | * service and interrupt enables | |
44 | */ | |
45 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 46 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
47 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
48 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
49 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
50 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 51 | |
e5262d05 WC |
52 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
53 | | QUARK_X1000_SSCR1_EFWR \ | |
54 | | QUARK_X1000_SSCR1_RFT \ | |
55 | | QUARK_X1000_SSCR1_TFT \ | |
56 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
57 | ||
7c7289a4 AS |
58 | #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ |
59 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ | |
60 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ | |
61 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
62 | | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
64 | ||
624ea72e JN |
65 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
66 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
67 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
8b136baa JN |
68 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
69 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 70 | |
dccf7369 JN |
71 | struct lpss_config { |
72 | /* LPSS offset from drv_data->ioaddr */ | |
73 | unsigned offset; | |
74 | /* Register offsets from drv_data->lpss_base or -1 */ | |
75 | int reg_general; | |
76 | int reg_ssp; | |
77 | int reg_cs_ctrl; | |
8b136baa | 78 | int reg_capabilities; |
dccf7369 JN |
79 | /* FIFO thresholds */ |
80 | u32 rx_threshold; | |
81 | u32 tx_threshold_lo; | |
82 | u32 tx_threshold_hi; | |
c1e4a53c MW |
83 | /* Chip select control */ |
84 | unsigned cs_sel_shift; | |
85 | unsigned cs_sel_mask; | |
30f3a6ab | 86 | unsigned cs_num; |
dccf7369 JN |
87 | }; |
88 | ||
89 | /* Keep these sorted with enum pxa_ssp_type */ | |
90 | static const struct lpss_config lpss_platforms[] = { | |
91 | { /* LPSS_LPT_SSP */ | |
92 | .offset = 0x800, | |
93 | .reg_general = 0x08, | |
94 | .reg_ssp = 0x0c, | |
95 | .reg_cs_ctrl = 0x18, | |
8b136baa | 96 | .reg_capabilities = -1, |
dccf7369 JN |
97 | .rx_threshold = 64, |
98 | .tx_threshold_lo = 160, | |
99 | .tx_threshold_hi = 224, | |
100 | }, | |
101 | { /* LPSS_BYT_SSP */ | |
102 | .offset = 0x400, | |
103 | .reg_general = 0x08, | |
104 | .reg_ssp = 0x0c, | |
105 | .reg_cs_ctrl = 0x18, | |
8b136baa | 106 | .reg_capabilities = -1, |
dccf7369 JN |
107 | .rx_threshold = 64, |
108 | .tx_threshold_lo = 160, | |
109 | .tx_threshold_hi = 224, | |
110 | }, | |
30f3a6ab MW |
111 | { /* LPSS_BSW_SSP */ |
112 | .offset = 0x400, | |
113 | .reg_general = 0x08, | |
114 | .reg_ssp = 0x0c, | |
115 | .reg_cs_ctrl = 0x18, | |
116 | .reg_capabilities = -1, | |
117 | .rx_threshold = 64, | |
118 | .tx_threshold_lo = 160, | |
119 | .tx_threshold_hi = 224, | |
120 | .cs_sel_shift = 2, | |
121 | .cs_sel_mask = 1 << 2, | |
122 | .cs_num = 2, | |
123 | }, | |
34cadd9c JN |
124 | { /* LPSS_SPT_SSP */ |
125 | .offset = 0x200, | |
126 | .reg_general = -1, | |
127 | .reg_ssp = 0x20, | |
128 | .reg_cs_ctrl = 0x24, | |
66ec246e | 129 | .reg_capabilities = -1, |
34cadd9c JN |
130 | .rx_threshold = 1, |
131 | .tx_threshold_lo = 32, | |
132 | .tx_threshold_hi = 56, | |
133 | }, | |
b7c08cf8 JN |
134 | { /* LPSS_BXT_SSP */ |
135 | .offset = 0x200, | |
136 | .reg_general = -1, | |
137 | .reg_ssp = 0x20, | |
138 | .reg_cs_ctrl = 0x24, | |
139 | .reg_capabilities = 0xfc, | |
140 | .rx_threshold = 1, | |
141 | .tx_threshold_lo = 16, | |
142 | .tx_threshold_hi = 48, | |
c1e4a53c MW |
143 | .cs_sel_shift = 8, |
144 | .cs_sel_mask = 3 << 8, | |
b7c08cf8 | 145 | }, |
fc0b2acc JN |
146 | { /* LPSS_CNL_SSP */ |
147 | .offset = 0x200, | |
148 | .reg_general = -1, | |
149 | .reg_ssp = 0x20, | |
150 | .reg_cs_ctrl = 0x24, | |
151 | .reg_capabilities = 0xfc, | |
152 | .rx_threshold = 1, | |
153 | .tx_threshold_lo = 32, | |
154 | .tx_threshold_hi = 56, | |
155 | .cs_sel_shift = 8, | |
156 | .cs_sel_mask = 3 << 8, | |
157 | }, | |
dccf7369 JN |
158 | }; |
159 | ||
160 | static inline const struct lpss_config | |
161 | *lpss_get_config(const struct driver_data *drv_data) | |
162 | { | |
163 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
164 | } | |
165 | ||
a0d2642e MW |
166 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
167 | { | |
03fbf488 JN |
168 | switch (drv_data->ssp_type) { |
169 | case LPSS_LPT_SSP: | |
170 | case LPSS_BYT_SSP: | |
30f3a6ab | 171 | case LPSS_BSW_SSP: |
34cadd9c | 172 | case LPSS_SPT_SSP: |
b7c08cf8 | 173 | case LPSS_BXT_SSP: |
fc0b2acc | 174 | case LPSS_CNL_SSP: |
03fbf488 JN |
175 | return true; |
176 | default: | |
177 | return false; | |
178 | } | |
a0d2642e MW |
179 | } |
180 | ||
e5262d05 WC |
181 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
182 | { | |
183 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
184 | } | |
185 | ||
4fdb2424 WC |
186 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
187 | { | |
188 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
189 | case QUARK_X1000_SSP: |
190 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
7c7289a4 AS |
191 | case CE4100_SSP: |
192 | return CE4100_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
193 | default: |
194 | return SSCR1_CHANGE_MASK; | |
195 | } | |
196 | } | |
197 | ||
198 | static u32 | |
199 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
200 | { | |
201 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
202 | case QUARK_X1000_SSP: |
203 | return RX_THRESH_QUARK_X1000_DFLT; | |
7c7289a4 AS |
204 | case CE4100_SSP: |
205 | return RX_THRESH_CE4100_DFLT; | |
4fdb2424 WC |
206 | default: |
207 | return RX_THRESH_DFLT; | |
208 | } | |
209 | } | |
210 | ||
211 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
212 | { | |
4fdb2424 WC |
213 | u32 mask; |
214 | ||
215 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
216 | case QUARK_X1000_SSP: |
217 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
218 | break; | |
7c7289a4 AS |
219 | case CE4100_SSP: |
220 | mask = CE4100_SSSR_TFL_MASK; | |
221 | break; | |
4fdb2424 WC |
222 | default: |
223 | mask = SSSR_TFL_MASK; | |
224 | break; | |
225 | } | |
226 | ||
c039dd27 | 227 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
228 | } |
229 | ||
230 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
231 | u32 *sccr1_reg) | |
232 | { | |
233 | u32 mask; | |
234 | ||
235 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
236 | case QUARK_X1000_SSP: |
237 | mask = QUARK_X1000_SSCR1_RFT; | |
238 | break; | |
7c7289a4 AS |
239 | case CE4100_SSP: |
240 | mask = CE4100_SSCR1_RFT; | |
241 | break; | |
4fdb2424 WC |
242 | default: |
243 | mask = SSCR1_RFT; | |
244 | break; | |
245 | } | |
246 | *sccr1_reg &= ~mask; | |
247 | } | |
248 | ||
249 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
250 | u32 *sccr1_reg, u32 threshold) | |
251 | { | |
252 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
253 | case QUARK_X1000_SSP: |
254 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
255 | break; | |
7c7289a4 AS |
256 | case CE4100_SSP: |
257 | *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); | |
258 | break; | |
4fdb2424 WC |
259 | default: |
260 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
261 | break; | |
262 | } | |
263 | } | |
264 | ||
265 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
266 | u32 clk_div, u8 bits) | |
267 | { | |
268 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
269 | case QUARK_X1000_SSP: |
270 | return clk_div | |
271 | | QUARK_X1000_SSCR0_Motorola | |
272 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
273 | | SSCR0_SSE; | |
4fdb2424 WC |
274 | default: |
275 | return clk_div | |
276 | | SSCR0_Motorola | |
277 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
278 | | SSCR0_SSE | |
279 | | (bits > 16 ? SSCR0_EDSS : 0); | |
280 | } | |
281 | } | |
282 | ||
a0d2642e MW |
283 | /* |
284 | * Read and write LPSS SSP private registers. Caller must first check that | |
285 | * is_lpss_ssp() returns true before these can be called. | |
286 | */ | |
287 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
288 | { | |
289 | WARN_ON(!drv_data->lpss_base); | |
290 | return readl(drv_data->lpss_base + offset); | |
291 | } | |
292 | ||
293 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
294 | unsigned offset, u32 value) | |
295 | { | |
296 | WARN_ON(!drv_data->lpss_base); | |
297 | writel(value, drv_data->lpss_base + offset); | |
298 | } | |
299 | ||
300 | /* | |
301 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
302 | * @drv_data: pointer to the driver private data | |
303 | * | |
304 | * Perform LPSS SSP specific setup. This function must be called first if | |
305 | * one is going to use LPSS SSP private registers. | |
306 | */ | |
307 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
308 | { | |
dccf7369 JN |
309 | const struct lpss_config *config; |
310 | u32 value; | |
a0d2642e | 311 | |
dccf7369 JN |
312 | config = lpss_get_config(drv_data); |
313 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
314 | |
315 | /* Enable software chip select control */ | |
0e897218 | 316 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
317 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
318 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 319 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
320 | |
321 | /* Enable multiblock DMA transfers */ | |
51eea52d | 322 | if (drv_data->controller_info->enable_dma) { |
dccf7369 | 323 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 324 | |
82ba2c2a JN |
325 | if (config->reg_general >= 0) { |
326 | value = __lpss_ssp_read_priv(drv_data, | |
327 | config->reg_general); | |
624ea72e | 328 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
329 | __lpss_ssp_write_priv(drv_data, |
330 | config->reg_general, value); | |
331 | } | |
1de70612 | 332 | } |
a0d2642e MW |
333 | } |
334 | ||
d5898e19 | 335 | static void lpss_ssp_select_cs(struct spi_device *spi, |
c1e4a53c MW |
336 | const struct lpss_config *config) |
337 | { | |
d5898e19 JN |
338 | struct driver_data *drv_data = |
339 | spi_controller_get_devdata(spi->controller); | |
c1e4a53c MW |
340 | u32 value, cs; |
341 | ||
342 | if (!config->cs_sel_mask) | |
343 | return; | |
344 | ||
345 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
346 | ||
d5898e19 | 347 | cs = spi->chip_select; |
c1e4a53c MW |
348 | cs <<= config->cs_sel_shift; |
349 | if (cs != (value & config->cs_sel_mask)) { | |
350 | /* | |
351 | * When switching another chip select output active the | |
352 | * output must be selected first and wait 2 ssp_clk cycles | |
353 | * before changing state to active. Otherwise a short | |
354 | * glitch will occur on the previous chip select since | |
355 | * output select is latched but state control is not. | |
356 | */ | |
357 | value &= ~config->cs_sel_mask; | |
358 | value |= cs; | |
359 | __lpss_ssp_write_priv(drv_data, | |
360 | config->reg_cs_ctrl, value); | |
361 | ndelay(1000000000 / | |
51eea52d | 362 | (drv_data->controller->max_speed_hz / 2)); |
c1e4a53c MW |
363 | } |
364 | } | |
365 | ||
d5898e19 | 366 | static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) |
a0d2642e | 367 | { |
d5898e19 JN |
368 | struct driver_data *drv_data = |
369 | spi_controller_get_devdata(spi->controller); | |
dccf7369 | 370 | const struct lpss_config *config; |
c1e4a53c | 371 | u32 value; |
a0d2642e | 372 | |
dccf7369 JN |
373 | config = lpss_get_config(drv_data); |
374 | ||
c1e4a53c | 375 | if (enable) |
d5898e19 | 376 | lpss_ssp_select_cs(spi, config); |
c1e4a53c | 377 | |
dccf7369 | 378 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
c1e4a53c | 379 | if (enable) |
624ea72e | 380 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
c1e4a53c | 381 | else |
624ea72e | 382 | value |= LPSS_CS_CONTROL_CS_HIGH; |
dccf7369 | 383 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
384 | } |
385 | ||
d5898e19 | 386 | static void cs_assert(struct spi_device *spi) |
a7bb3909 | 387 | { |
d5898e19 JN |
388 | struct chip_data *chip = spi_get_ctldata(spi); |
389 | struct driver_data *drv_data = | |
390 | spi_controller_get_devdata(spi->controller); | |
a7bb3909 | 391 | |
2a8626a9 | 392 | if (drv_data->ssp_type == CE4100_SSP) { |
96579a4e | 393 | pxa2xx_spi_write(drv_data, SSSR, chip->frm); |
2a8626a9 SAS |
394 | return; |
395 | } | |
396 | ||
a7bb3909 EM |
397 | if (chip->cs_control) { |
398 | chip->cs_control(PXA2XX_CS_ASSERT); | |
399 | return; | |
400 | } | |
401 | ||
c18d925f JK |
402 | if (chip->gpiod_cs) { |
403 | gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); | |
a0d2642e MW |
404 | return; |
405 | } | |
406 | ||
7566bcc7 | 407 | if (is_lpss_ssp(drv_data)) |
d5898e19 | 408 | lpss_ssp_cs_control(spi, true); |
a7bb3909 EM |
409 | } |
410 | ||
d5898e19 | 411 | static void cs_deassert(struct spi_device *spi) |
a7bb3909 | 412 | { |
d5898e19 JN |
413 | struct chip_data *chip = spi_get_ctldata(spi); |
414 | struct driver_data *drv_data = | |
415 | spi_controller_get_devdata(spi->controller); | |
104e51af | 416 | unsigned long timeout; |
a7bb3909 | 417 | |
2a8626a9 SAS |
418 | if (drv_data->ssp_type == CE4100_SSP) |
419 | return; | |
420 | ||
104e51af JN |
421 | /* Wait until SSP becomes idle before deasserting the CS */ |
422 | timeout = jiffies + msecs_to_jiffies(10); | |
423 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && | |
424 | !time_after(jiffies, timeout)) | |
425 | cpu_relax(); | |
426 | ||
a7bb3909 | 427 | if (chip->cs_control) { |
2b2562d3 | 428 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
429 | return; |
430 | } | |
431 | ||
c18d925f JK |
432 | if (chip->gpiod_cs) { |
433 | gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); | |
a0d2642e MW |
434 | return; |
435 | } | |
436 | ||
7566bcc7 | 437 | if (is_lpss_ssp(drv_data)) |
d5898e19 JN |
438 | lpss_ssp_cs_control(spi, false); |
439 | } | |
440 | ||
441 | static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) | |
442 | { | |
443 | if (level) | |
444 | cs_deassert(spi); | |
445 | else | |
446 | cs_assert(spi); | |
a7bb3909 EM |
447 | } |
448 | ||
cd7bed00 | 449 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
450 | { |
451 | unsigned long limit = loops_per_jiffy << 1; | |
452 | ||
e0c9905e | 453 | do { |
c039dd27 JN |
454 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
455 | pxa2xx_spi_read(drv_data, SSDR); | |
456 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 457 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
458 | |
459 | return limit; | |
460 | } | |
461 | ||
8d94cc50 | 462 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 463 | { |
9708c121 | 464 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 465 | |
4fdb2424 | 466 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
467 | || (drv_data->tx == drv_data->tx_end)) |
468 | return 0; | |
469 | ||
c039dd27 | 470 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
471 | drv_data->tx += n_bytes; |
472 | ||
473 | return 1; | |
e0c9905e SS |
474 | } |
475 | ||
8d94cc50 | 476 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 477 | { |
9708c121 | 478 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 479 | |
c039dd27 JN |
480 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
481 | && (drv_data->rx < drv_data->rx_end)) { | |
482 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
483 | drv_data->rx += n_bytes; |
484 | } | |
8d94cc50 SS |
485 | |
486 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
487 | } |
488 | ||
8d94cc50 | 489 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 490 | { |
4fdb2424 | 491 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
492 | || (drv_data->tx == drv_data->tx_end)) |
493 | return 0; | |
494 | ||
c039dd27 | 495 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
496 | ++drv_data->tx; |
497 | ||
498 | return 1; | |
e0c9905e SS |
499 | } |
500 | ||
8d94cc50 | 501 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 502 | { |
c039dd27 JN |
503 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
504 | && (drv_data->rx < drv_data->rx_end)) { | |
505 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
506 | ++drv_data->rx; |
507 | } | |
8d94cc50 SS |
508 | |
509 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
510 | } |
511 | ||
8d94cc50 | 512 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 513 | { |
4fdb2424 | 514 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
515 | || (drv_data->tx == drv_data->tx_end)) |
516 | return 0; | |
517 | ||
c039dd27 | 518 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
519 | drv_data->tx += 2; |
520 | ||
521 | return 1; | |
e0c9905e SS |
522 | } |
523 | ||
8d94cc50 | 524 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 525 | { |
c039dd27 JN |
526 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
527 | && (drv_data->rx < drv_data->rx_end)) { | |
528 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
529 | drv_data->rx += 2; |
530 | } | |
8d94cc50 SS |
531 | |
532 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 533 | } |
8d94cc50 SS |
534 | |
535 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 536 | { |
4fdb2424 | 537 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
538 | || (drv_data->tx == drv_data->tx_end)) |
539 | return 0; | |
540 | ||
c039dd27 | 541 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
542 | drv_data->tx += 4; |
543 | ||
544 | return 1; | |
e0c9905e SS |
545 | } |
546 | ||
8d94cc50 | 547 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 548 | { |
c039dd27 JN |
549 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
550 | && (drv_data->rx < drv_data->rx_end)) { | |
551 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
552 | drv_data->rx += 4; |
553 | } | |
8d94cc50 SS |
554 | |
555 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
556 | } |
557 | ||
579d3bb2 SAS |
558 | static void reset_sccr1(struct driver_data *drv_data) |
559 | { | |
96579a4e | 560 | struct chip_data *chip = |
51eea52d | 561 | spi_get_ctldata(drv_data->controller->cur_msg->spi); |
579d3bb2 SAS |
562 | u32 sccr1_reg; |
563 | ||
c039dd27 | 564 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
152bc19e AS |
565 | switch (drv_data->ssp_type) { |
566 | case QUARK_X1000_SSP: | |
567 | sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; | |
568 | break; | |
7c7289a4 AS |
569 | case CE4100_SSP: |
570 | sccr1_reg &= ~CE4100_SSCR1_RFT; | |
571 | break; | |
152bc19e AS |
572 | default: |
573 | sccr1_reg &= ~SSCR1_RFT; | |
574 | break; | |
575 | } | |
579d3bb2 | 576 | sccr1_reg |= chip->threshold; |
c039dd27 | 577 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
578 | } |
579 | ||
8d94cc50 | 580 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 581 | { |
8d94cc50 | 582 | /* Stop and reset SSP */ |
2a8626a9 | 583 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 584 | reset_sccr1(drv_data); |
2a8626a9 | 585 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 586 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 587 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
588 | pxa2xx_spi_write(drv_data, SSCR0, |
589 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 590 | |
8d94cc50 | 591 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 592 | |
51eea52d LR |
593 | drv_data->controller->cur_msg->status = -EIO; |
594 | spi_finalize_current_transfer(drv_data->controller); | |
8d94cc50 | 595 | } |
5daa3ba0 | 596 | |
8d94cc50 SS |
597 | static void int_transfer_complete(struct driver_data *drv_data) |
598 | { | |
07550df0 | 599 | /* Clear and disable interrupts */ |
2a8626a9 | 600 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 601 | reset_sccr1(drv_data); |
2a8626a9 | 602 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 603 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 604 | |
51eea52d | 605 | spi_finalize_current_transfer(drv_data->controller); |
8d94cc50 | 606 | } |
e0c9905e | 607 | |
8d94cc50 SS |
608 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
609 | { | |
c039dd27 JN |
610 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
611 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 612 | |
c039dd27 | 613 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 614 | |
8d94cc50 SS |
615 | if (irq_status & SSSR_ROR) { |
616 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
617 | return IRQ_HANDLED; | |
618 | } | |
e0c9905e | 619 | |
ec93cb6f LR |
620 | if (irq_status & SSSR_TUR) { |
621 | int_error_stop(drv_data, "interrupt_transfer: fifo underrun"); | |
622 | return IRQ_HANDLED; | |
623 | } | |
624 | ||
8d94cc50 | 625 | if (irq_status & SSSR_TINT) { |
c039dd27 | 626 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
627 | if (drv_data->read(drv_data)) { |
628 | int_transfer_complete(drv_data); | |
629 | return IRQ_HANDLED; | |
630 | } | |
631 | } | |
e0c9905e | 632 | |
8d94cc50 SS |
633 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
634 | do { | |
635 | if (drv_data->read(drv_data)) { | |
636 | int_transfer_complete(drv_data); | |
637 | return IRQ_HANDLED; | |
638 | } | |
639 | } while (drv_data->write(drv_data)); | |
e0c9905e | 640 | |
8d94cc50 SS |
641 | if (drv_data->read(drv_data)) { |
642 | int_transfer_complete(drv_data); | |
643 | return IRQ_HANDLED; | |
644 | } | |
e0c9905e | 645 | |
8d94cc50 | 646 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
647 | u32 bytes_left; |
648 | u32 sccr1_reg; | |
649 | ||
c039dd27 | 650 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
651 | sccr1_reg &= ~SSCR1_TIE; |
652 | ||
653 | /* | |
654 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 655 | * remaining RX bytes. |
579d3bb2 | 656 | */ |
2a8626a9 | 657 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 658 | u32 rx_thre; |
579d3bb2 | 659 | |
4fdb2424 | 660 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
661 | |
662 | bytes_left = drv_data->rx_end - drv_data->rx; | |
663 | switch (drv_data->n_bytes) { | |
664 | case 4: | |
2c183376 GS |
665 | bytes_left >>= 2; |
666 | break; | |
579d3bb2 SAS |
667 | case 2: |
668 | bytes_left >>= 1; | |
2c183376 | 669 | break; |
8d94cc50 | 670 | } |
579d3bb2 | 671 | |
4fdb2424 WC |
672 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
673 | if (rx_thre > bytes_left) | |
674 | rx_thre = bytes_left; | |
579d3bb2 | 675 | |
4fdb2424 | 676 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 677 | } |
c039dd27 | 678 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
679 | } |
680 | ||
5daa3ba0 SS |
681 | /* We did something */ |
682 | return IRQ_HANDLED; | |
e0c9905e SS |
683 | } |
684 | ||
b0312482 JK |
685 | static void handle_bad_msg(struct driver_data *drv_data) |
686 | { | |
687 | pxa2xx_spi_write(drv_data, SSCR0, | |
688 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
689 | pxa2xx_spi_write(drv_data, SSCR1, | |
690 | pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); | |
691 | if (!pxa25x_ssp_comp(drv_data)) | |
692 | pxa2xx_spi_write(drv_data, SSTO, 0); | |
693 | write_SSSR_CS(drv_data, drv_data->clear_sr); | |
694 | ||
695 | dev_err(&drv_data->pdev->dev, | |
696 | "bad message state in interrupt handler\n"); | |
697 | } | |
698 | ||
7d12e780 | 699 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 700 | { |
c7bec5ab | 701 | struct driver_data *drv_data = dev_id; |
7d94a505 | 702 | u32 sccr1_reg; |
49cbb1e0 SAS |
703 | u32 mask = drv_data->mask_sr; |
704 | u32 status; | |
705 | ||
7d94a505 MW |
706 | /* |
707 | * The IRQ might be shared with other peripherals so we must first | |
708 | * check that are we RPM suspended or not. If we are we assume that | |
709 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
710 | * interrupt is enabled). | |
711 | */ | |
712 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
713 | return IRQ_NONE; | |
714 | ||
269e4a41 MW |
715 | /* |
716 | * If the device is not yet in RPM suspended state and we get an | |
717 | * interrupt that is meant for another device, check if status bits | |
718 | * are all set to one. That means that the device is already | |
719 | * powered off. | |
720 | */ | |
c039dd27 | 721 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
722 | if (status == ~0) |
723 | return IRQ_NONE; | |
724 | ||
c039dd27 | 725 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
726 | |
727 | /* Ignore possible writes if we don't need to write */ | |
728 | if (!(sccr1_reg & SSCR1_TIE)) | |
729 | mask &= ~SSSR_TFS; | |
730 | ||
02bc933e TJN |
731 | /* Ignore RX timeout interrupt if it is disabled */ |
732 | if (!(sccr1_reg & SSCR1_TINTE)) | |
733 | mask &= ~SSSR_TINT; | |
734 | ||
49cbb1e0 SAS |
735 | if (!(status & mask)) |
736 | return IRQ_NONE; | |
e0c9905e | 737 | |
e51e9b93 JK |
738 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); |
739 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); | |
5daa3ba0 | 740 | |
51eea52d | 741 | if (!drv_data->controller->cur_msg) { |
b0312482 | 742 | handle_bad_msg(drv_data); |
e0c9905e SS |
743 | /* Never fail */ |
744 | return IRQ_HANDLED; | |
745 | } | |
746 | ||
747 | return drv_data->transfer_handler(drv_data); | |
748 | } | |
749 | ||
e5262d05 | 750 | /* |
9df461ec AS |
751 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
752 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
753 | * | |
754 | * There are formulas to get baud rate value for given input frequency and | |
755 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
756 | * | |
757 | * Fsys = 200MHz | |
758 | * | |
759 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
760 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
761 | * | |
762 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
763 | * SCR is in range 0 .. 255 | |
764 | * | |
765 | * Divisor = 5^i * 2^j * 2 * k | |
766 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
767 | * j = [0, 23] j = 0 iff i = 1 | |
768 | * k = [1, 256] | |
769 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
770 | * | |
771 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
772 | * are: | |
773 | * Case 1: 2^n, n = [0, 23] | |
774 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
775 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
776 | * | |
777 | * In all cases the lowest possible value is better. | |
778 | * | |
779 | * The function calculates parameters for all cases and chooses the one closest | |
780 | * to the asked baud rate. | |
e5262d05 | 781 | */ |
9df461ec AS |
782 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
783 | { | |
784 | unsigned long xtal = 200000000; | |
785 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
786 | see (2) */ | |
787 | /* case 3 */ | |
788 | unsigned long fref1 = fref / 2; /* case 1 */ | |
789 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
790 | unsigned long scale; | |
791 | unsigned long q, q1, q2; | |
792 | long r, r1, r2; | |
793 | u32 mul; | |
794 | ||
795 | /* Case 1 */ | |
796 | ||
797 | /* Set initial value for DDS_CLK_RATE */ | |
798 | mul = (1 << 24) >> 1; | |
799 | ||
800 | /* Calculate initial quot */ | |
3ad48062 | 801 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
802 | |
803 | /* Scale q1 if it's too big */ | |
804 | if (q1 > 256) { | |
805 | /* Scale q1 to range [1, 512] */ | |
806 | scale = fls_long(q1 - 1); | |
807 | if (scale > 9) { | |
808 | q1 >>= scale - 9; | |
809 | mul >>= scale - 9; | |
e5262d05 | 810 | } |
9df461ec AS |
811 | |
812 | /* Round the result if we have a remainder */ | |
813 | q1 += q1 & 1; | |
814 | } | |
815 | ||
816 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
817 | scale = __ffs(q1); | |
818 | q1 >>= scale; | |
819 | mul >>= scale; | |
820 | ||
821 | /* Get the remainder */ | |
822 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
823 | ||
824 | /* Case 2 */ | |
825 | ||
3ad48062 | 826 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
827 | r2 = abs(fref2 / q2 - rate); |
828 | ||
829 | /* | |
830 | * Choose the best between two: less remainder we have the better. We | |
831 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
832 | * hold only values 0 .. 255. | |
833 | */ | |
834 | if (r2 >= r1 || q2 > 256) { | |
835 | /* case 1 is better */ | |
836 | r = r1; | |
837 | q = q1; | |
838 | } else { | |
839 | /* case 2 is better */ | |
840 | r = r2; | |
841 | q = q2; | |
842 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
843 | } |
844 | ||
3ad48062 | 845 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
846 | if (fref / rate >= 80) { |
847 | u64 fssp; | |
848 | u32 m; | |
849 | ||
850 | /* Calculate initial quot */ | |
3ad48062 | 851 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
852 | m = (1 << 24) / q1; |
853 | ||
854 | /* Get the remainder */ | |
855 | fssp = (u64)fref * m; | |
856 | do_div(fssp, 1 << 24); | |
857 | r1 = abs(fssp - rate); | |
858 | ||
859 | /* Choose this one if it suits better */ | |
860 | if (r1 < r) { | |
861 | /* case 3 is better */ | |
862 | q = 1; | |
863 | mul = m; | |
864 | } | |
865 | } | |
e5262d05 | 866 | |
9df461ec AS |
867 | *dds = mul; |
868 | return q - 1; | |
e5262d05 WC |
869 | } |
870 | ||
3343b7a6 | 871 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 872 | { |
51eea52d | 873 | unsigned long ssp_clk = drv_data->controller->max_speed_hz; |
3343b7a6 MW |
874 | const struct ssp_device *ssp = drv_data->ssp; |
875 | ||
876 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 877 | |
29f21337 FS |
878 | /* |
879 | * Calculate the divisor for the SCR (Serial Clock Rate), avoiding | |
880 | * that the SSP transmission rate can be greater than the device rate | |
881 | */ | |
2a8626a9 | 882 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
29f21337 | 883 | return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; |
2f1a74e5 | 884 | else |
29f21337 | 885 | return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; |
2f1a74e5 | 886 | } |
887 | ||
e5262d05 | 888 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 889 | int rate) |
e5262d05 | 890 | { |
96579a4e | 891 | struct chip_data *chip = |
51eea52d | 892 | spi_get_ctldata(drv_data->controller->cur_msg->spi); |
025ffe88 | 893 | unsigned int clk_div; |
e5262d05 WC |
894 | |
895 | switch (drv_data->ssp_type) { | |
896 | case QUARK_X1000_SSP: | |
9df461ec | 897 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 898 | break; |
e5262d05 | 899 | default: |
025ffe88 | 900 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 901 | break; |
e5262d05 | 902 | } |
025ffe88 | 903 | return clk_div << 8; |
e5262d05 WC |
904 | } |
905 | ||
51eea52d | 906 | static bool pxa2xx_spi_can_dma(struct spi_controller *controller, |
b6ced294 JN |
907 | struct spi_device *spi, |
908 | struct spi_transfer *xfer) | |
909 | { | |
910 | struct chip_data *chip = spi_get_ctldata(spi); | |
911 | ||
912 | return chip->enable_dma && | |
913 | xfer->len <= MAX_DMA_LEN && | |
914 | xfer->len >= chip->dma_burst_size; | |
915 | } | |
916 | ||
51eea52d | 917 | static int pxa2xx_spi_transfer_one(struct spi_controller *controller, |
71293a60 | 918 | struct spi_device *spi, |
919 | struct spi_transfer *transfer) | |
e0c9905e | 920 | { |
51eea52d LR |
921 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
922 | struct spi_message *message = controller->cur_msg; | |
20f4c379 | 923 | struct chip_data *chip = spi_get_ctldata(spi); |
96579a4e JN |
924 | u32 dma_thresh = chip->dma_threshold; |
925 | u32 dma_burst = chip->dma_burst_size; | |
926 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); | |
bffc967e JN |
927 | u32 clk_div; |
928 | u8 bits; | |
929 | u32 speed; | |
9708c121 | 930 | u32 cr0; |
8d94cc50 | 931 | u32 cr1; |
7d1f1bf6 | 932 | int err; |
b6ced294 | 933 | int dma_mapped; |
e0c9905e | 934 | |
cd7bed00 | 935 | /* Check if we can DMA this transfer */ |
b6ced294 | 936 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { |
7e964455 NF |
937 | |
938 | /* reject already-mapped transfers; PIO won't always work */ | |
939 | if (message->is_dma_mapped | |
940 | || transfer->rx_dma || transfer->tx_dma) { | |
748fbadf | 941 | dev_err(&spi->dev, |
8ae55af3 | 942 | "Mapped transfer length of %u is greater than %d\n", |
7e964455 | 943 | transfer->len, MAX_DMA_LEN); |
d5898e19 | 944 | return -EINVAL; |
7e964455 NF |
945 | } |
946 | ||
947 | /* warn ... we force this to PIO mode */ | |
20f4c379 | 948 | dev_warn_ratelimited(&spi->dev, |
8ae55af3 | 949 | "DMA disabled for transfer length %ld greater than %d\n", |
d5898e19 | 950 | (long)transfer->len, MAX_DMA_LEN); |
8d94cc50 SS |
951 | } |
952 | ||
e0c9905e | 953 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 954 | if (pxa2xx_spi_flush(drv_data) == 0) { |
748fbadf | 955 | dev_err(&spi->dev, "Flush failed\n"); |
d5898e19 | 956 | return -EIO; |
e0c9905e | 957 | } |
9708c121 | 958 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
959 | drv_data->tx = (void *)transfer->tx_buf; |
960 | drv_data->tx_end = drv_data->tx + transfer->len; | |
961 | drv_data->rx = transfer->rx_buf; | |
962 | drv_data->rx_end = drv_data->rx + transfer->len; | |
e0c9905e SS |
963 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
964 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
965 | |
966 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
967 | bits = transfer->bits_per_word; |
968 | speed = transfer->speed_hz; | |
969 | ||
d2c2f6a4 | 970 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
971 | |
972 | if (bits <= 8) { | |
973 | drv_data->n_bytes = 1; | |
974 | drv_data->read = drv_data->read != null_reader ? | |
975 | u8_reader : null_reader; | |
976 | drv_data->write = drv_data->write != null_writer ? | |
977 | u8_writer : null_writer; | |
978 | } else if (bits <= 16) { | |
979 | drv_data->n_bytes = 2; | |
980 | drv_data->read = drv_data->read != null_reader ? | |
981 | u16_reader : null_reader; | |
982 | drv_data->write = drv_data->write != null_writer ? | |
983 | u16_writer : null_writer; | |
984 | } else if (bits <= 32) { | |
985 | drv_data->n_bytes = 4; | |
986 | drv_data->read = drv_data->read != null_reader ? | |
987 | u32_reader : null_reader; | |
988 | drv_data->write = drv_data->write != null_writer ? | |
989 | u32_writer : null_writer; | |
9708c121 | 990 | } |
196b0e2c JN |
991 | /* |
992 | * if bits/word is changed in dma mode, then must check the | |
993 | * thresholds and burst also | |
994 | */ | |
995 | if (chip->enable_dma) { | |
996 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
20f4c379 | 997 | spi, |
196b0e2c JN |
998 | bits, &dma_burst, |
999 | &dma_thresh)) | |
20f4c379 | 1000 | dev_warn_ratelimited(&spi->dev, |
8ae55af3 | 1001 | "DMA burst size reduced to match bits_per_word\n"); |
9708c121 SS |
1002 | } |
1003 | ||
51eea52d | 1004 | dma_mapped = controller->can_dma && |
20f4c379 | 1005 | controller->can_dma(controller, spi, transfer) && |
51eea52d | 1006 | controller->cur_msg_mapped; |
b6ced294 | 1007 | if (dma_mapped) { |
e0c9905e SS |
1008 | |
1009 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1010 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1011 | ||
d5898e19 JN |
1012 | err = pxa2xx_spi_dma_prepare(drv_data, transfer); |
1013 | if (err) | |
1014 | return err; | |
e0c9905e | 1015 | |
8d94cc50 SS |
1016 | /* Clear status and start DMA engine */ |
1017 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1018 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1019 | |
1020 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1021 | } else { |
1022 | /* Ensure we have the correct interrupt handler */ | |
1023 | drv_data->transfer_handler = interrupt_transfer; | |
1024 | ||
8d94cc50 SS |
1025 | /* Clear status */ |
1026 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1027 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1028 | } |
1029 | ||
ee03672d JN |
1030 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1031 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); | |
1032 | if (!pxa25x_ssp_comp(drv_data)) | |
20f4c379 | 1033 | dev_dbg(&spi->dev, "%u Hz actual, %s\n", |
51eea52d | 1034 | controller->max_speed_hz |
ee03672d | 1035 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), |
b6ced294 | 1036 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1037 | else |
20f4c379 | 1038 | dev_dbg(&spi->dev, "%u Hz actual, %s\n", |
51eea52d | 1039 | controller->max_speed_hz / 2 |
ee03672d | 1040 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
b6ced294 | 1041 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1042 | |
a0d2642e | 1043 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1044 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1045 | != chip->lpss_rx_threshold) | |
1046 | pxa2xx_spi_write(drv_data, SSIRF, | |
1047 | chip->lpss_rx_threshold); | |
1048 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1049 | != chip->lpss_tx_threshold) | |
1050 | pxa2xx_spi_write(drv_data, SSITF, | |
1051 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1052 | } |
1053 | ||
e5262d05 | 1054 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1055 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1056 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1057 | |
8d94cc50 | 1058 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1059 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1060 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1061 | != (cr1 & change_mask)) { | |
b97c74bd | 1062 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1063 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1064 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1065 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1066 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1067 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1068 | /* restart the SSP */ |
c039dd27 | 1069 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1070 | |
8d94cc50 | 1071 | } else { |
2a8626a9 | 1072 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1073 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1074 | } |
b97c74bd | 1075 | |
82391856 LR |
1076 | if (drv_data->ssp_type == MMP2_SSP) { |
1077 | u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) | |
1078 | & SSSR_TFL_MASK) >> 8; | |
1079 | ||
1080 | if (tx_level) { | |
1081 | /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ | |
1082 | dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", | |
1083 | tx_level); | |
1084 | if (tx_level > transfer->len) | |
1085 | tx_level = transfer->len; | |
1086 | drv_data->tx += tx_level; | |
1087 | } | |
1088 | } | |
1089 | ||
51eea52d | 1090 | if (spi_controller_is_slave(controller)) { |
ec93cb6f LR |
1091 | while (drv_data->write(drv_data)) |
1092 | ; | |
77d33897 LR |
1093 | if (drv_data->gpiod_ready) { |
1094 | gpiod_set_value(drv_data->gpiod_ready, 1); | |
1095 | udelay(1); | |
1096 | gpiod_set_value(drv_data->gpiod_ready, 0); | |
1097 | } | |
ec93cb6f LR |
1098 | } |
1099 | ||
d5898e19 JN |
1100 | /* |
1101 | * Release the data by enabling service requests and interrupts, | |
1102 | * without changing any mode bits | |
1103 | */ | |
c039dd27 | 1104 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
d5898e19 JN |
1105 | |
1106 | return 1; | |
e0c9905e SS |
1107 | } |
1108 | ||
51eea52d | 1109 | static int pxa2xx_spi_slave_abort(struct spi_controller *controller) |
ec93cb6f | 1110 | { |
51eea52d | 1111 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
ec93cb6f LR |
1112 | |
1113 | /* Stop and reset SSP */ | |
1114 | write_SSSR_CS(drv_data, drv_data->clear_sr); | |
1115 | reset_sccr1(drv_data); | |
1116 | if (!pxa25x_ssp_comp(drv_data)) | |
1117 | pxa2xx_spi_write(drv_data, SSTO, 0); | |
1118 | pxa2xx_spi_flush(drv_data); | |
1119 | pxa2xx_spi_write(drv_data, SSCR0, | |
1120 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
1121 | ||
1122 | dev_dbg(&drv_data->pdev->dev, "transfer aborted\n"); | |
1123 | ||
51eea52d LR |
1124 | drv_data->controller->cur_msg->status = -EINTR; |
1125 | spi_finalize_current_transfer(drv_data->controller); | |
ec93cb6f LR |
1126 | |
1127 | return 0; | |
1128 | } | |
1129 | ||
51eea52d | 1130 | static void pxa2xx_spi_handle_err(struct spi_controller *controller, |
d5898e19 | 1131 | struct spi_message *msg) |
e0c9905e | 1132 | { |
51eea52d | 1133 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
e0c9905e | 1134 | |
d5898e19 JN |
1135 | /* Disable the SSP */ |
1136 | pxa2xx_spi_write(drv_data, SSCR0, | |
1137 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
1138 | /* Clear and disable interrupts and service requests */ | |
1139 | write_SSSR_CS(drv_data, drv_data->clear_sr); | |
1140 | pxa2xx_spi_write(drv_data, SSCR1, | |
1141 | pxa2xx_spi_read(drv_data, SSCR1) | |
1142 | & ~(drv_data->int_cr1 | drv_data->dma_cr1)); | |
1143 | if (!pxa25x_ssp_comp(drv_data)) | |
1144 | pxa2xx_spi_write(drv_data, SSTO, 0); | |
e0c9905e | 1145 | |
d5898e19 JN |
1146 | /* |
1147 | * Stop the DMA if running. Note DMA callback handler may have unset | |
1148 | * the dma_running already, which is fine as stopping is not needed | |
1149 | * then but we shouldn't rely this flag for anything else than | |
1150 | * stopping. For instance to differentiate between PIO and DMA | |
1151 | * transfers. | |
1152 | */ | |
1153 | if (atomic_read(&drv_data->dma_running)) | |
1154 | pxa2xx_spi_dma_stop(drv_data); | |
e0c9905e SS |
1155 | } |
1156 | ||
51eea52d | 1157 | static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) |
7d94a505 | 1158 | { |
51eea52d | 1159 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
7d94a505 MW |
1160 | |
1161 | /* Disable the SSP now */ | |
c039dd27 JN |
1162 | pxa2xx_spi_write(drv_data, SSCR0, |
1163 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1164 | |
7d94a505 MW |
1165 | return 0; |
1166 | } | |
1167 | ||
a7bb3909 EM |
1168 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1169 | struct pxa2xx_spi_chip *chip_info) | |
1170 | { | |
3cc7b0e3 JN |
1171 | struct driver_data *drv_data = |
1172 | spi_controller_get_devdata(spi->controller); | |
c18d925f | 1173 | struct gpio_desc *gpiod; |
a7bb3909 EM |
1174 | int err = 0; |
1175 | ||
99f499cd MW |
1176 | if (chip == NULL) |
1177 | return 0; | |
1178 | ||
6ac5a435 | 1179 | if (drv_data->cs_gpiods) { |
6ac5a435 AS |
1180 | gpiod = drv_data->cs_gpiods[spi->chip_select]; |
1181 | if (gpiod) { | |
c18d925f | 1182 | chip->gpiod_cs = gpiod; |
6ac5a435 AS |
1183 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; |
1184 | gpiod_set_value(gpiod, chip->gpio_cs_inverted); | |
99f499cd MW |
1185 | } |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | if (chip_info == NULL) | |
a7bb3909 EM |
1191 | return 0; |
1192 | ||
1193 | /* NOTE: setup() can be called multiple times, possibly with | |
1194 | * different chip_info, release previously requested GPIO | |
1195 | */ | |
c18d925f | 1196 | if (chip->gpiod_cs) { |
a885eebc | 1197 | gpiod_put(chip->gpiod_cs); |
c18d925f JK |
1198 | chip->gpiod_cs = NULL; |
1199 | } | |
a7bb3909 EM |
1200 | |
1201 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1202 | if (chip_info->cs_control) { | |
1203 | chip->cs_control = chip_info->cs_control; | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1208 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1209 | if (err) { | |
f6bd03a7 JN |
1210 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1211 | chip_info->gpio_cs); | |
a7bb3909 EM |
1212 | return err; |
1213 | } | |
1214 | ||
c18d925f JK |
1215 | gpiod = gpio_to_desc(chip_info->gpio_cs); |
1216 | chip->gpiod_cs = gpiod; | |
a7bb3909 EM |
1217 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; |
1218 | ||
c18d925f | 1219 | err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); |
a7bb3909 EM |
1220 | } |
1221 | ||
1222 | return err; | |
1223 | } | |
1224 | ||
e0c9905e SS |
1225 | static int setup(struct spi_device *spi) |
1226 | { | |
bffc967e | 1227 | struct pxa2xx_spi_chip *chip_info; |
e0c9905e | 1228 | struct chip_data *chip; |
dccf7369 | 1229 | const struct lpss_config *config; |
3cc7b0e3 JN |
1230 | struct driver_data *drv_data = |
1231 | spi_controller_get_devdata(spi->controller); | |
a0d2642e MW |
1232 | uint tx_thres, tx_hi_thres, rx_thres; |
1233 | ||
e5262d05 WC |
1234 | switch (drv_data->ssp_type) { |
1235 | case QUARK_X1000_SSP: | |
1236 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1237 | tx_hi_thres = 0; | |
1238 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1239 | break; | |
7c7289a4 AS |
1240 | case CE4100_SSP: |
1241 | tx_thres = TX_THRESH_CE4100_DFLT; | |
1242 | tx_hi_thres = 0; | |
1243 | rx_thres = RX_THRESH_CE4100_DFLT; | |
1244 | break; | |
03fbf488 JN |
1245 | case LPSS_LPT_SSP: |
1246 | case LPSS_BYT_SSP: | |
30f3a6ab | 1247 | case LPSS_BSW_SSP: |
34cadd9c | 1248 | case LPSS_SPT_SSP: |
b7c08cf8 | 1249 | case LPSS_BXT_SSP: |
fc0b2acc | 1250 | case LPSS_CNL_SSP: |
dccf7369 JN |
1251 | config = lpss_get_config(drv_data); |
1252 | tx_thres = config->tx_threshold_lo; | |
1253 | tx_hi_thres = config->tx_threshold_hi; | |
1254 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1255 | break; |
1256 | default: | |
a0d2642e | 1257 | tx_hi_thres = 0; |
51eea52d | 1258 | if (spi_controller_is_slave(drv_data->controller)) { |
ec93cb6f LR |
1259 | tx_thres = 1; |
1260 | rx_thres = 2; | |
1261 | } else { | |
1262 | tx_thres = TX_THRESH_DFLT; | |
1263 | rx_thres = RX_THRESH_DFLT; | |
1264 | } | |
e5262d05 | 1265 | break; |
a0d2642e | 1266 | } |
e0c9905e | 1267 | |
8d94cc50 | 1268 | /* Only alloc on first setup */ |
e0c9905e | 1269 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1270 | if (!chip) { |
e0c9905e | 1271 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1272 | if (!chip) |
e0c9905e SS |
1273 | return -ENOMEM; |
1274 | ||
2a8626a9 SAS |
1275 | if (drv_data->ssp_type == CE4100_SSP) { |
1276 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1277 | dev_err(&spi->dev, |
1278 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1279 | kfree(chip); |
1280 | return -EINVAL; | |
1281 | } | |
1282 | ||
1283 | chip->frm = spi->chip_select; | |
c18d925f | 1284 | } |
51eea52d | 1285 | chip->enable_dma = drv_data->controller_info->enable_dma; |
f1f640a9 | 1286 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1287 | } |
1288 | ||
8d94cc50 SS |
1289 | /* protocol drivers may change the chip settings, so... |
1290 | * if chip_info exists, use it */ | |
1291 | chip_info = spi->controller_data; | |
1292 | ||
e0c9905e | 1293 | /* chip_info isn't always needed */ |
8d94cc50 | 1294 | chip->cr1 = 0; |
e0c9905e | 1295 | if (chip_info) { |
f1f640a9 VS |
1296 | if (chip_info->timeout) |
1297 | chip->timeout = chip_info->timeout; | |
1298 | if (chip_info->tx_threshold) | |
1299 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1300 | if (chip_info->tx_hi_threshold) |
1301 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1302 | if (chip_info->rx_threshold) |
1303 | rx_thres = chip_info->rx_threshold; | |
e0c9905e | 1304 | chip->dma_threshold = 0; |
e0c9905e SS |
1305 | if (chip_info->enable_loopback) |
1306 | chip->cr1 = SSCR1_LBM; | |
1307 | } | |
51eea52d | 1308 | if (spi_controller_is_slave(drv_data->controller)) { |
ec93cb6f LR |
1309 | chip->cr1 |= SSCR1_SCFR; |
1310 | chip->cr1 |= SSCR1_SCLKDIR; | |
1311 | chip->cr1 |= SSCR1_SFRMDIR; | |
1312 | chip->cr1 |= SSCR1_SPH; | |
1313 | } | |
e0c9905e | 1314 | |
a0d2642e MW |
1315 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1316 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1317 | | SSITF_TxHiThresh(tx_hi_thres); | |
1318 | ||
8d94cc50 SS |
1319 | /* set dma burst and threshold outside of chip_info path so that if |
1320 | * chip_info goes away after setting chip->enable_dma, the | |
1321 | * burst and threshold can still respond to changes in bits_per_word */ | |
1322 | if (chip->enable_dma) { | |
1323 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1324 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1325 | spi->bits_per_word, | |
8d94cc50 SS |
1326 | &chip->dma_burst_size, |
1327 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1328 | dev_warn(&spi->dev, |
1329 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 1330 | } |
000c6af4 AS |
1331 | dev_dbg(&spi->dev, |
1332 | "in setup: DMA burst size set to %u\n", | |
1333 | chip->dma_burst_size); | |
8d94cc50 SS |
1334 | } |
1335 | ||
e5262d05 WC |
1336 | switch (drv_data->ssp_type) { |
1337 | case QUARK_X1000_SSP: | |
1338 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1339 | & QUARK_X1000_SSCR1_RFT) | |
1340 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1341 | & QUARK_X1000_SSCR1_TFT); | |
1342 | break; | |
7c7289a4 AS |
1343 | case CE4100_SSP: |
1344 | chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | | |
1345 | (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); | |
1346 | break; | |
e5262d05 WC |
1347 | default: |
1348 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1349 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1350 | break; | |
1351 | } | |
1352 | ||
7f6ee1ad JC |
1353 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1354 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1355 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1356 | |
b833172f MW |
1357 | if (spi->mode & SPI_LOOP) |
1358 | chip->cr1 |= SSCR1_LBM; | |
1359 | ||
e0c9905e SS |
1360 | if (spi->bits_per_word <= 8) { |
1361 | chip->n_bytes = 1; | |
e0c9905e SS |
1362 | chip->read = u8_reader; |
1363 | chip->write = u8_writer; | |
1364 | } else if (spi->bits_per_word <= 16) { | |
1365 | chip->n_bytes = 2; | |
e0c9905e SS |
1366 | chip->read = u16_reader; |
1367 | chip->write = u16_writer; | |
1368 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1369 | chip->n_bytes = 4; |
e0c9905e SS |
1370 | chip->read = u32_reader; |
1371 | chip->write = u32_writer; | |
e0c9905e SS |
1372 | } |
1373 | ||
1374 | spi_set_ctldata(spi, chip); | |
1375 | ||
2a8626a9 SAS |
1376 | if (drv_data->ssp_type == CE4100_SSP) |
1377 | return 0; | |
1378 | ||
a7bb3909 | 1379 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1380 | } |
1381 | ||
0ffa0285 | 1382 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1383 | { |
0ffa0285 | 1384 | struct chip_data *chip = spi_get_ctldata(spi); |
3cc7b0e3 JN |
1385 | struct driver_data *drv_data = |
1386 | spi_controller_get_devdata(spi->controller); | |
e0c9905e | 1387 | |
7348d82a DR |
1388 | if (!chip) |
1389 | return; | |
1390 | ||
6ac5a435 | 1391 | if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && |
c18d925f | 1392 | chip->gpiod_cs) |
a885eebc | 1393 | gpiod_put(chip->gpiod_cs); |
a7bb3909 | 1394 | |
e0c9905e SS |
1395 | kfree(chip); |
1396 | } | |
1397 | ||
8422ddf7 | 1398 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1399 | { "INT33C0", LPSS_LPT_SSP }, |
1400 | { "INT33C1", LPSS_LPT_SSP }, | |
1401 | { "INT3430", LPSS_LPT_SSP }, | |
1402 | { "INT3431", LPSS_LPT_SSP }, | |
1403 | { "80860F0E", LPSS_BYT_SSP }, | |
30f3a6ab | 1404 | { "8086228E", LPSS_BSW_SSP }, |
03fbf488 JN |
1405 | { }, |
1406 | }; | |
1407 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1408 | ||
34cadd9c JN |
1409 | /* |
1410 | * PCI IDs of compound devices that integrate both host controller and private | |
1411 | * integrated DMA engine. Please note these are not used in module | |
1412 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1413 | */ | |
1414 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1415 | /* SPT-LP */ | |
1416 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1417 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1418 | /* SPT-H */ | |
1419 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1420 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
704d2b07 MW |
1421 | /* KBL-H */ |
1422 | { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, | |
1423 | { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, | |
c1b03f11 | 1424 | /* BXT A-Step */ |
b7c08cf8 JN |
1425 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, |
1426 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1427 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
c1b03f11 JN |
1428 | /* BXT B-Step */ |
1429 | { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, | |
1430 | { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, | |
1431 | { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, | |
e18a80ac DB |
1432 | /* GLK */ |
1433 | { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, | |
1434 | { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, | |
1435 | { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, | |
22d71a50 MW |
1436 | /* ICL-LP */ |
1437 | { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, | |
1438 | { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, | |
1439 | { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, | |
8cc77204 JN |
1440 | /* EHL */ |
1441 | { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP }, | |
1442 | { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP }, | |
1443 | { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP }, | |
b7c08cf8 JN |
1444 | /* APL */ |
1445 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1446 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1447 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
fc0b2acc JN |
1448 | /* CNL-LP */ |
1449 | { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, | |
1450 | { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, | |
1451 | { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, | |
1452 | /* CNL-H */ | |
1453 | { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, | |
1454 | { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, | |
1455 | { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, | |
41a91802 EG |
1456 | /* CML-LP */ |
1457 | { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP }, | |
1458 | { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP }, | |
1459 | { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP }, | |
94e5c23d | 1460 | { }, |
34cadd9c JN |
1461 | }; |
1462 | ||
87ae1d2d LR |
1463 | static const struct of_device_id pxa2xx_spi_of_match[] = { |
1464 | { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, | |
1465 | {}, | |
1466 | }; | |
1467 | MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); | |
1468 | ||
1469 | #ifdef CONFIG_ACPI | |
1470 | ||
1471 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1472 | { | |
1473 | unsigned int devid; | |
1474 | int port_id = -1; | |
1475 | ||
1476 | if (adev && adev->pnp.unique_id && | |
1477 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1478 | port_id = devid; | |
1479 | return port_id; | |
1480 | } | |
1481 | ||
1482 | #else /* !CONFIG_ACPI */ | |
1483 | ||
1484 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1485 | { | |
1486 | return -1; | |
1487 | } | |
1488 | ||
1489 | #endif /* CONFIG_ACPI */ | |
1490 | ||
1491 | ||
1492 | #ifdef CONFIG_PCI | |
1493 | ||
34cadd9c JN |
1494 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) |
1495 | { | |
5ba846b1 | 1496 | return param == chan->device->dev; |
34cadd9c JN |
1497 | } |
1498 | ||
87ae1d2d LR |
1499 | #endif /* CONFIG_PCI */ |
1500 | ||
51eea52d | 1501 | static struct pxa2xx_spi_controller * |
0db64215 | 1502 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 | 1503 | { |
51eea52d | 1504 | struct pxa2xx_spi_controller *pdata; |
a3496855 MW |
1505 | struct acpi_device *adev; |
1506 | struct ssp_device *ssp; | |
1507 | struct resource *res; | |
34cadd9c JN |
1508 | const struct acpi_device_id *adev_id = NULL; |
1509 | const struct pci_device_id *pcidev_id = NULL; | |
87ae1d2d | 1510 | const struct of_device_id *of_id = NULL; |
55ef8262 | 1511 | enum pxa_ssp_type type; |
a3496855 | 1512 | |
b9f6940a | 1513 | adev = ACPI_COMPANION(&pdev->dev); |
a3496855 | 1514 | |
87ae1d2d LR |
1515 | if (pdev->dev.of_node) |
1516 | of_id = of_match_device(pdev->dev.driver->of_match_table, | |
1517 | &pdev->dev); | |
1518 | else if (dev_is_pci(pdev->dev.parent)) | |
34cadd9c JN |
1519 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, |
1520 | to_pci_dev(pdev->dev.parent)); | |
0db64215 | 1521 | else if (adev) |
34cadd9c JN |
1522 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
1523 | &pdev->dev); | |
0db64215 JN |
1524 | else |
1525 | return NULL; | |
34cadd9c JN |
1526 | |
1527 | if (adev_id) | |
55ef8262 | 1528 | type = (enum pxa_ssp_type)adev_id->driver_data; |
34cadd9c | 1529 | else if (pcidev_id) |
55ef8262 | 1530 | type = (enum pxa_ssp_type)pcidev_id->driver_data; |
87ae1d2d LR |
1531 | else if (of_id) |
1532 | type = (enum pxa_ssp_type)of_id->data; | |
03fbf488 JN |
1533 | else |
1534 | return NULL; | |
1535 | ||
cc0ee987 | 1536 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1537 | if (!pdata) |
a3496855 | 1538 | return NULL; |
a3496855 MW |
1539 | |
1540 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1541 | if (!res) | |
1542 | return NULL; | |
1543 | ||
1544 | ssp = &pdata->ssp; | |
1545 | ||
1546 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1547 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1548 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1549 | return NULL; |
a3496855 | 1550 | |
87ae1d2d | 1551 | #ifdef CONFIG_PCI |
34cadd9c JN |
1552 | if (pcidev_id) { |
1553 | pdata->tx_param = pdev->dev.parent; | |
1554 | pdata->rx_param = pdev->dev.parent; | |
1555 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1556 | } | |
87ae1d2d | 1557 | #endif |
34cadd9c | 1558 | |
a3496855 MW |
1559 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1560 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1561 | ssp->type = type; |
a3496855 | 1562 | ssp->pdev = pdev; |
0db64215 | 1563 | ssp->port_id = pxa2xx_spi_get_port_id(adev); |
a3496855 | 1564 | |
f0915dfc | 1565 | pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave"); |
a3496855 | 1566 | pdata->num_chipselect = 1; |
cddb339b | 1567 | pdata->enable_dma = true; |
37821a82 | 1568 | pdata->dma_burst_size = 1; |
a3496855 MW |
1569 | |
1570 | return pdata; | |
1571 | } | |
1572 | ||
51eea52d | 1573 | static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, |
3cc7b0e3 | 1574 | unsigned int cs) |
0c27d9cf | 1575 | { |
51eea52d | 1576 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
0c27d9cf MW |
1577 | |
1578 | if (has_acpi_companion(&drv_data->pdev->dev)) { | |
1579 | switch (drv_data->ssp_type) { | |
1580 | /* | |
1581 | * For Atoms the ACPI DeviceSelection used by the Windows | |
1582 | * driver starts from 1 instead of 0 so translate it here | |
1583 | * to match what Linux expects. | |
1584 | */ | |
1585 | case LPSS_BYT_SSP: | |
30f3a6ab | 1586 | case LPSS_BSW_SSP: |
0c27d9cf MW |
1587 | return cs - 1; |
1588 | ||
1589 | default: | |
1590 | break; | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | return cs; | |
1595 | } | |
1596 | ||
fd4a319b | 1597 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1598 | { |
1599 | struct device *dev = &pdev->dev; | |
51eea52d LR |
1600 | struct pxa2xx_spi_controller *platform_info; |
1601 | struct spi_controller *controller; | |
65a00a20 | 1602 | struct driver_data *drv_data; |
2f1a74e5 | 1603 | struct ssp_device *ssp; |
8b136baa | 1604 | const struct lpss_config *config; |
99f499cd | 1605 | int status, count; |
c039dd27 | 1606 | u32 tmp; |
e0c9905e | 1607 | |
851bacf5 MW |
1608 | platform_info = dev_get_platdata(dev); |
1609 | if (!platform_info) { | |
0db64215 | 1610 | platform_info = pxa2xx_spi_init_pdata(pdev); |
a3496855 MW |
1611 | if (!platform_info) { |
1612 | dev_err(&pdev->dev, "missing platform data\n"); | |
1613 | return -ENODEV; | |
1614 | } | |
851bacf5 | 1615 | } |
e0c9905e | 1616 | |
baffe169 | 1617 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1618 | if (!ssp) |
1619 | ssp = &platform_info->ssp; | |
1620 | ||
1621 | if (!ssp->mmio_base) { | |
1622 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1623 | return -ENODEV; |
1624 | } | |
1625 | ||
ec93cb6f | 1626 | if (platform_info->is_slave) |
51eea52d | 1627 | controller = spi_alloc_slave(dev, sizeof(struct driver_data)); |
ec93cb6f | 1628 | else |
51eea52d | 1629 | controller = spi_alloc_master(dev, sizeof(struct driver_data)); |
ec93cb6f | 1630 | |
51eea52d LR |
1631 | if (!controller) { |
1632 | dev_err(&pdev->dev, "cannot alloc spi_controller\n"); | |
baffe169 | 1633 | pxa_ssp_free(ssp); |
e0c9905e SS |
1634 | return -ENOMEM; |
1635 | } | |
51eea52d LR |
1636 | drv_data = spi_controller_get_devdata(controller); |
1637 | drv_data->controller = controller; | |
1638 | drv_data->controller_info = platform_info; | |
e0c9905e | 1639 | drv_data->pdev = pdev; |
2f1a74e5 | 1640 | drv_data->ssp = ssp; |
e0c9905e | 1641 | |
51eea52d | 1642 | controller->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1643 | /* the spi->mode bits understood by this driver: */ |
51eea52d LR |
1644 | controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
1645 | ||
1646 | controller->bus_num = ssp->port_id; | |
1647 | controller->dma_alignment = DMA_ALIGNMENT; | |
1648 | controller->cleanup = cleanup; | |
1649 | controller->setup = setup; | |
1650 | controller->set_cs = pxa2xx_spi_set_cs; | |
1651 | controller->transfer_one = pxa2xx_spi_transfer_one; | |
1652 | controller->slave_abort = pxa2xx_spi_slave_abort; | |
1653 | controller->handle_err = pxa2xx_spi_handle_err; | |
1654 | controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
1655 | controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; | |
1656 | controller->auto_runtime_pm = true; | |
1657 | controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; | |
e0c9905e | 1658 | |
2f1a74e5 | 1659 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1660 | |
2f1a74e5 | 1661 | drv_data->ioaddr = ssp->mmio_base; |
1662 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1663 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1664 | switch (drv_data->ssp_type) { |
1665 | case QUARK_X1000_SSP: | |
51eea52d | 1666 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e5262d05 WC |
1667 | break; |
1668 | default: | |
51eea52d | 1669 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e5262d05 WC |
1670 | break; |
1671 | } | |
1672 | ||
e0c9905e SS |
1673 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1674 | drv_data->dma_cr1 = 0; | |
1675 | drv_data->clear_sr = SSSR_ROR; | |
1676 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1677 | } else { | |
51eea52d | 1678 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1679 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1680 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e | 1681 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
ec93cb6f LR |
1682 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS |
1683 | | SSSR_ROR | SSSR_TUR; | |
e0c9905e SS |
1684 | } |
1685 | ||
49cbb1e0 SAS |
1686 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1687 | drv_data); | |
e0c9905e | 1688 | if (status < 0) { |
65a00a20 | 1689 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
51eea52d | 1690 | goto out_error_controller_alloc; |
e0c9905e SS |
1691 | } |
1692 | ||
1693 | /* Setup DMA if requested */ | |
e0c9905e | 1694 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1695 | status = pxa2xx_spi_dma_setup(drv_data); |
1696 | if (status) { | |
8b57b11b | 1697 | dev_warn(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1698 | platform_info->enable_dma = false; |
b6ced294 | 1699 | } else { |
51eea52d | 1700 | controller->can_dma = pxa2xx_spi_can_dma; |
bf9f742c | 1701 | controller->max_dma_len = MAX_DMA_LEN; |
e0c9905e | 1702 | } |
e0c9905e SS |
1703 | } |
1704 | ||
1705 | /* Enable SOC clock */ | |
62bbc864 TJ |
1706 | status = clk_prepare_enable(ssp->clk); |
1707 | if (status) | |
1708 | goto out_error_dma_irq_alloc; | |
3343b7a6 | 1709 | |
51eea52d | 1710 | controller->max_speed_hz = clk_get_rate(ssp->clk); |
23cdddb2 JN |
1711 | /* |
1712 | * Set minimum speed for all other platforms than Intel Quark which is | |
1713 | * able do under 1 Hz transfers. | |
1714 | */ | |
1715 | if (!pxa25x_ssp_comp(drv_data)) | |
1716 | controller->min_speed_hz = | |
1717 | DIV_ROUND_UP(controller->max_speed_hz, 4096); | |
1718 | else if (!is_quark_x1000_ssp(drv_data)) | |
1719 | controller->min_speed_hz = | |
1720 | DIV_ROUND_UP(controller->max_speed_hz, 512); | |
e0c9905e SS |
1721 | |
1722 | /* Load default SSP configuration */ | |
c039dd27 | 1723 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1724 | switch (drv_data->ssp_type) { |
1725 | case QUARK_X1000_SSP: | |
7c7289a4 AS |
1726 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | |
1727 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
c039dd27 | 1728 | pxa2xx_spi_write(drv_data, SSCR1, tmp); |
e5262d05 WC |
1729 | |
1730 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
7c7289a4 AS |
1731 | tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); |
1732 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 | 1733 | break; |
7c7289a4 AS |
1734 | case CE4100_SSP: |
1735 | tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | | |
1736 | CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); | |
1737 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1738 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1739 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
a2dd8af0 | 1740 | break; |
e5262d05 | 1741 | default: |
ec93cb6f | 1742 | |
51eea52d | 1743 | if (spi_controller_is_slave(controller)) { |
ec93cb6f LR |
1744 | tmp = SSCR1_SCFR | |
1745 | SSCR1_SCLKDIR | | |
1746 | SSCR1_SFRMDIR | | |
1747 | SSCR1_RxTresh(2) | | |
1748 | SSCR1_TxTresh(1) | | |
1749 | SSCR1_SPH; | |
1750 | } else { | |
1751 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | | |
1752 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1753 | } | |
c039dd27 | 1754 | pxa2xx_spi_write(drv_data, SSCR1, tmp); |
ec93cb6f | 1755 | tmp = SSCR0_Motorola | SSCR0_DataSize(8); |
51eea52d | 1756 | if (!spi_controller_is_slave(controller)) |
ec93cb6f | 1757 | tmp |= SSCR0_SCR(2); |
c039dd27 | 1758 | pxa2xx_spi_write(drv_data, SSCR0, tmp); |
e5262d05 WC |
1759 | break; |
1760 | } | |
1761 | ||
2a8626a9 | 1762 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1763 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1764 | |
1765 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1766 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1767 | |
8b136baa JN |
1768 | if (is_lpss_ssp(drv_data)) { |
1769 | lpss_ssp_setup(drv_data); | |
1770 | config = lpss_get_config(drv_data); | |
1771 | if (config->reg_capabilities >= 0) { | |
1772 | tmp = __lpss_ssp_read_priv(drv_data, | |
1773 | config->reg_capabilities); | |
1774 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1775 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1776 | platform_info->num_chipselect = ffz(tmp); | |
30f3a6ab MW |
1777 | } else if (config->cs_num) { |
1778 | platform_info->num_chipselect = config->cs_num; | |
8b136baa JN |
1779 | } |
1780 | } | |
51eea52d | 1781 | controller->num_chipselect = platform_info->num_chipselect; |
8b136baa | 1782 | |
99f499cd | 1783 | count = gpiod_count(&pdev->dev, "cs"); |
6ac5a435 AS |
1784 | if (count > 0) { |
1785 | int i; | |
1786 | ||
51eea52d LR |
1787 | controller->num_chipselect = max_t(int, count, |
1788 | controller->num_chipselect); | |
99f499cd | 1789 | |
6ac5a435 | 1790 | drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, |
51eea52d | 1791 | controller->num_chipselect, sizeof(struct gpio_desc *), |
6ac5a435 AS |
1792 | GFP_KERNEL); |
1793 | if (!drv_data->cs_gpiods) { | |
1794 | status = -ENOMEM; | |
1795 | goto out_error_clock_enabled; | |
1796 | } | |
1797 | ||
51eea52d | 1798 | for (i = 0; i < controller->num_chipselect; i++) { |
6ac5a435 AS |
1799 | struct gpio_desc *gpiod; |
1800 | ||
d35f2dc9 | 1801 | gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); |
6ac5a435 AS |
1802 | if (IS_ERR(gpiod)) { |
1803 | /* Means use native chip select */ | |
1804 | if (PTR_ERR(gpiod) == -ENOENT) | |
1805 | continue; | |
1806 | ||
77d33897 | 1807 | status = PTR_ERR(gpiod); |
6ac5a435 AS |
1808 | goto out_error_clock_enabled; |
1809 | } else { | |
1810 | drv_data->cs_gpiods[i] = gpiod; | |
1811 | } | |
1812 | } | |
1813 | } | |
1814 | ||
77d33897 LR |
1815 | if (platform_info->is_slave) { |
1816 | drv_data->gpiod_ready = devm_gpiod_get_optional(dev, | |
1817 | "ready", GPIOD_OUT_LOW); | |
1818 | if (IS_ERR(drv_data->gpiod_ready)) { | |
1819 | status = PTR_ERR(drv_data->gpiod_ready); | |
1820 | goto out_error_clock_enabled; | |
1821 | } | |
1822 | } | |
1823 | ||
836d1a22 AO |
1824 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1825 | pm_runtime_use_autosuspend(&pdev->dev); | |
1826 | pm_runtime_set_active(&pdev->dev); | |
1827 | pm_runtime_enable(&pdev->dev); | |
1828 | ||
e0c9905e SS |
1829 | /* Register with the SPI framework */ |
1830 | platform_set_drvdata(pdev, drv_data); | |
51eea52d | 1831 | status = devm_spi_register_controller(&pdev->dev, controller); |
e0c9905e | 1832 | if (status != 0) { |
51eea52d | 1833 | dev_err(&pdev->dev, "problem registering spi controller\n"); |
7f86bde9 | 1834 | goto out_error_clock_enabled; |
e0c9905e SS |
1835 | } |
1836 | ||
1837 | return status; | |
1838 | ||
e0c9905e | 1839 | out_error_clock_enabled: |
e2b714af JN |
1840 | pm_runtime_put_noidle(&pdev->dev); |
1841 | pm_runtime_disable(&pdev->dev); | |
3343b7a6 | 1842 | clk_disable_unprepare(ssp->clk); |
62bbc864 TJ |
1843 | |
1844 | out_error_dma_irq_alloc: | |
cd7bed00 | 1845 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1846 | free_irq(ssp->irq, drv_data); |
e0c9905e | 1847 | |
51eea52d LR |
1848 | out_error_controller_alloc: |
1849 | spi_controller_put(controller); | |
baffe169 | 1850 | pxa_ssp_free(ssp); |
e0c9905e SS |
1851 | return status; |
1852 | } | |
1853 | ||
1854 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1855 | { | |
1856 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1857 | struct ssp_device *ssp; |
e0c9905e SS |
1858 | |
1859 | if (!drv_data) | |
1860 | return 0; | |
51e911e2 | 1861 | ssp = drv_data->ssp; |
e0c9905e | 1862 | |
7d94a505 MW |
1863 | pm_runtime_get_sync(&pdev->dev); |
1864 | ||
e0c9905e | 1865 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1866 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1867 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1868 | |
1869 | /* Release DMA */ | |
51eea52d | 1870 | if (drv_data->controller_info->enable_dma) |
cd7bed00 | 1871 | pxa2xx_spi_dma_release(drv_data); |
e0c9905e | 1872 | |
7d94a505 MW |
1873 | pm_runtime_put_noidle(&pdev->dev); |
1874 | pm_runtime_disable(&pdev->dev); | |
1875 | ||
e0c9905e | 1876 | /* Release IRQ */ |
2f1a74e5 | 1877 | free_irq(ssp->irq, drv_data); |
1878 | ||
1879 | /* Release SSP */ | |
baffe169 | 1880 | pxa_ssp_free(ssp); |
e0c9905e | 1881 | |
e0c9905e SS |
1882 | return 0; |
1883 | } | |
1884 | ||
382cebb0 | 1885 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1886 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1887 | { |
86d2593a | 1888 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1889 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1890 | int status; |
e0c9905e | 1891 | |
51eea52d | 1892 | status = spi_controller_suspend(drv_data->controller); |
e0c9905e SS |
1893 | if (status != 0) |
1894 | return status; | |
c039dd27 | 1895 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1896 | |
1897 | if (!pm_runtime_suspended(dev)) | |
1898 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1899 | |
1900 | return 0; | |
1901 | } | |
1902 | ||
86d2593a | 1903 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1904 | { |
86d2593a | 1905 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1906 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1907 | int status; |
e0c9905e SS |
1908 | |
1909 | /* Enable the SSP clock */ | |
62bbc864 TJ |
1910 | if (!pm_runtime_suspended(dev)) { |
1911 | status = clk_prepare_enable(ssp->clk); | |
1912 | if (status) | |
1913 | return status; | |
1914 | } | |
e0c9905e SS |
1915 | |
1916 | /* Start the queue running */ | |
51eea52d | 1917 | return spi_controller_resume(drv_data->controller); |
e0c9905e | 1918 | } |
7d94a505 MW |
1919 | #endif |
1920 | ||
ec833050 | 1921 | #ifdef CONFIG_PM |
7d94a505 MW |
1922 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1923 | { | |
1924 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1925 | ||
1926 | clk_disable_unprepare(drv_data->ssp->clk); | |
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1931 | { | |
1932 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
62bbc864 | 1933 | int status; |
7d94a505 | 1934 | |
62bbc864 TJ |
1935 | status = clk_prepare_enable(drv_data->ssp->clk); |
1936 | return status; | |
7d94a505 MW |
1937 | } |
1938 | #endif | |
86d2593a | 1939 | |
47145210 | 1940 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1941 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1942 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1943 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1944 | }; |
e0c9905e SS |
1945 | |
1946 | static struct platform_driver driver = { | |
1947 | .driver = { | |
86d2593a | 1948 | .name = "pxa2xx-spi", |
86d2593a | 1949 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1950 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
87ae1d2d | 1951 | .of_match_table = of_match_ptr(pxa2xx_spi_of_match), |
e0c9905e | 1952 | }, |
fbd29a14 | 1953 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1954 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1955 | }; |
1956 | ||
1957 | static int __init pxa2xx_spi_init(void) | |
1958 | { | |
fbd29a14 | 1959 | return platform_driver_register(&driver); |
e0c9905e | 1960 | } |
5b61a749 | 1961 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1962 | |
1963 | static void __exit pxa2xx_spi_exit(void) | |
1964 | { | |
1965 | platform_driver_unregister(&driver); | |
1966 | } | |
1967 | module_exit(pxa2xx_spi_exit); | |
51ebf6ac FS |
1968 | |
1969 | MODULE_SOFTDEP("pre: dw_dmac"); |