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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
8b136baa | 16 | #include <linux/bitops.h> |
e0c9905e SS |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/errno.h> | |
cbfd6a21 | 22 | #include <linux/err.h> |
e0c9905e | 23 | #include <linux/interrupt.h> |
9df461ec | 24 | #include <linux/kernel.h> |
34cadd9c | 25 | #include <linux/pci.h> |
e0c9905e | 26 | #include <linux/platform_device.h> |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 28 | #include <linux/spi/spi.h> |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
3343b7a6 | 32 | #include <linux/clk.h> |
7d94a505 | 33 | #include <linux/pm_runtime.h> |
a3496855 | 34 | #include <linux/acpi.h> |
e0c9905e | 35 | |
cd7bed00 | 36 | #include "spi-pxa2xx.h" |
e0c9905e SS |
37 | |
38 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 39 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 40 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 41 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 42 | |
f1f640a9 VS |
43 | #define TIMOUT_DFLT 1000 |
44 | ||
b97c74bd NF |
45 | /* |
46 | * for testing SSCR1 changes that require SSP restart, basically | |
47 | * everything except the service and interrupt enables, the pxa270 developer | |
48 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
49 | * list, but the PXA255 dev man says all bits without really meaning the | |
50 | * service and interrupt enables | |
51 | */ | |
52 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 53 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
54 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
55 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
56 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
57 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 58 | |
e5262d05 WC |
59 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
60 | | QUARK_X1000_SSCR1_EFWR \ | |
61 | | QUARK_X1000_SSCR1_RFT \ | |
62 | | QUARK_X1000_SSCR1_TFT \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
64 | ||
624ea72e JN |
65 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
66 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
67 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
d0283eb2 JN |
68 | #define LPSS_CS_CONTROL_CS_SEL_SHIFT 8 |
69 | #define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT) | |
8b136baa JN |
70 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
71 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 72 | |
dccf7369 JN |
73 | struct lpss_config { |
74 | /* LPSS offset from drv_data->ioaddr */ | |
75 | unsigned offset; | |
76 | /* Register offsets from drv_data->lpss_base or -1 */ | |
77 | int reg_general; | |
78 | int reg_ssp; | |
79 | int reg_cs_ctrl; | |
8b136baa | 80 | int reg_capabilities; |
dccf7369 JN |
81 | /* FIFO thresholds */ |
82 | u32 rx_threshold; | |
83 | u32 tx_threshold_lo; | |
84 | u32 tx_threshold_hi; | |
85 | }; | |
86 | ||
87 | /* Keep these sorted with enum pxa_ssp_type */ | |
88 | static const struct lpss_config lpss_platforms[] = { | |
89 | { /* LPSS_LPT_SSP */ | |
90 | .offset = 0x800, | |
91 | .reg_general = 0x08, | |
92 | .reg_ssp = 0x0c, | |
93 | .reg_cs_ctrl = 0x18, | |
8b136baa | 94 | .reg_capabilities = -1, |
dccf7369 JN |
95 | .rx_threshold = 64, |
96 | .tx_threshold_lo = 160, | |
97 | .tx_threshold_hi = 224, | |
98 | }, | |
99 | { /* LPSS_BYT_SSP */ | |
100 | .offset = 0x400, | |
101 | .reg_general = 0x08, | |
102 | .reg_ssp = 0x0c, | |
103 | .reg_cs_ctrl = 0x18, | |
8b136baa | 104 | .reg_capabilities = -1, |
dccf7369 JN |
105 | .rx_threshold = 64, |
106 | .tx_threshold_lo = 160, | |
107 | .tx_threshold_hi = 224, | |
108 | }, | |
34cadd9c JN |
109 | { /* LPSS_SPT_SSP */ |
110 | .offset = 0x200, | |
111 | .reg_general = -1, | |
112 | .reg_ssp = 0x20, | |
113 | .reg_cs_ctrl = 0x24, | |
8b136baa | 114 | .reg_capabilities = 0xfc, |
34cadd9c JN |
115 | .rx_threshold = 1, |
116 | .tx_threshold_lo = 32, | |
117 | .tx_threshold_hi = 56, | |
118 | }, | |
b7c08cf8 JN |
119 | { /* LPSS_BXT_SSP */ |
120 | .offset = 0x200, | |
121 | .reg_general = -1, | |
122 | .reg_ssp = 0x20, | |
123 | .reg_cs_ctrl = 0x24, | |
124 | .reg_capabilities = 0xfc, | |
125 | .rx_threshold = 1, | |
126 | .tx_threshold_lo = 16, | |
127 | .tx_threshold_hi = 48, | |
128 | }, | |
dccf7369 JN |
129 | }; |
130 | ||
131 | static inline const struct lpss_config | |
132 | *lpss_get_config(const struct driver_data *drv_data) | |
133 | { | |
134 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
135 | } | |
136 | ||
a0d2642e MW |
137 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
138 | { | |
03fbf488 JN |
139 | switch (drv_data->ssp_type) { |
140 | case LPSS_LPT_SSP: | |
141 | case LPSS_BYT_SSP: | |
34cadd9c | 142 | case LPSS_SPT_SSP: |
b7c08cf8 | 143 | case LPSS_BXT_SSP: |
03fbf488 JN |
144 | return true; |
145 | default: | |
146 | return false; | |
147 | } | |
a0d2642e MW |
148 | } |
149 | ||
e5262d05 WC |
150 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
151 | { | |
152 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
153 | } | |
154 | ||
4fdb2424 WC |
155 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
156 | { | |
157 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
158 | case QUARK_X1000_SSP: |
159 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
160 | default: |
161 | return SSCR1_CHANGE_MASK; | |
162 | } | |
163 | } | |
164 | ||
165 | static u32 | |
166 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
167 | { | |
168 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
169 | case QUARK_X1000_SSP: |
170 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
171 | default: |
172 | return RX_THRESH_DFLT; | |
173 | } | |
174 | } | |
175 | ||
176 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
177 | { | |
4fdb2424 WC |
178 | u32 mask; |
179 | ||
180 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
181 | case QUARK_X1000_SSP: |
182 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
183 | break; | |
4fdb2424 WC |
184 | default: |
185 | mask = SSSR_TFL_MASK; | |
186 | break; | |
187 | } | |
188 | ||
c039dd27 | 189 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
190 | } |
191 | ||
192 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
193 | u32 *sccr1_reg) | |
194 | { | |
195 | u32 mask; | |
196 | ||
197 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
198 | case QUARK_X1000_SSP: |
199 | mask = QUARK_X1000_SSCR1_RFT; | |
200 | break; | |
4fdb2424 WC |
201 | default: |
202 | mask = SSCR1_RFT; | |
203 | break; | |
204 | } | |
205 | *sccr1_reg &= ~mask; | |
206 | } | |
207 | ||
208 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
209 | u32 *sccr1_reg, u32 threshold) | |
210 | { | |
211 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
212 | case QUARK_X1000_SSP: |
213 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
214 | break; | |
4fdb2424 WC |
215 | default: |
216 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
217 | break; | |
218 | } | |
219 | } | |
220 | ||
221 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
222 | u32 clk_div, u8 bits) | |
223 | { | |
224 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
225 | case QUARK_X1000_SSP: |
226 | return clk_div | |
227 | | QUARK_X1000_SSCR0_Motorola | |
228 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
229 | | SSCR0_SSE; | |
4fdb2424 WC |
230 | default: |
231 | return clk_div | |
232 | | SSCR0_Motorola | |
233 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
234 | | SSCR0_SSE | |
235 | | (bits > 16 ? SSCR0_EDSS : 0); | |
236 | } | |
237 | } | |
238 | ||
a0d2642e MW |
239 | /* |
240 | * Read and write LPSS SSP private registers. Caller must first check that | |
241 | * is_lpss_ssp() returns true before these can be called. | |
242 | */ | |
243 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
244 | { | |
245 | WARN_ON(!drv_data->lpss_base); | |
246 | return readl(drv_data->lpss_base + offset); | |
247 | } | |
248 | ||
249 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
250 | unsigned offset, u32 value) | |
251 | { | |
252 | WARN_ON(!drv_data->lpss_base); | |
253 | writel(value, drv_data->lpss_base + offset); | |
254 | } | |
255 | ||
256 | /* | |
257 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
258 | * @drv_data: pointer to the driver private data | |
259 | * | |
260 | * Perform LPSS SSP specific setup. This function must be called first if | |
261 | * one is going to use LPSS SSP private registers. | |
262 | */ | |
263 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
264 | { | |
dccf7369 JN |
265 | const struct lpss_config *config; |
266 | u32 value; | |
a0d2642e | 267 | |
dccf7369 JN |
268 | config = lpss_get_config(drv_data); |
269 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
270 | |
271 | /* Enable software chip select control */ | |
0e897218 | 272 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
273 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
274 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 275 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
276 | |
277 | /* Enable multiblock DMA transfers */ | |
1de70612 | 278 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 279 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 280 | |
82ba2c2a JN |
281 | if (config->reg_general >= 0) { |
282 | value = __lpss_ssp_read_priv(drv_data, | |
283 | config->reg_general); | |
624ea72e | 284 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
285 | __lpss_ssp_write_priv(drv_data, |
286 | config->reg_general, value); | |
287 | } | |
1de70612 | 288 | } |
a0d2642e MW |
289 | } |
290 | ||
291 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
292 | { | |
dccf7369 | 293 | const struct lpss_config *config; |
d0283eb2 | 294 | u32 value, cs; |
a0d2642e | 295 | |
dccf7369 JN |
296 | config = lpss_get_config(drv_data); |
297 | ||
298 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
d0283eb2 JN |
299 | if (enable) { |
300 | cs = drv_data->cur_msg->spi->chip_select; | |
301 | cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT; | |
302 | if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) { | |
303 | /* | |
304 | * When switching another chip select output active | |
305 | * the output must be selected first and wait 2 ssp_clk | |
306 | * cycles before changing state to active. Otherwise | |
307 | * a short glitch will occur on the previous chip | |
308 | * select since output select is latched but state | |
309 | * control is not. | |
310 | */ | |
311 | value &= ~LPSS_CS_CONTROL_CS_SEL_MASK; | |
312 | value |= cs; | |
313 | __lpss_ssp_write_priv(drv_data, | |
314 | config->reg_cs_ctrl, value); | |
315 | ndelay(1000000000 / | |
316 | (drv_data->master->max_speed_hz / 2)); | |
317 | } | |
624ea72e | 318 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
d0283eb2 | 319 | } else { |
624ea72e | 320 | value |= LPSS_CS_CONTROL_CS_HIGH; |
d0283eb2 | 321 | } |
dccf7369 | 322 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
323 | } |
324 | ||
a7bb3909 EM |
325 | static void cs_assert(struct driver_data *drv_data) |
326 | { | |
327 | struct chip_data *chip = drv_data->cur_chip; | |
328 | ||
2a8626a9 | 329 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 330 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
331 | return; |
332 | } | |
333 | ||
a7bb3909 EM |
334 | if (chip->cs_control) { |
335 | chip->cs_control(PXA2XX_CS_ASSERT); | |
336 | return; | |
337 | } | |
338 | ||
a0d2642e | 339 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 340 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
341 | return; |
342 | } | |
343 | ||
7566bcc7 JN |
344 | if (is_lpss_ssp(drv_data)) |
345 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
346 | } |
347 | ||
348 | static void cs_deassert(struct driver_data *drv_data) | |
349 | { | |
350 | struct chip_data *chip = drv_data->cur_chip; | |
351 | ||
2a8626a9 SAS |
352 | if (drv_data->ssp_type == CE4100_SSP) |
353 | return; | |
354 | ||
a7bb3909 | 355 | if (chip->cs_control) { |
2b2562d3 | 356 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
357 | return; |
358 | } | |
359 | ||
a0d2642e | 360 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 361 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
362 | return; |
363 | } | |
364 | ||
7566bcc7 JN |
365 | if (is_lpss_ssp(drv_data)) |
366 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
367 | } |
368 | ||
cd7bed00 | 369 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
370 | { |
371 | unsigned long limit = loops_per_jiffy << 1; | |
372 | ||
e0c9905e | 373 | do { |
c039dd27 JN |
374 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
375 | pxa2xx_spi_read(drv_data, SSDR); | |
376 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 377 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
378 | |
379 | return limit; | |
380 | } | |
381 | ||
8d94cc50 | 382 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 383 | { |
9708c121 | 384 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 385 | |
4fdb2424 | 386 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
387 | || (drv_data->tx == drv_data->tx_end)) |
388 | return 0; | |
389 | ||
c039dd27 | 390 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
391 | drv_data->tx += n_bytes; |
392 | ||
393 | return 1; | |
e0c9905e SS |
394 | } |
395 | ||
8d94cc50 | 396 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 397 | { |
9708c121 | 398 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 399 | |
c039dd27 JN |
400 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
401 | && (drv_data->rx < drv_data->rx_end)) { | |
402 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
403 | drv_data->rx += n_bytes; |
404 | } | |
8d94cc50 SS |
405 | |
406 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
407 | } |
408 | ||
8d94cc50 | 409 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 410 | { |
4fdb2424 | 411 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
412 | || (drv_data->tx == drv_data->tx_end)) |
413 | return 0; | |
414 | ||
c039dd27 | 415 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
416 | ++drv_data->tx; |
417 | ||
418 | return 1; | |
e0c9905e SS |
419 | } |
420 | ||
8d94cc50 | 421 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 422 | { |
c039dd27 JN |
423 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
424 | && (drv_data->rx < drv_data->rx_end)) { | |
425 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
426 | ++drv_data->rx; |
427 | } | |
8d94cc50 SS |
428 | |
429 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
430 | } |
431 | ||
8d94cc50 | 432 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 433 | { |
4fdb2424 | 434 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
435 | || (drv_data->tx == drv_data->tx_end)) |
436 | return 0; | |
437 | ||
c039dd27 | 438 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
439 | drv_data->tx += 2; |
440 | ||
441 | return 1; | |
e0c9905e SS |
442 | } |
443 | ||
8d94cc50 | 444 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 445 | { |
c039dd27 JN |
446 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
447 | && (drv_data->rx < drv_data->rx_end)) { | |
448 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
449 | drv_data->rx += 2; |
450 | } | |
8d94cc50 SS |
451 | |
452 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 453 | } |
8d94cc50 SS |
454 | |
455 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 456 | { |
4fdb2424 | 457 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
458 | || (drv_data->tx == drv_data->tx_end)) |
459 | return 0; | |
460 | ||
c039dd27 | 461 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
462 | drv_data->tx += 4; |
463 | ||
464 | return 1; | |
e0c9905e SS |
465 | } |
466 | ||
8d94cc50 | 467 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 468 | { |
c039dd27 JN |
469 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
470 | && (drv_data->rx < drv_data->rx_end)) { | |
471 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
472 | drv_data->rx += 4; |
473 | } | |
8d94cc50 SS |
474 | |
475 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
476 | } |
477 | ||
cd7bed00 | 478 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
479 | { |
480 | struct spi_message *msg = drv_data->cur_msg; | |
481 | struct spi_transfer *trans = drv_data->cur_transfer; | |
482 | ||
483 | /* Move to next transfer */ | |
484 | if (trans->transfer_list.next != &msg->transfers) { | |
485 | drv_data->cur_transfer = | |
486 | list_entry(trans->transfer_list.next, | |
487 | struct spi_transfer, | |
488 | transfer_list); | |
489 | return RUNNING_STATE; | |
490 | } else | |
491 | return DONE_STATE; | |
492 | } | |
493 | ||
e0c9905e | 494 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 495 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
496 | { |
497 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 498 | struct spi_message *msg; |
e0c9905e | 499 | |
5daa3ba0 SS |
500 | msg = drv_data->cur_msg; |
501 | drv_data->cur_msg = NULL; | |
502 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 503 | |
23e2c2aa | 504 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
505 | transfer_list); |
506 | ||
8423597d NF |
507 | /* Delay if requested before any change in chip select */ |
508 | if (last_transfer->delay_usecs) | |
509 | udelay(last_transfer->delay_usecs); | |
510 | ||
511 | /* Drop chip select UNLESS cs_change is true or we are returning | |
512 | * a message with an error, or next message is for another chip | |
513 | */ | |
e0c9905e | 514 | if (!last_transfer->cs_change) |
a7bb3909 | 515 | cs_deassert(drv_data); |
8423597d NF |
516 | else { |
517 | struct spi_message *next_msg; | |
518 | ||
519 | /* Holding of cs was hinted, but we need to make sure | |
520 | * the next message is for the same chip. Don't waste | |
521 | * time with the following tests unless this was hinted. | |
522 | * | |
523 | * We cannot postpone this until pump_messages, because | |
524 | * after calling msg->complete (below) the driver that | |
525 | * sent the current message could be unloaded, which | |
526 | * could invalidate the cs_control() callback... | |
527 | */ | |
528 | ||
529 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 530 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
531 | |
532 | /* see if the next and current messages point | |
533 | * to the same chip | |
534 | */ | |
535 | if (next_msg && next_msg->spi != msg->spi) | |
536 | next_msg = NULL; | |
537 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 538 | cs_deassert(drv_data); |
8423597d | 539 | } |
e0c9905e | 540 | |
a7bb3909 | 541 | drv_data->cur_chip = NULL; |
c957e8f0 | 542 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
543 | } |
544 | ||
579d3bb2 SAS |
545 | static void reset_sccr1(struct driver_data *drv_data) |
546 | { | |
579d3bb2 SAS |
547 | struct chip_data *chip = drv_data->cur_chip; |
548 | u32 sccr1_reg; | |
549 | ||
c039dd27 | 550 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
551 | sccr1_reg &= ~SSCR1_RFT; |
552 | sccr1_reg |= chip->threshold; | |
c039dd27 | 553 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
554 | } |
555 | ||
8d94cc50 | 556 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 557 | { |
8d94cc50 | 558 | /* Stop and reset SSP */ |
2a8626a9 | 559 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 560 | reset_sccr1(drv_data); |
2a8626a9 | 561 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 562 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 563 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
564 | pxa2xx_spi_write(drv_data, SSCR0, |
565 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 566 | |
8d94cc50 | 567 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 568 | |
8d94cc50 SS |
569 | drv_data->cur_msg->state = ERROR_STATE; |
570 | tasklet_schedule(&drv_data->pump_transfers); | |
571 | } | |
5daa3ba0 | 572 | |
8d94cc50 SS |
573 | static void int_transfer_complete(struct driver_data *drv_data) |
574 | { | |
8d94cc50 | 575 | /* Stop SSP */ |
2a8626a9 | 576 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 577 | reset_sccr1(drv_data); |
2a8626a9 | 578 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 579 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 580 | |
25985edc | 581 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
582 | drv_data->cur_msg->actual_length += drv_data->len - |
583 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 584 | |
8423597d NF |
585 | /* Transfer delays and chip select release are |
586 | * handled in pump_transfers or giveback | |
587 | */ | |
e0c9905e | 588 | |
8d94cc50 | 589 | /* Move to next transfer */ |
cd7bed00 | 590 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 591 | |
8d94cc50 SS |
592 | /* Schedule transfer tasklet */ |
593 | tasklet_schedule(&drv_data->pump_transfers); | |
594 | } | |
e0c9905e | 595 | |
8d94cc50 SS |
596 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
597 | { | |
c039dd27 JN |
598 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
599 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 600 | |
c039dd27 | 601 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 602 | |
8d94cc50 SS |
603 | if (irq_status & SSSR_ROR) { |
604 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
605 | return IRQ_HANDLED; | |
606 | } | |
e0c9905e | 607 | |
8d94cc50 | 608 | if (irq_status & SSSR_TINT) { |
c039dd27 | 609 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
610 | if (drv_data->read(drv_data)) { |
611 | int_transfer_complete(drv_data); | |
612 | return IRQ_HANDLED; | |
613 | } | |
614 | } | |
e0c9905e | 615 | |
8d94cc50 SS |
616 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
617 | do { | |
618 | if (drv_data->read(drv_data)) { | |
619 | int_transfer_complete(drv_data); | |
620 | return IRQ_HANDLED; | |
621 | } | |
622 | } while (drv_data->write(drv_data)); | |
e0c9905e | 623 | |
8d94cc50 SS |
624 | if (drv_data->read(drv_data)) { |
625 | int_transfer_complete(drv_data); | |
626 | return IRQ_HANDLED; | |
627 | } | |
e0c9905e | 628 | |
8d94cc50 | 629 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
630 | u32 bytes_left; |
631 | u32 sccr1_reg; | |
632 | ||
c039dd27 | 633 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
634 | sccr1_reg &= ~SSCR1_TIE; |
635 | ||
636 | /* | |
637 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 638 | * remaining RX bytes. |
579d3bb2 | 639 | */ |
2a8626a9 | 640 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 641 | u32 rx_thre; |
579d3bb2 | 642 | |
4fdb2424 | 643 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
644 | |
645 | bytes_left = drv_data->rx_end - drv_data->rx; | |
646 | switch (drv_data->n_bytes) { | |
647 | case 4: | |
648 | bytes_left >>= 1; | |
649 | case 2: | |
650 | bytes_left >>= 1; | |
8d94cc50 | 651 | } |
579d3bb2 | 652 | |
4fdb2424 WC |
653 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
654 | if (rx_thre > bytes_left) | |
655 | rx_thre = bytes_left; | |
579d3bb2 | 656 | |
4fdb2424 | 657 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 658 | } |
c039dd27 | 659 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
660 | } |
661 | ||
5daa3ba0 SS |
662 | /* We did something */ |
663 | return IRQ_HANDLED; | |
e0c9905e SS |
664 | } |
665 | ||
7d12e780 | 666 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 667 | { |
c7bec5ab | 668 | struct driver_data *drv_data = dev_id; |
7d94a505 | 669 | u32 sccr1_reg; |
49cbb1e0 SAS |
670 | u32 mask = drv_data->mask_sr; |
671 | u32 status; | |
672 | ||
7d94a505 MW |
673 | /* |
674 | * The IRQ might be shared with other peripherals so we must first | |
675 | * check that are we RPM suspended or not. If we are we assume that | |
676 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
677 | * interrupt is enabled). | |
678 | */ | |
679 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
680 | return IRQ_NONE; | |
681 | ||
269e4a41 MW |
682 | /* |
683 | * If the device is not yet in RPM suspended state and we get an | |
684 | * interrupt that is meant for another device, check if status bits | |
685 | * are all set to one. That means that the device is already | |
686 | * powered off. | |
687 | */ | |
c039dd27 | 688 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
689 | if (status == ~0) |
690 | return IRQ_NONE; | |
691 | ||
c039dd27 | 692 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
693 | |
694 | /* Ignore possible writes if we don't need to write */ | |
695 | if (!(sccr1_reg & SSCR1_TIE)) | |
696 | mask &= ~SSSR_TFS; | |
697 | ||
02bc933e TJN |
698 | /* Ignore RX timeout interrupt if it is disabled */ |
699 | if (!(sccr1_reg & SSCR1_TINTE)) | |
700 | mask &= ~SSSR_TINT; | |
701 | ||
49cbb1e0 SAS |
702 | if (!(status & mask)) |
703 | return IRQ_NONE; | |
e0c9905e SS |
704 | |
705 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 706 | |
c039dd27 JN |
707 | pxa2xx_spi_write(drv_data, SSCR0, |
708 | pxa2xx_spi_read(drv_data, SSCR0) | |
709 | & ~SSCR0_SSE); | |
710 | pxa2xx_spi_write(drv_data, SSCR1, | |
711 | pxa2xx_spi_read(drv_data, SSCR1) | |
712 | & ~drv_data->int_cr1); | |
2a8626a9 | 713 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 714 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 715 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 716 | |
f6bd03a7 JN |
717 | dev_err(&drv_data->pdev->dev, |
718 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 719 | |
e0c9905e SS |
720 | /* Never fail */ |
721 | return IRQ_HANDLED; | |
722 | } | |
723 | ||
724 | return drv_data->transfer_handler(drv_data); | |
725 | } | |
726 | ||
e5262d05 | 727 | /* |
9df461ec AS |
728 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
729 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
730 | * | |
731 | * There are formulas to get baud rate value for given input frequency and | |
732 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
733 | * | |
734 | * Fsys = 200MHz | |
735 | * | |
736 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
737 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
738 | * | |
739 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
740 | * SCR is in range 0 .. 255 | |
741 | * | |
742 | * Divisor = 5^i * 2^j * 2 * k | |
743 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
744 | * j = [0, 23] j = 0 iff i = 1 | |
745 | * k = [1, 256] | |
746 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
747 | * | |
748 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
749 | * are: | |
750 | * Case 1: 2^n, n = [0, 23] | |
751 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
752 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
753 | * | |
754 | * In all cases the lowest possible value is better. | |
755 | * | |
756 | * The function calculates parameters for all cases and chooses the one closest | |
757 | * to the asked baud rate. | |
e5262d05 | 758 | */ |
9df461ec AS |
759 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
760 | { | |
761 | unsigned long xtal = 200000000; | |
762 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
763 | see (2) */ | |
764 | /* case 3 */ | |
765 | unsigned long fref1 = fref / 2; /* case 1 */ | |
766 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
767 | unsigned long scale; | |
768 | unsigned long q, q1, q2; | |
769 | long r, r1, r2; | |
770 | u32 mul; | |
771 | ||
772 | /* Case 1 */ | |
773 | ||
774 | /* Set initial value for DDS_CLK_RATE */ | |
775 | mul = (1 << 24) >> 1; | |
776 | ||
777 | /* Calculate initial quot */ | |
3ad48062 | 778 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
779 | |
780 | /* Scale q1 if it's too big */ | |
781 | if (q1 > 256) { | |
782 | /* Scale q1 to range [1, 512] */ | |
783 | scale = fls_long(q1 - 1); | |
784 | if (scale > 9) { | |
785 | q1 >>= scale - 9; | |
786 | mul >>= scale - 9; | |
e5262d05 | 787 | } |
9df461ec AS |
788 | |
789 | /* Round the result if we have a remainder */ | |
790 | q1 += q1 & 1; | |
791 | } | |
792 | ||
793 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
794 | scale = __ffs(q1); | |
795 | q1 >>= scale; | |
796 | mul >>= scale; | |
797 | ||
798 | /* Get the remainder */ | |
799 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
800 | ||
801 | /* Case 2 */ | |
802 | ||
3ad48062 | 803 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
804 | r2 = abs(fref2 / q2 - rate); |
805 | ||
806 | /* | |
807 | * Choose the best between two: less remainder we have the better. We | |
808 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
809 | * hold only values 0 .. 255. | |
810 | */ | |
811 | if (r2 >= r1 || q2 > 256) { | |
812 | /* case 1 is better */ | |
813 | r = r1; | |
814 | q = q1; | |
815 | } else { | |
816 | /* case 2 is better */ | |
817 | r = r2; | |
818 | q = q2; | |
819 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
820 | } |
821 | ||
3ad48062 | 822 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
823 | if (fref / rate >= 80) { |
824 | u64 fssp; | |
825 | u32 m; | |
826 | ||
827 | /* Calculate initial quot */ | |
3ad48062 | 828 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
829 | m = (1 << 24) / q1; |
830 | ||
831 | /* Get the remainder */ | |
832 | fssp = (u64)fref * m; | |
833 | do_div(fssp, 1 << 24); | |
834 | r1 = abs(fssp - rate); | |
835 | ||
836 | /* Choose this one if it suits better */ | |
837 | if (r1 < r) { | |
838 | /* case 3 is better */ | |
839 | q = 1; | |
840 | mul = m; | |
841 | } | |
842 | } | |
e5262d05 | 843 | |
9df461ec AS |
844 | *dds = mul; |
845 | return q - 1; | |
e5262d05 WC |
846 | } |
847 | ||
3343b7a6 | 848 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 849 | { |
0eca7cf2 | 850 | unsigned long ssp_clk = drv_data->master->max_speed_hz; |
3343b7a6 MW |
851 | const struct ssp_device *ssp = drv_data->ssp; |
852 | ||
853 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 854 | |
2a8626a9 | 855 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 856 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 857 | else |
025ffe88 | 858 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 859 | } |
860 | ||
e5262d05 | 861 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 862 | int rate) |
e5262d05 | 863 | { |
d2c2f6a4 | 864 | struct chip_data *chip = drv_data->cur_chip; |
025ffe88 | 865 | unsigned int clk_div; |
e5262d05 WC |
866 | |
867 | switch (drv_data->ssp_type) { | |
868 | case QUARK_X1000_SSP: | |
9df461ec | 869 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 870 | break; |
e5262d05 | 871 | default: |
025ffe88 | 872 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 873 | break; |
e5262d05 | 874 | } |
025ffe88 | 875 | return clk_div << 8; |
e5262d05 WC |
876 | } |
877 | ||
e0c9905e SS |
878 | static void pump_transfers(unsigned long data) |
879 | { | |
880 | struct driver_data *drv_data = (struct driver_data *)data; | |
881 | struct spi_message *message = NULL; | |
882 | struct spi_transfer *transfer = NULL; | |
883 | struct spi_transfer *previous = NULL; | |
884 | struct chip_data *chip = NULL; | |
9708c121 SS |
885 | u32 clk_div = 0; |
886 | u8 bits = 0; | |
887 | u32 speed = 0; | |
888 | u32 cr0; | |
8d94cc50 SS |
889 | u32 cr1; |
890 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
891 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 892 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
893 | |
894 | /* Get current state information */ | |
895 | message = drv_data->cur_msg; | |
896 | transfer = drv_data->cur_transfer; | |
897 | chip = drv_data->cur_chip; | |
898 | ||
899 | /* Handle for abort */ | |
900 | if (message->state == ERROR_STATE) { | |
901 | message->status = -EIO; | |
5daa3ba0 | 902 | giveback(drv_data); |
e0c9905e SS |
903 | return; |
904 | } | |
905 | ||
906 | /* Handle end of message */ | |
907 | if (message->state == DONE_STATE) { | |
908 | message->status = 0; | |
5daa3ba0 | 909 | giveback(drv_data); |
e0c9905e SS |
910 | return; |
911 | } | |
912 | ||
8423597d | 913 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
914 | if (message->state == RUNNING_STATE) { |
915 | previous = list_entry(transfer->transfer_list.prev, | |
916 | struct spi_transfer, | |
917 | transfer_list); | |
918 | if (previous->delay_usecs) | |
919 | udelay(previous->delay_usecs); | |
8423597d NF |
920 | |
921 | /* Drop chip select only if cs_change is requested */ | |
922 | if (previous->cs_change) | |
a7bb3909 | 923 | cs_deassert(drv_data); |
e0c9905e SS |
924 | } |
925 | ||
cd7bed00 MW |
926 | /* Check if we can DMA this transfer */ |
927 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
928 | |
929 | /* reject already-mapped transfers; PIO won't always work */ | |
930 | if (message->is_dma_mapped | |
931 | || transfer->rx_dma || transfer->tx_dma) { | |
932 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
933 | "pump_transfers: mapped transfer length of " |
934 | "%u is greater than %d\n", | |
7e964455 NF |
935 | transfer->len, MAX_DMA_LEN); |
936 | message->status = -EINVAL; | |
937 | giveback(drv_data); | |
938 | return; | |
939 | } | |
940 | ||
941 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
942 | dev_warn_ratelimited(&message->spi->dev, |
943 | "pump_transfers: DMA disabled for transfer length %ld " | |
944 | "greater than %d\n", | |
945 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
946 | } |
947 | ||
e0c9905e | 948 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 949 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
950 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
951 | message->status = -EIO; | |
5daa3ba0 | 952 | giveback(drv_data); |
e0c9905e SS |
953 | return; |
954 | } | |
9708c121 | 955 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
956 | drv_data->tx = (void *)transfer->tx_buf; |
957 | drv_data->tx_end = drv_data->tx + transfer->len; | |
958 | drv_data->rx = transfer->rx_buf; | |
959 | drv_data->rx_end = drv_data->rx + transfer->len; | |
960 | drv_data->rx_dma = transfer->rx_dma; | |
961 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 962 | drv_data->len = transfer->len; |
e0c9905e SS |
963 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
964 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
965 | |
966 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
967 | bits = transfer->bits_per_word; |
968 | speed = transfer->speed_hz; | |
969 | ||
d2c2f6a4 | 970 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
971 | |
972 | if (bits <= 8) { | |
973 | drv_data->n_bytes = 1; | |
974 | drv_data->read = drv_data->read != null_reader ? | |
975 | u8_reader : null_reader; | |
976 | drv_data->write = drv_data->write != null_writer ? | |
977 | u8_writer : null_writer; | |
978 | } else if (bits <= 16) { | |
979 | drv_data->n_bytes = 2; | |
980 | drv_data->read = drv_data->read != null_reader ? | |
981 | u16_reader : null_reader; | |
982 | drv_data->write = drv_data->write != null_writer ? | |
983 | u16_writer : null_writer; | |
984 | } else if (bits <= 32) { | |
985 | drv_data->n_bytes = 4; | |
986 | drv_data->read = drv_data->read != null_reader ? | |
987 | u32_reader : null_reader; | |
988 | drv_data->write = drv_data->write != null_writer ? | |
989 | u32_writer : null_writer; | |
9708c121 | 990 | } |
196b0e2c JN |
991 | /* |
992 | * if bits/word is changed in dma mode, then must check the | |
993 | * thresholds and burst also | |
994 | */ | |
995 | if (chip->enable_dma) { | |
996 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
997 | message->spi, | |
998 | bits, &dma_burst, | |
999 | &dma_thresh)) | |
1000 | dev_warn_ratelimited(&message->spi->dev, | |
1001 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
9708c121 SS |
1002 | } |
1003 | ||
d74c4b1c | 1004 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
196b0e2c | 1005 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
d74c4b1c AS |
1006 | if (!pxa25x_ssp_comp(drv_data)) |
1007 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
1008 | drv_data->master->max_speed_hz | |
1009 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), | |
1010 | chip->enable_dma ? "DMA" : "PIO"); | |
1011 | else | |
1012 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
1013 | drv_data->master->max_speed_hz / 2 | |
1014 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), | |
1015 | chip->enable_dma ? "DMA" : "PIO"); | |
9708c121 | 1016 | |
e0c9905e SS |
1017 | message->state = RUNNING_STATE; |
1018 | ||
7e964455 | 1019 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
1020 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
1021 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 1022 | if (drv_data->dma_mapped) { |
e0c9905e SS |
1023 | |
1024 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1025 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1026 | ||
1027 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 1028 | |
8d94cc50 SS |
1029 | /* Clear status and start DMA engine */ |
1030 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1031 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1032 | |
1033 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1034 | } else { |
1035 | /* Ensure we have the correct interrupt handler */ | |
1036 | drv_data->transfer_handler = interrupt_transfer; | |
1037 | ||
8d94cc50 SS |
1038 | /* Clear status */ |
1039 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1040 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1041 | } |
1042 | ||
a0d2642e | 1043 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1044 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1045 | != chip->lpss_rx_threshold) | |
1046 | pxa2xx_spi_write(drv_data, SSIRF, | |
1047 | chip->lpss_rx_threshold); | |
1048 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1049 | != chip->lpss_tx_threshold) | |
1050 | pxa2xx_spi_write(drv_data, SSITF, | |
1051 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1052 | } |
1053 | ||
e5262d05 | 1054 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1055 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1056 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1057 | |
8d94cc50 | 1058 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1059 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1060 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1061 | != (cr1 & change_mask)) { | |
b97c74bd | 1062 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1063 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1064 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1065 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1066 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1067 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1068 | /* restart the SSP */ |
c039dd27 | 1069 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1070 | |
8d94cc50 | 1071 | } else { |
2a8626a9 | 1072 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1073 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1074 | } |
b97c74bd | 1075 | |
a7bb3909 | 1076 | cs_assert(drv_data); |
b97c74bd NF |
1077 | |
1078 | /* after chip select, release the data by enabling service | |
1079 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1080 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1081 | } |
1082 | ||
7f86bde9 MW |
1083 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1084 | struct spi_message *msg) | |
e0c9905e | 1085 | { |
7f86bde9 | 1086 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1087 | |
7f86bde9 | 1088 | drv_data->cur_msg = msg; |
e0c9905e SS |
1089 | /* Initial message state*/ |
1090 | drv_data->cur_msg->state = START_STATE; | |
1091 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1092 | struct spi_transfer, | |
1093 | transfer_list); | |
1094 | ||
8d94cc50 SS |
1095 | /* prepare to setup the SSP, in pump_transfers, using the per |
1096 | * chip configuration */ | |
e0c9905e | 1097 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1098 | |
1099 | /* Mark as busy and launch transfers */ | |
1100 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1101 | return 0; |
1102 | } | |
1103 | ||
7d94a505 MW |
1104 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1105 | { | |
1106 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1107 | ||
1108 | /* Disable the SSP now */ | |
c039dd27 JN |
1109 | pxa2xx_spi_write(drv_data, SSCR0, |
1110 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1111 | |
7d94a505 MW |
1112 | return 0; |
1113 | } | |
1114 | ||
a7bb3909 EM |
1115 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1116 | struct pxa2xx_spi_chip *chip_info) | |
1117 | { | |
1118 | int err = 0; | |
1119 | ||
1120 | if (chip == NULL || chip_info == NULL) | |
1121 | return 0; | |
1122 | ||
1123 | /* NOTE: setup() can be called multiple times, possibly with | |
1124 | * different chip_info, release previously requested GPIO | |
1125 | */ | |
1126 | if (gpio_is_valid(chip->gpio_cs)) | |
1127 | gpio_free(chip->gpio_cs); | |
1128 | ||
1129 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1130 | if (chip_info->cs_control) { | |
1131 | chip->cs_control = chip_info->cs_control; | |
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1136 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1137 | if (err) { | |
f6bd03a7 JN |
1138 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1139 | chip_info->gpio_cs); | |
a7bb3909 EM |
1140 | return err; |
1141 | } | |
1142 | ||
1143 | chip->gpio_cs = chip_info->gpio_cs; | |
1144 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1145 | ||
1146 | err = gpio_direction_output(chip->gpio_cs, | |
1147 | !chip->gpio_cs_inverted); | |
1148 | } | |
1149 | ||
1150 | return err; | |
1151 | } | |
1152 | ||
e0c9905e SS |
1153 | static int setup(struct spi_device *spi) |
1154 | { | |
1155 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1156 | struct chip_data *chip; | |
dccf7369 | 1157 | const struct lpss_config *config; |
e0c9905e | 1158 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a0d2642e MW |
1159 | uint tx_thres, tx_hi_thres, rx_thres; |
1160 | ||
e5262d05 WC |
1161 | switch (drv_data->ssp_type) { |
1162 | case QUARK_X1000_SSP: | |
1163 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1164 | tx_hi_thres = 0; | |
1165 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1166 | break; | |
03fbf488 JN |
1167 | case LPSS_LPT_SSP: |
1168 | case LPSS_BYT_SSP: | |
34cadd9c | 1169 | case LPSS_SPT_SSP: |
b7c08cf8 | 1170 | case LPSS_BXT_SSP: |
dccf7369 JN |
1171 | config = lpss_get_config(drv_data); |
1172 | tx_thres = config->tx_threshold_lo; | |
1173 | tx_hi_thres = config->tx_threshold_hi; | |
1174 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1175 | break; |
1176 | default: | |
a0d2642e MW |
1177 | tx_thres = TX_THRESH_DFLT; |
1178 | tx_hi_thres = 0; | |
1179 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1180 | break; |
a0d2642e | 1181 | } |
e0c9905e | 1182 | |
8d94cc50 | 1183 | /* Only alloc on first setup */ |
e0c9905e | 1184 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1185 | if (!chip) { |
e0c9905e | 1186 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1187 | if (!chip) |
e0c9905e SS |
1188 | return -ENOMEM; |
1189 | ||
2a8626a9 SAS |
1190 | if (drv_data->ssp_type == CE4100_SSP) { |
1191 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1192 | dev_err(&spi->dev, |
1193 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1194 | kfree(chip); |
1195 | return -EINVAL; | |
1196 | } | |
1197 | ||
1198 | chip->frm = spi->chip_select; | |
1199 | } else | |
1200 | chip->gpio_cs = -1; | |
e0c9905e | 1201 | chip->enable_dma = 0; |
f1f640a9 | 1202 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1203 | } |
1204 | ||
8d94cc50 SS |
1205 | /* protocol drivers may change the chip settings, so... |
1206 | * if chip_info exists, use it */ | |
1207 | chip_info = spi->controller_data; | |
1208 | ||
e0c9905e | 1209 | /* chip_info isn't always needed */ |
8d94cc50 | 1210 | chip->cr1 = 0; |
e0c9905e | 1211 | if (chip_info) { |
f1f640a9 VS |
1212 | if (chip_info->timeout) |
1213 | chip->timeout = chip_info->timeout; | |
1214 | if (chip_info->tx_threshold) | |
1215 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1216 | if (chip_info->tx_hi_threshold) |
1217 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1218 | if (chip_info->rx_threshold) |
1219 | rx_thres = chip_info->rx_threshold; | |
1220 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1221 | chip->dma_threshold = 0; |
e0c9905e SS |
1222 | if (chip_info->enable_loopback) |
1223 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1224 | } else if (ACPI_HANDLE(&spi->dev)) { |
1225 | /* | |
1226 | * Slave devices enumerated from ACPI namespace don't | |
1227 | * usually have chip_info but we still might want to use | |
1228 | * DMA with them. | |
1229 | */ | |
1230 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1231 | } |
1232 | ||
a0d2642e MW |
1233 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1234 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1235 | | SSITF_TxHiThresh(tx_hi_thres); | |
1236 | ||
8d94cc50 SS |
1237 | /* set dma burst and threshold outside of chip_info path so that if |
1238 | * chip_info goes away after setting chip->enable_dma, the | |
1239 | * burst and threshold can still respond to changes in bits_per_word */ | |
1240 | if (chip->enable_dma) { | |
1241 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1242 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1243 | spi->bits_per_word, | |
8d94cc50 SS |
1244 | &chip->dma_burst_size, |
1245 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1246 | dev_warn(&spi->dev, |
1247 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1248 | } |
1249 | } | |
1250 | ||
e5262d05 WC |
1251 | switch (drv_data->ssp_type) { |
1252 | case QUARK_X1000_SSP: | |
1253 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1254 | & QUARK_X1000_SSCR1_RFT) | |
1255 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1256 | & QUARK_X1000_SSCR1_TFT); | |
1257 | break; | |
1258 | default: | |
1259 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1260 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1261 | break; | |
1262 | } | |
1263 | ||
7f6ee1ad JC |
1264 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1265 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1266 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1267 | |
b833172f MW |
1268 | if (spi->mode & SPI_LOOP) |
1269 | chip->cr1 |= SSCR1_LBM; | |
1270 | ||
e0c9905e SS |
1271 | if (spi->bits_per_word <= 8) { |
1272 | chip->n_bytes = 1; | |
e0c9905e SS |
1273 | chip->read = u8_reader; |
1274 | chip->write = u8_writer; | |
1275 | } else if (spi->bits_per_word <= 16) { | |
1276 | chip->n_bytes = 2; | |
e0c9905e SS |
1277 | chip->read = u16_reader; |
1278 | chip->write = u16_writer; | |
1279 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1280 | chip->n_bytes = 4; |
e0c9905e SS |
1281 | chip->read = u32_reader; |
1282 | chip->write = u32_writer; | |
e0c9905e SS |
1283 | } |
1284 | ||
1285 | spi_set_ctldata(spi, chip); | |
1286 | ||
2a8626a9 SAS |
1287 | if (drv_data->ssp_type == CE4100_SSP) |
1288 | return 0; | |
1289 | ||
a7bb3909 | 1290 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1291 | } |
1292 | ||
0ffa0285 | 1293 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1294 | { |
0ffa0285 | 1295 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1296 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1297 | |
7348d82a DR |
1298 | if (!chip) |
1299 | return; | |
1300 | ||
2a8626a9 | 1301 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1302 | gpio_free(chip->gpio_cs); |
1303 | ||
e0c9905e SS |
1304 | kfree(chip); |
1305 | } | |
1306 | ||
0db64215 | 1307 | #ifdef CONFIG_PCI |
a3496855 | 1308 | #ifdef CONFIG_ACPI |
03fbf488 | 1309 | |
8422ddf7 | 1310 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1311 | { "INT33C0", LPSS_LPT_SSP }, |
1312 | { "INT33C1", LPSS_LPT_SSP }, | |
1313 | { "INT3430", LPSS_LPT_SSP }, | |
1314 | { "INT3431", LPSS_LPT_SSP }, | |
1315 | { "80860F0E", LPSS_BYT_SSP }, | |
1316 | { "8086228E", LPSS_BYT_SSP }, | |
1317 | { }, | |
1318 | }; | |
1319 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1320 | ||
0db64215 JN |
1321 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) |
1322 | { | |
1323 | unsigned int devid; | |
1324 | int port_id = -1; | |
1325 | ||
1326 | if (adev && adev->pnp.unique_id && | |
1327 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1328 | port_id = devid; | |
1329 | return port_id; | |
1330 | } | |
1331 | #else /* !CONFIG_ACPI */ | |
1332 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1333 | { | |
1334 | return -1; | |
1335 | } | |
1336 | #endif | |
1337 | ||
34cadd9c JN |
1338 | /* |
1339 | * PCI IDs of compound devices that integrate both host controller and private | |
1340 | * integrated DMA engine. Please note these are not used in module | |
1341 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1342 | */ | |
1343 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1344 | /* SPT-LP */ | |
1345 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1346 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1347 | /* SPT-H */ | |
1348 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1349 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
b7c08cf8 JN |
1350 | /* BXT */ |
1351 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, | |
1352 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1353 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
1354 | /* APL */ | |
1355 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1356 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1357 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
94e5c23d | 1358 | { }, |
34cadd9c JN |
1359 | }; |
1360 | ||
1361 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1362 | { | |
1363 | struct device *dev = param; | |
1364 | ||
1365 | if (dev != chan->device->dev->parent) | |
1366 | return false; | |
1367 | ||
1368 | return true; | |
1369 | } | |
1370 | ||
a3496855 | 1371 | static struct pxa2xx_spi_master * |
0db64215 | 1372 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1373 | { |
1374 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1375 | struct acpi_device *adev; |
1376 | struct ssp_device *ssp; | |
1377 | struct resource *res; | |
34cadd9c JN |
1378 | const struct acpi_device_id *adev_id = NULL; |
1379 | const struct pci_device_id *pcidev_id = NULL; | |
3b8b6d05 | 1380 | int type; |
a3496855 | 1381 | |
b9f6940a | 1382 | adev = ACPI_COMPANION(&pdev->dev); |
a3496855 | 1383 | |
34cadd9c JN |
1384 | if (dev_is_pci(pdev->dev.parent)) |
1385 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1386 | to_pci_dev(pdev->dev.parent)); | |
0db64215 | 1387 | else if (adev) |
34cadd9c JN |
1388 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
1389 | &pdev->dev); | |
0db64215 JN |
1390 | else |
1391 | return NULL; | |
34cadd9c JN |
1392 | |
1393 | if (adev_id) | |
1394 | type = (int)adev_id->driver_data; | |
1395 | else if (pcidev_id) | |
1396 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1397 | else |
1398 | return NULL; | |
1399 | ||
cc0ee987 | 1400 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1401 | if (!pdata) |
a3496855 | 1402 | return NULL; |
a3496855 MW |
1403 | |
1404 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1405 | if (!res) | |
1406 | return NULL; | |
1407 | ||
1408 | ssp = &pdata->ssp; | |
1409 | ||
1410 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1411 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1412 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1413 | return NULL; |
a3496855 | 1414 | |
34cadd9c JN |
1415 | if (pcidev_id) { |
1416 | pdata->tx_param = pdev->dev.parent; | |
1417 | pdata->rx_param = pdev->dev.parent; | |
1418 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1419 | } | |
1420 | ||
a3496855 MW |
1421 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1422 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1423 | ssp->type = type; |
a3496855 | 1424 | ssp->pdev = pdev; |
0db64215 | 1425 | ssp->port_id = pxa2xx_spi_get_port_id(adev); |
a3496855 MW |
1426 | |
1427 | pdata->num_chipselect = 1; | |
cddb339b | 1428 | pdata->enable_dma = true; |
a3496855 MW |
1429 | |
1430 | return pdata; | |
1431 | } | |
1432 | ||
0db64215 | 1433 | #else /* !CONFIG_PCI */ |
a3496855 | 1434 | static inline struct pxa2xx_spi_master * |
0db64215 | 1435 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1436 | { |
1437 | return NULL; | |
1438 | } | |
1439 | #endif | |
1440 | ||
fd4a319b | 1441 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1442 | { |
1443 | struct device *dev = &pdev->dev; | |
1444 | struct pxa2xx_spi_master *platform_info; | |
1445 | struct spi_master *master; | |
65a00a20 | 1446 | struct driver_data *drv_data; |
2f1a74e5 | 1447 | struct ssp_device *ssp; |
8b136baa | 1448 | const struct lpss_config *config; |
65a00a20 | 1449 | int status; |
c039dd27 | 1450 | u32 tmp; |
e0c9905e | 1451 | |
851bacf5 MW |
1452 | platform_info = dev_get_platdata(dev); |
1453 | if (!platform_info) { | |
0db64215 | 1454 | platform_info = pxa2xx_spi_init_pdata(pdev); |
a3496855 MW |
1455 | if (!platform_info) { |
1456 | dev_err(&pdev->dev, "missing platform data\n"); | |
1457 | return -ENODEV; | |
1458 | } | |
851bacf5 | 1459 | } |
e0c9905e | 1460 | |
baffe169 | 1461 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1462 | if (!ssp) |
1463 | ssp = &platform_info->ssp; | |
1464 | ||
1465 | if (!ssp->mmio_base) { | |
1466 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1467 | return -ENODEV; |
1468 | } | |
1469 | ||
757fe8d5 | 1470 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1471 | if (!master) { |
65a00a20 | 1472 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1473 | pxa_ssp_free(ssp); |
e0c9905e SS |
1474 | return -ENOMEM; |
1475 | } | |
1476 | drv_data = spi_master_get_devdata(master); | |
1477 | drv_data->master = master; | |
1478 | drv_data->master_info = platform_info; | |
1479 | drv_data->pdev = pdev; | |
2f1a74e5 | 1480 | drv_data->ssp = ssp; |
e0c9905e | 1481 | |
21486af0 | 1482 | master->dev.parent = &pdev->dev; |
21486af0 | 1483 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1484 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1485 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1486 | |
851bacf5 | 1487 | master->bus_num = ssp->port_id; |
7ad0ba91 | 1488 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1489 | master->cleanup = cleanup; |
1490 | master->setup = setup; | |
7f86bde9 | 1491 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1492 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1493 | master->auto_runtime_pm = true; |
e0c9905e | 1494 | |
2f1a74e5 | 1495 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1496 | |
2f1a74e5 | 1497 | drv_data->ioaddr = ssp->mmio_base; |
1498 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1499 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1500 | switch (drv_data->ssp_type) { |
1501 | case QUARK_X1000_SSP: | |
1502 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1503 | break; | |
1504 | default: | |
1505 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1506 | break; | |
1507 | } | |
1508 | ||
e0c9905e SS |
1509 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1510 | drv_data->dma_cr1 = 0; | |
1511 | drv_data->clear_sr = SSSR_ROR; | |
1512 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1513 | } else { | |
24778be2 | 1514 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1515 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1516 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1517 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1518 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1519 | } | |
1520 | ||
49cbb1e0 SAS |
1521 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1522 | drv_data); | |
e0c9905e | 1523 | if (status < 0) { |
65a00a20 | 1524 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1525 | goto out_error_master_alloc; |
1526 | } | |
1527 | ||
1528 | /* Setup DMA if requested */ | |
e0c9905e | 1529 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1530 | status = pxa2xx_spi_dma_setup(drv_data); |
1531 | if (status) { | |
cddb339b | 1532 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1533 | platform_info->enable_dma = false; |
e0c9905e | 1534 | } |
e0c9905e SS |
1535 | } |
1536 | ||
1537 | /* Enable SOC clock */ | |
3343b7a6 MW |
1538 | clk_prepare_enable(ssp->clk); |
1539 | ||
0eca7cf2 | 1540 | master->max_speed_hz = clk_get_rate(ssp->clk); |
e0c9905e SS |
1541 | |
1542 | /* Load default SSP configuration */ | |
c039dd27 | 1543 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1544 | switch (drv_data->ssp_type) { |
1545 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1546 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1547 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1548 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1549 | |
1550 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1551 | pxa2xx_spi_write(drv_data, SSCR0, |
1552 | QUARK_X1000_SSCR0_Motorola | |
1553 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1554 | break; |
1555 | default: | |
c039dd27 JN |
1556 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1557 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1558 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1559 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1560 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1561 | break; |
1562 | } | |
1563 | ||
2a8626a9 | 1564 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1565 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1566 | |
1567 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1568 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1569 | |
7566bcc7 JN |
1570 | if (is_lpss_ssp(drv_data)) |
1571 | lpss_ssp_setup(drv_data); | |
a0d2642e | 1572 | |
8b136baa JN |
1573 | if (is_lpss_ssp(drv_data)) { |
1574 | lpss_ssp_setup(drv_data); | |
1575 | config = lpss_get_config(drv_data); | |
1576 | if (config->reg_capabilities >= 0) { | |
1577 | tmp = __lpss_ssp_read_priv(drv_data, | |
1578 | config->reg_capabilities); | |
1579 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1580 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1581 | platform_info->num_chipselect = ffz(tmp); | |
1582 | } | |
1583 | } | |
1584 | master->num_chipselect = platform_info->num_chipselect; | |
1585 | ||
7f86bde9 MW |
1586 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1587 | (unsigned long)drv_data); | |
e0c9905e | 1588 | |
836d1a22 AO |
1589 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1590 | pm_runtime_use_autosuspend(&pdev->dev); | |
1591 | pm_runtime_set_active(&pdev->dev); | |
1592 | pm_runtime_enable(&pdev->dev); | |
1593 | ||
e0c9905e SS |
1594 | /* Register with the SPI framework */ |
1595 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1596 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1597 | if (status != 0) { |
1598 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1599 | goto out_error_clock_enabled; |
e0c9905e SS |
1600 | } |
1601 | ||
1602 | return status; | |
1603 | ||
e0c9905e | 1604 | out_error_clock_enabled: |
3343b7a6 | 1605 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1606 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1607 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1608 | |
1609 | out_error_master_alloc: | |
1610 | spi_master_put(master); | |
baffe169 | 1611 | pxa_ssp_free(ssp); |
e0c9905e SS |
1612 | return status; |
1613 | } | |
1614 | ||
1615 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1616 | { | |
1617 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1618 | struct ssp_device *ssp; |
e0c9905e SS |
1619 | |
1620 | if (!drv_data) | |
1621 | return 0; | |
51e911e2 | 1622 | ssp = drv_data->ssp; |
e0c9905e | 1623 | |
7d94a505 MW |
1624 | pm_runtime_get_sync(&pdev->dev); |
1625 | ||
e0c9905e | 1626 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1627 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1628 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1629 | |
1630 | /* Release DMA */ | |
cd7bed00 MW |
1631 | if (drv_data->master_info->enable_dma) |
1632 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1633 | |
7d94a505 MW |
1634 | pm_runtime_put_noidle(&pdev->dev); |
1635 | pm_runtime_disable(&pdev->dev); | |
1636 | ||
e0c9905e | 1637 | /* Release IRQ */ |
2f1a74e5 | 1638 | free_irq(ssp->irq, drv_data); |
1639 | ||
1640 | /* Release SSP */ | |
baffe169 | 1641 | pxa_ssp_free(ssp); |
e0c9905e | 1642 | |
e0c9905e SS |
1643 | return 0; |
1644 | } | |
1645 | ||
1646 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1647 | { | |
1648 | int status = 0; | |
1649 | ||
1650 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1651 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1652 | } | |
1653 | ||
382cebb0 | 1654 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1655 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1656 | { |
86d2593a | 1657 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1658 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1659 | int status = 0; |
1660 | ||
7f86bde9 | 1661 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1662 | if (status != 0) |
1663 | return status; | |
c039dd27 | 1664 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1665 | |
1666 | if (!pm_runtime_suspended(dev)) | |
1667 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1668 | |
1669 | return 0; | |
1670 | } | |
1671 | ||
86d2593a | 1672 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1673 | { |
86d2593a | 1674 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1675 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1676 | int status = 0; |
1677 | ||
1678 | /* Enable the SSP clock */ | |
2b9375b9 DES |
1679 | if (!pm_runtime_suspended(dev)) |
1680 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1681 | |
c50325f7 | 1682 | /* Restore LPSS private register bits */ |
48421adf JN |
1683 | if (is_lpss_ssp(drv_data)) |
1684 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1685 | |
e0c9905e | 1686 | /* Start the queue running */ |
7f86bde9 | 1687 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1688 | if (status != 0) { |
86d2593a | 1689 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1690 | return status; |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
7d94a505 MW |
1695 | #endif |
1696 | ||
ec833050 | 1697 | #ifdef CONFIG_PM |
7d94a505 MW |
1698 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1699 | { | |
1700 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1701 | ||
1702 | clk_disable_unprepare(drv_data->ssp->clk); | |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1707 | { | |
1708 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1709 | ||
1710 | clk_prepare_enable(drv_data->ssp->clk); | |
1711 | return 0; | |
1712 | } | |
1713 | #endif | |
86d2593a | 1714 | |
47145210 | 1715 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1716 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1717 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1718 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1719 | }; |
e0c9905e SS |
1720 | |
1721 | static struct platform_driver driver = { | |
1722 | .driver = { | |
86d2593a | 1723 | .name = "pxa2xx-spi", |
86d2593a | 1724 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1725 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1726 | }, |
fbd29a14 | 1727 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1728 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1729 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1730 | }; |
1731 | ||
1732 | static int __init pxa2xx_spi_init(void) | |
1733 | { | |
fbd29a14 | 1734 | return platform_driver_register(&driver); |
e0c9905e | 1735 | } |
5b61a749 | 1736 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1737 | |
1738 | static void __exit pxa2xx_spi_exit(void) | |
1739 | { | |
1740 | platform_driver_unregister(&driver); | |
1741 | } | |
1742 | module_exit(pxa2xx_spi_exit); |