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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
8b136baa | 16 | #include <linux/bitops.h> |
e0c9905e SS |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/errno.h> | |
cbfd6a21 | 22 | #include <linux/err.h> |
e0c9905e | 23 | #include <linux/interrupt.h> |
9df461ec | 24 | #include <linux/kernel.h> |
34cadd9c | 25 | #include <linux/pci.h> |
e0c9905e | 26 | #include <linux/platform_device.h> |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 28 | #include <linux/spi/spi.h> |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
3343b7a6 | 32 | #include <linux/clk.h> |
7d94a505 | 33 | #include <linux/pm_runtime.h> |
a3496855 | 34 | #include <linux/acpi.h> |
e0c9905e | 35 | |
cd7bed00 | 36 | #include "spi-pxa2xx.h" |
e0c9905e SS |
37 | |
38 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 39 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 40 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 41 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 42 | |
f1f640a9 VS |
43 | #define TIMOUT_DFLT 1000 |
44 | ||
b97c74bd NF |
45 | /* |
46 | * for testing SSCR1 changes that require SSP restart, basically | |
47 | * everything except the service and interrupt enables, the pxa270 developer | |
48 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
49 | * list, but the PXA255 dev man says all bits without really meaning the | |
50 | * service and interrupt enables | |
51 | */ | |
52 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 53 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
54 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
55 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
56 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
57 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 58 | |
e5262d05 WC |
59 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
60 | | QUARK_X1000_SSCR1_EFWR \ | |
61 | | QUARK_X1000_SSCR1_RFT \ | |
62 | | QUARK_X1000_SSCR1_TFT \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
64 | ||
624ea72e JN |
65 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
66 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
67 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
8b136baa JN |
68 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
69 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 70 | |
dccf7369 JN |
71 | struct lpss_config { |
72 | /* LPSS offset from drv_data->ioaddr */ | |
73 | unsigned offset; | |
74 | /* Register offsets from drv_data->lpss_base or -1 */ | |
75 | int reg_general; | |
76 | int reg_ssp; | |
77 | int reg_cs_ctrl; | |
8b136baa | 78 | int reg_capabilities; |
dccf7369 JN |
79 | /* FIFO thresholds */ |
80 | u32 rx_threshold; | |
81 | u32 tx_threshold_lo; | |
82 | u32 tx_threshold_hi; | |
c1e4a53c MW |
83 | /* Chip select control */ |
84 | unsigned cs_sel_shift; | |
85 | unsigned cs_sel_mask; | |
30f3a6ab | 86 | unsigned cs_num; |
dccf7369 JN |
87 | }; |
88 | ||
89 | /* Keep these sorted with enum pxa_ssp_type */ | |
90 | static const struct lpss_config lpss_platforms[] = { | |
91 | { /* LPSS_LPT_SSP */ | |
92 | .offset = 0x800, | |
93 | .reg_general = 0x08, | |
94 | .reg_ssp = 0x0c, | |
95 | .reg_cs_ctrl = 0x18, | |
8b136baa | 96 | .reg_capabilities = -1, |
dccf7369 JN |
97 | .rx_threshold = 64, |
98 | .tx_threshold_lo = 160, | |
99 | .tx_threshold_hi = 224, | |
100 | }, | |
101 | { /* LPSS_BYT_SSP */ | |
102 | .offset = 0x400, | |
103 | .reg_general = 0x08, | |
104 | .reg_ssp = 0x0c, | |
105 | .reg_cs_ctrl = 0x18, | |
8b136baa | 106 | .reg_capabilities = -1, |
dccf7369 JN |
107 | .rx_threshold = 64, |
108 | .tx_threshold_lo = 160, | |
109 | .tx_threshold_hi = 224, | |
110 | }, | |
30f3a6ab MW |
111 | { /* LPSS_BSW_SSP */ |
112 | .offset = 0x400, | |
113 | .reg_general = 0x08, | |
114 | .reg_ssp = 0x0c, | |
115 | .reg_cs_ctrl = 0x18, | |
116 | .reg_capabilities = -1, | |
117 | .rx_threshold = 64, | |
118 | .tx_threshold_lo = 160, | |
119 | .tx_threshold_hi = 224, | |
120 | .cs_sel_shift = 2, | |
121 | .cs_sel_mask = 1 << 2, | |
122 | .cs_num = 2, | |
123 | }, | |
34cadd9c JN |
124 | { /* LPSS_SPT_SSP */ |
125 | .offset = 0x200, | |
126 | .reg_general = -1, | |
127 | .reg_ssp = 0x20, | |
128 | .reg_cs_ctrl = 0x24, | |
66ec246e | 129 | .reg_capabilities = -1, |
34cadd9c JN |
130 | .rx_threshold = 1, |
131 | .tx_threshold_lo = 32, | |
132 | .tx_threshold_hi = 56, | |
133 | }, | |
b7c08cf8 JN |
134 | { /* LPSS_BXT_SSP */ |
135 | .offset = 0x200, | |
136 | .reg_general = -1, | |
137 | .reg_ssp = 0x20, | |
138 | .reg_cs_ctrl = 0x24, | |
139 | .reg_capabilities = 0xfc, | |
140 | .rx_threshold = 1, | |
141 | .tx_threshold_lo = 16, | |
142 | .tx_threshold_hi = 48, | |
c1e4a53c MW |
143 | .cs_sel_shift = 8, |
144 | .cs_sel_mask = 3 << 8, | |
b7c08cf8 | 145 | }, |
dccf7369 JN |
146 | }; |
147 | ||
148 | static inline const struct lpss_config | |
149 | *lpss_get_config(const struct driver_data *drv_data) | |
150 | { | |
151 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
152 | } | |
153 | ||
a0d2642e MW |
154 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
155 | { | |
03fbf488 JN |
156 | switch (drv_data->ssp_type) { |
157 | case LPSS_LPT_SSP: | |
158 | case LPSS_BYT_SSP: | |
30f3a6ab | 159 | case LPSS_BSW_SSP: |
34cadd9c | 160 | case LPSS_SPT_SSP: |
b7c08cf8 | 161 | case LPSS_BXT_SSP: |
03fbf488 JN |
162 | return true; |
163 | default: | |
164 | return false; | |
165 | } | |
a0d2642e MW |
166 | } |
167 | ||
e5262d05 WC |
168 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
169 | { | |
170 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
171 | } | |
172 | ||
4fdb2424 WC |
173 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
174 | { | |
175 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
176 | case QUARK_X1000_SSP: |
177 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
178 | default: |
179 | return SSCR1_CHANGE_MASK; | |
180 | } | |
181 | } | |
182 | ||
183 | static u32 | |
184 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
185 | { | |
186 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
187 | case QUARK_X1000_SSP: |
188 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
189 | default: |
190 | return RX_THRESH_DFLT; | |
191 | } | |
192 | } | |
193 | ||
194 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
195 | { | |
4fdb2424 WC |
196 | u32 mask; |
197 | ||
198 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
199 | case QUARK_X1000_SSP: |
200 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
201 | break; | |
4fdb2424 WC |
202 | default: |
203 | mask = SSSR_TFL_MASK; | |
204 | break; | |
205 | } | |
206 | ||
c039dd27 | 207 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
208 | } |
209 | ||
210 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
211 | u32 *sccr1_reg) | |
212 | { | |
213 | u32 mask; | |
214 | ||
215 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
216 | case QUARK_X1000_SSP: |
217 | mask = QUARK_X1000_SSCR1_RFT; | |
218 | break; | |
4fdb2424 WC |
219 | default: |
220 | mask = SSCR1_RFT; | |
221 | break; | |
222 | } | |
223 | *sccr1_reg &= ~mask; | |
224 | } | |
225 | ||
226 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
227 | u32 *sccr1_reg, u32 threshold) | |
228 | { | |
229 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
230 | case QUARK_X1000_SSP: |
231 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
232 | break; | |
4fdb2424 WC |
233 | default: |
234 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
235 | break; | |
236 | } | |
237 | } | |
238 | ||
239 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
240 | u32 clk_div, u8 bits) | |
241 | { | |
242 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
243 | case QUARK_X1000_SSP: |
244 | return clk_div | |
245 | | QUARK_X1000_SSCR0_Motorola | |
246 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
247 | | SSCR0_SSE; | |
4fdb2424 WC |
248 | default: |
249 | return clk_div | |
250 | | SSCR0_Motorola | |
251 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
252 | | SSCR0_SSE | |
253 | | (bits > 16 ? SSCR0_EDSS : 0); | |
254 | } | |
255 | } | |
256 | ||
a0d2642e MW |
257 | /* |
258 | * Read and write LPSS SSP private registers. Caller must first check that | |
259 | * is_lpss_ssp() returns true before these can be called. | |
260 | */ | |
261 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
262 | { | |
263 | WARN_ON(!drv_data->lpss_base); | |
264 | return readl(drv_data->lpss_base + offset); | |
265 | } | |
266 | ||
267 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
268 | unsigned offset, u32 value) | |
269 | { | |
270 | WARN_ON(!drv_data->lpss_base); | |
271 | writel(value, drv_data->lpss_base + offset); | |
272 | } | |
273 | ||
274 | /* | |
275 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
276 | * @drv_data: pointer to the driver private data | |
277 | * | |
278 | * Perform LPSS SSP specific setup. This function must be called first if | |
279 | * one is going to use LPSS SSP private registers. | |
280 | */ | |
281 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
282 | { | |
dccf7369 JN |
283 | const struct lpss_config *config; |
284 | u32 value; | |
a0d2642e | 285 | |
dccf7369 JN |
286 | config = lpss_get_config(drv_data); |
287 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
288 | |
289 | /* Enable software chip select control */ | |
0e897218 | 290 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
291 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
292 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 293 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
294 | |
295 | /* Enable multiblock DMA transfers */ | |
1de70612 | 296 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 297 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 298 | |
82ba2c2a JN |
299 | if (config->reg_general >= 0) { |
300 | value = __lpss_ssp_read_priv(drv_data, | |
301 | config->reg_general); | |
624ea72e | 302 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
303 | __lpss_ssp_write_priv(drv_data, |
304 | config->reg_general, value); | |
305 | } | |
1de70612 | 306 | } |
a0d2642e MW |
307 | } |
308 | ||
c1e4a53c MW |
309 | static void lpss_ssp_select_cs(struct driver_data *drv_data, |
310 | const struct lpss_config *config) | |
311 | { | |
312 | u32 value, cs; | |
313 | ||
314 | if (!config->cs_sel_mask) | |
315 | return; | |
316 | ||
317 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
318 | ||
319 | cs = drv_data->cur_msg->spi->chip_select; | |
320 | cs <<= config->cs_sel_shift; | |
321 | if (cs != (value & config->cs_sel_mask)) { | |
322 | /* | |
323 | * When switching another chip select output active the | |
324 | * output must be selected first and wait 2 ssp_clk cycles | |
325 | * before changing state to active. Otherwise a short | |
326 | * glitch will occur on the previous chip select since | |
327 | * output select is latched but state control is not. | |
328 | */ | |
329 | value &= ~config->cs_sel_mask; | |
330 | value |= cs; | |
331 | __lpss_ssp_write_priv(drv_data, | |
332 | config->reg_cs_ctrl, value); | |
333 | ndelay(1000000000 / | |
334 | (drv_data->master->max_speed_hz / 2)); | |
335 | } | |
336 | } | |
337 | ||
a0d2642e MW |
338 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) |
339 | { | |
dccf7369 | 340 | const struct lpss_config *config; |
c1e4a53c | 341 | u32 value; |
a0d2642e | 342 | |
dccf7369 JN |
343 | config = lpss_get_config(drv_data); |
344 | ||
c1e4a53c MW |
345 | if (enable) |
346 | lpss_ssp_select_cs(drv_data, config); | |
347 | ||
dccf7369 | 348 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
c1e4a53c | 349 | if (enable) |
624ea72e | 350 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
c1e4a53c | 351 | else |
624ea72e | 352 | value |= LPSS_CS_CONTROL_CS_HIGH; |
dccf7369 | 353 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
354 | } |
355 | ||
a7bb3909 EM |
356 | static void cs_assert(struct driver_data *drv_data) |
357 | { | |
358 | struct chip_data *chip = drv_data->cur_chip; | |
359 | ||
2a8626a9 | 360 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 361 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
362 | return; |
363 | } | |
364 | ||
a7bb3909 EM |
365 | if (chip->cs_control) { |
366 | chip->cs_control(PXA2XX_CS_ASSERT); | |
367 | return; | |
368 | } | |
369 | ||
a0d2642e | 370 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 371 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
372 | return; |
373 | } | |
374 | ||
7566bcc7 JN |
375 | if (is_lpss_ssp(drv_data)) |
376 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
377 | } |
378 | ||
379 | static void cs_deassert(struct driver_data *drv_data) | |
380 | { | |
381 | struct chip_data *chip = drv_data->cur_chip; | |
382 | ||
2a8626a9 SAS |
383 | if (drv_data->ssp_type == CE4100_SSP) |
384 | return; | |
385 | ||
a7bb3909 | 386 | if (chip->cs_control) { |
2b2562d3 | 387 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
388 | return; |
389 | } | |
390 | ||
a0d2642e | 391 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 392 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
393 | return; |
394 | } | |
395 | ||
7566bcc7 JN |
396 | if (is_lpss_ssp(drv_data)) |
397 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
398 | } |
399 | ||
cd7bed00 | 400 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
401 | { |
402 | unsigned long limit = loops_per_jiffy << 1; | |
403 | ||
e0c9905e | 404 | do { |
c039dd27 JN |
405 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
406 | pxa2xx_spi_read(drv_data, SSDR); | |
407 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 408 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
409 | |
410 | return limit; | |
411 | } | |
412 | ||
8d94cc50 | 413 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 414 | { |
9708c121 | 415 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 416 | |
4fdb2424 | 417 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
418 | || (drv_data->tx == drv_data->tx_end)) |
419 | return 0; | |
420 | ||
c039dd27 | 421 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
422 | drv_data->tx += n_bytes; |
423 | ||
424 | return 1; | |
e0c9905e SS |
425 | } |
426 | ||
8d94cc50 | 427 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 428 | { |
9708c121 | 429 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 430 | |
c039dd27 JN |
431 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
432 | && (drv_data->rx < drv_data->rx_end)) { | |
433 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
434 | drv_data->rx += n_bytes; |
435 | } | |
8d94cc50 SS |
436 | |
437 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
438 | } |
439 | ||
8d94cc50 | 440 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 441 | { |
4fdb2424 | 442 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
443 | || (drv_data->tx == drv_data->tx_end)) |
444 | return 0; | |
445 | ||
c039dd27 | 446 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
447 | ++drv_data->tx; |
448 | ||
449 | return 1; | |
e0c9905e SS |
450 | } |
451 | ||
8d94cc50 | 452 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 453 | { |
c039dd27 JN |
454 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
455 | && (drv_data->rx < drv_data->rx_end)) { | |
456 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
457 | ++drv_data->rx; |
458 | } | |
8d94cc50 SS |
459 | |
460 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
461 | } |
462 | ||
8d94cc50 | 463 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 464 | { |
4fdb2424 | 465 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
466 | || (drv_data->tx == drv_data->tx_end)) |
467 | return 0; | |
468 | ||
c039dd27 | 469 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
470 | drv_data->tx += 2; |
471 | ||
472 | return 1; | |
e0c9905e SS |
473 | } |
474 | ||
8d94cc50 | 475 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 476 | { |
c039dd27 JN |
477 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
478 | && (drv_data->rx < drv_data->rx_end)) { | |
479 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
480 | drv_data->rx += 2; |
481 | } | |
8d94cc50 SS |
482 | |
483 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 484 | } |
8d94cc50 SS |
485 | |
486 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 487 | { |
4fdb2424 | 488 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
489 | || (drv_data->tx == drv_data->tx_end)) |
490 | return 0; | |
491 | ||
c039dd27 | 492 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
493 | drv_data->tx += 4; |
494 | ||
495 | return 1; | |
e0c9905e SS |
496 | } |
497 | ||
8d94cc50 | 498 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 499 | { |
c039dd27 JN |
500 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
501 | && (drv_data->rx < drv_data->rx_end)) { | |
502 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
503 | drv_data->rx += 4; |
504 | } | |
8d94cc50 SS |
505 | |
506 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
507 | } |
508 | ||
cd7bed00 | 509 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
510 | { |
511 | struct spi_message *msg = drv_data->cur_msg; | |
512 | struct spi_transfer *trans = drv_data->cur_transfer; | |
513 | ||
514 | /* Move to next transfer */ | |
515 | if (trans->transfer_list.next != &msg->transfers) { | |
516 | drv_data->cur_transfer = | |
517 | list_entry(trans->transfer_list.next, | |
518 | struct spi_transfer, | |
519 | transfer_list); | |
520 | return RUNNING_STATE; | |
521 | } else | |
522 | return DONE_STATE; | |
523 | } | |
524 | ||
e0c9905e | 525 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 526 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
527 | { |
528 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 529 | struct spi_message *msg; |
7a8d44bc | 530 | unsigned long timeout; |
e0c9905e | 531 | |
5daa3ba0 SS |
532 | msg = drv_data->cur_msg; |
533 | drv_data->cur_msg = NULL; | |
534 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 535 | |
23e2c2aa | 536 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
537 | transfer_list); |
538 | ||
8423597d NF |
539 | /* Delay if requested before any change in chip select */ |
540 | if (last_transfer->delay_usecs) | |
541 | udelay(last_transfer->delay_usecs); | |
542 | ||
7a8d44bc JN |
543 | /* Wait until SSP becomes idle before deasserting the CS */ |
544 | timeout = jiffies + msecs_to_jiffies(10); | |
545 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && | |
546 | !time_after(jiffies, timeout)) | |
547 | cpu_relax(); | |
548 | ||
8423597d NF |
549 | /* Drop chip select UNLESS cs_change is true or we are returning |
550 | * a message with an error, or next message is for another chip | |
551 | */ | |
e0c9905e | 552 | if (!last_transfer->cs_change) |
a7bb3909 | 553 | cs_deassert(drv_data); |
8423597d NF |
554 | else { |
555 | struct spi_message *next_msg; | |
556 | ||
557 | /* Holding of cs was hinted, but we need to make sure | |
558 | * the next message is for the same chip. Don't waste | |
559 | * time with the following tests unless this was hinted. | |
560 | * | |
561 | * We cannot postpone this until pump_messages, because | |
562 | * after calling msg->complete (below) the driver that | |
563 | * sent the current message could be unloaded, which | |
564 | * could invalidate the cs_control() callback... | |
565 | */ | |
566 | ||
567 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 568 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
569 | |
570 | /* see if the next and current messages point | |
571 | * to the same chip | |
572 | */ | |
a52db659 CR |
573 | if ((next_msg && next_msg->spi != msg->spi) || |
574 | msg->state == ERROR_STATE) | |
a7bb3909 | 575 | cs_deassert(drv_data); |
8423597d | 576 | } |
e0c9905e | 577 | |
a7bb3909 | 578 | drv_data->cur_chip = NULL; |
c957e8f0 | 579 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
580 | } |
581 | ||
579d3bb2 SAS |
582 | static void reset_sccr1(struct driver_data *drv_data) |
583 | { | |
579d3bb2 SAS |
584 | struct chip_data *chip = drv_data->cur_chip; |
585 | u32 sccr1_reg; | |
586 | ||
c039dd27 | 587 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
152bc19e AS |
588 | switch (drv_data->ssp_type) { |
589 | case QUARK_X1000_SSP: | |
590 | sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; | |
591 | break; | |
592 | default: | |
593 | sccr1_reg &= ~SSCR1_RFT; | |
594 | break; | |
595 | } | |
579d3bb2 | 596 | sccr1_reg |= chip->threshold; |
c039dd27 | 597 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
598 | } |
599 | ||
8d94cc50 | 600 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 601 | { |
8d94cc50 | 602 | /* Stop and reset SSP */ |
2a8626a9 | 603 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 604 | reset_sccr1(drv_data); |
2a8626a9 | 605 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 606 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 607 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
608 | pxa2xx_spi_write(drv_data, SSCR0, |
609 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 610 | |
8d94cc50 | 611 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 612 | |
8d94cc50 SS |
613 | drv_data->cur_msg->state = ERROR_STATE; |
614 | tasklet_schedule(&drv_data->pump_transfers); | |
615 | } | |
5daa3ba0 | 616 | |
8d94cc50 SS |
617 | static void int_transfer_complete(struct driver_data *drv_data) |
618 | { | |
07550df0 | 619 | /* Clear and disable interrupts */ |
2a8626a9 | 620 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 621 | reset_sccr1(drv_data); |
2a8626a9 | 622 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 623 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 624 | |
25985edc | 625 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
626 | drv_data->cur_msg->actual_length += drv_data->len - |
627 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 628 | |
8423597d NF |
629 | /* Transfer delays and chip select release are |
630 | * handled in pump_transfers or giveback | |
631 | */ | |
e0c9905e | 632 | |
8d94cc50 | 633 | /* Move to next transfer */ |
cd7bed00 | 634 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 635 | |
8d94cc50 SS |
636 | /* Schedule transfer tasklet */ |
637 | tasklet_schedule(&drv_data->pump_transfers); | |
638 | } | |
e0c9905e | 639 | |
8d94cc50 SS |
640 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
641 | { | |
c039dd27 JN |
642 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
643 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 644 | |
c039dd27 | 645 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 646 | |
8d94cc50 SS |
647 | if (irq_status & SSSR_ROR) { |
648 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
649 | return IRQ_HANDLED; | |
650 | } | |
e0c9905e | 651 | |
8d94cc50 | 652 | if (irq_status & SSSR_TINT) { |
c039dd27 | 653 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
654 | if (drv_data->read(drv_data)) { |
655 | int_transfer_complete(drv_data); | |
656 | return IRQ_HANDLED; | |
657 | } | |
658 | } | |
e0c9905e | 659 | |
8d94cc50 SS |
660 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
661 | do { | |
662 | if (drv_data->read(drv_data)) { | |
663 | int_transfer_complete(drv_data); | |
664 | return IRQ_HANDLED; | |
665 | } | |
666 | } while (drv_data->write(drv_data)); | |
e0c9905e | 667 | |
8d94cc50 SS |
668 | if (drv_data->read(drv_data)) { |
669 | int_transfer_complete(drv_data); | |
670 | return IRQ_HANDLED; | |
671 | } | |
e0c9905e | 672 | |
8d94cc50 | 673 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
674 | u32 bytes_left; |
675 | u32 sccr1_reg; | |
676 | ||
c039dd27 | 677 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
678 | sccr1_reg &= ~SSCR1_TIE; |
679 | ||
680 | /* | |
681 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 682 | * remaining RX bytes. |
579d3bb2 | 683 | */ |
2a8626a9 | 684 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 685 | u32 rx_thre; |
579d3bb2 | 686 | |
4fdb2424 | 687 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
688 | |
689 | bytes_left = drv_data->rx_end - drv_data->rx; | |
690 | switch (drv_data->n_bytes) { | |
691 | case 4: | |
692 | bytes_left >>= 1; | |
693 | case 2: | |
694 | bytes_left >>= 1; | |
8d94cc50 | 695 | } |
579d3bb2 | 696 | |
4fdb2424 WC |
697 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
698 | if (rx_thre > bytes_left) | |
699 | rx_thre = bytes_left; | |
579d3bb2 | 700 | |
4fdb2424 | 701 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 702 | } |
c039dd27 | 703 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
704 | } |
705 | ||
5daa3ba0 SS |
706 | /* We did something */ |
707 | return IRQ_HANDLED; | |
e0c9905e SS |
708 | } |
709 | ||
7d12e780 | 710 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 711 | { |
c7bec5ab | 712 | struct driver_data *drv_data = dev_id; |
7d94a505 | 713 | u32 sccr1_reg; |
49cbb1e0 SAS |
714 | u32 mask = drv_data->mask_sr; |
715 | u32 status; | |
716 | ||
7d94a505 MW |
717 | /* |
718 | * The IRQ might be shared with other peripherals so we must first | |
719 | * check that are we RPM suspended or not. If we are we assume that | |
720 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
721 | * interrupt is enabled). | |
722 | */ | |
723 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
724 | return IRQ_NONE; | |
725 | ||
269e4a41 MW |
726 | /* |
727 | * If the device is not yet in RPM suspended state and we get an | |
728 | * interrupt that is meant for another device, check if status bits | |
729 | * are all set to one. That means that the device is already | |
730 | * powered off. | |
731 | */ | |
c039dd27 | 732 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
733 | if (status == ~0) |
734 | return IRQ_NONE; | |
735 | ||
c039dd27 | 736 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
737 | |
738 | /* Ignore possible writes if we don't need to write */ | |
739 | if (!(sccr1_reg & SSCR1_TIE)) | |
740 | mask &= ~SSSR_TFS; | |
741 | ||
02bc933e TJN |
742 | /* Ignore RX timeout interrupt if it is disabled */ |
743 | if (!(sccr1_reg & SSCR1_TINTE)) | |
744 | mask &= ~SSSR_TINT; | |
745 | ||
49cbb1e0 SAS |
746 | if (!(status & mask)) |
747 | return IRQ_NONE; | |
e0c9905e SS |
748 | |
749 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 750 | |
c039dd27 JN |
751 | pxa2xx_spi_write(drv_data, SSCR0, |
752 | pxa2xx_spi_read(drv_data, SSCR0) | |
753 | & ~SSCR0_SSE); | |
754 | pxa2xx_spi_write(drv_data, SSCR1, | |
755 | pxa2xx_spi_read(drv_data, SSCR1) | |
756 | & ~drv_data->int_cr1); | |
2a8626a9 | 757 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 758 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 759 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 760 | |
f6bd03a7 JN |
761 | dev_err(&drv_data->pdev->dev, |
762 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 763 | |
e0c9905e SS |
764 | /* Never fail */ |
765 | return IRQ_HANDLED; | |
766 | } | |
767 | ||
768 | return drv_data->transfer_handler(drv_data); | |
769 | } | |
770 | ||
e5262d05 | 771 | /* |
9df461ec AS |
772 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
773 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
774 | * | |
775 | * There are formulas to get baud rate value for given input frequency and | |
776 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
777 | * | |
778 | * Fsys = 200MHz | |
779 | * | |
780 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
781 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
782 | * | |
783 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
784 | * SCR is in range 0 .. 255 | |
785 | * | |
786 | * Divisor = 5^i * 2^j * 2 * k | |
787 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
788 | * j = [0, 23] j = 0 iff i = 1 | |
789 | * k = [1, 256] | |
790 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
791 | * | |
792 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
793 | * are: | |
794 | * Case 1: 2^n, n = [0, 23] | |
795 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
796 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
797 | * | |
798 | * In all cases the lowest possible value is better. | |
799 | * | |
800 | * The function calculates parameters for all cases and chooses the one closest | |
801 | * to the asked baud rate. | |
e5262d05 | 802 | */ |
9df461ec AS |
803 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
804 | { | |
805 | unsigned long xtal = 200000000; | |
806 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
807 | see (2) */ | |
808 | /* case 3 */ | |
809 | unsigned long fref1 = fref / 2; /* case 1 */ | |
810 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
811 | unsigned long scale; | |
812 | unsigned long q, q1, q2; | |
813 | long r, r1, r2; | |
814 | u32 mul; | |
815 | ||
816 | /* Case 1 */ | |
817 | ||
818 | /* Set initial value for DDS_CLK_RATE */ | |
819 | mul = (1 << 24) >> 1; | |
820 | ||
821 | /* Calculate initial quot */ | |
3ad48062 | 822 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
823 | |
824 | /* Scale q1 if it's too big */ | |
825 | if (q1 > 256) { | |
826 | /* Scale q1 to range [1, 512] */ | |
827 | scale = fls_long(q1 - 1); | |
828 | if (scale > 9) { | |
829 | q1 >>= scale - 9; | |
830 | mul >>= scale - 9; | |
e5262d05 | 831 | } |
9df461ec AS |
832 | |
833 | /* Round the result if we have a remainder */ | |
834 | q1 += q1 & 1; | |
835 | } | |
836 | ||
837 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
838 | scale = __ffs(q1); | |
839 | q1 >>= scale; | |
840 | mul >>= scale; | |
841 | ||
842 | /* Get the remainder */ | |
843 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
844 | ||
845 | /* Case 2 */ | |
846 | ||
3ad48062 | 847 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
848 | r2 = abs(fref2 / q2 - rate); |
849 | ||
850 | /* | |
851 | * Choose the best between two: less remainder we have the better. We | |
852 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
853 | * hold only values 0 .. 255. | |
854 | */ | |
855 | if (r2 >= r1 || q2 > 256) { | |
856 | /* case 1 is better */ | |
857 | r = r1; | |
858 | q = q1; | |
859 | } else { | |
860 | /* case 2 is better */ | |
861 | r = r2; | |
862 | q = q2; | |
863 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
864 | } |
865 | ||
3ad48062 | 866 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
867 | if (fref / rate >= 80) { |
868 | u64 fssp; | |
869 | u32 m; | |
870 | ||
871 | /* Calculate initial quot */ | |
3ad48062 | 872 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
873 | m = (1 << 24) / q1; |
874 | ||
875 | /* Get the remainder */ | |
876 | fssp = (u64)fref * m; | |
877 | do_div(fssp, 1 << 24); | |
878 | r1 = abs(fssp - rate); | |
879 | ||
880 | /* Choose this one if it suits better */ | |
881 | if (r1 < r) { | |
882 | /* case 3 is better */ | |
883 | q = 1; | |
884 | mul = m; | |
885 | } | |
886 | } | |
e5262d05 | 887 | |
9df461ec AS |
888 | *dds = mul; |
889 | return q - 1; | |
e5262d05 WC |
890 | } |
891 | ||
3343b7a6 | 892 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 893 | { |
0eca7cf2 | 894 | unsigned long ssp_clk = drv_data->master->max_speed_hz; |
3343b7a6 MW |
895 | const struct ssp_device *ssp = drv_data->ssp; |
896 | ||
897 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 898 | |
2a8626a9 | 899 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 900 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 901 | else |
025ffe88 | 902 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 903 | } |
904 | ||
e5262d05 | 905 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 906 | int rate) |
e5262d05 | 907 | { |
d2c2f6a4 | 908 | struct chip_data *chip = drv_data->cur_chip; |
025ffe88 | 909 | unsigned int clk_div; |
e5262d05 WC |
910 | |
911 | switch (drv_data->ssp_type) { | |
912 | case QUARK_X1000_SSP: | |
9df461ec | 913 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 914 | break; |
e5262d05 | 915 | default: |
025ffe88 | 916 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 917 | break; |
e5262d05 | 918 | } |
025ffe88 | 919 | return clk_div << 8; |
e5262d05 WC |
920 | } |
921 | ||
b6ced294 JN |
922 | static bool pxa2xx_spi_can_dma(struct spi_master *master, |
923 | struct spi_device *spi, | |
924 | struct spi_transfer *xfer) | |
925 | { | |
926 | struct chip_data *chip = spi_get_ctldata(spi); | |
927 | ||
928 | return chip->enable_dma && | |
929 | xfer->len <= MAX_DMA_LEN && | |
930 | xfer->len >= chip->dma_burst_size; | |
931 | } | |
932 | ||
e0c9905e SS |
933 | static void pump_transfers(unsigned long data) |
934 | { | |
935 | struct driver_data *drv_data = (struct driver_data *)data; | |
2d7537d8 | 936 | struct spi_master *master = drv_data->master; |
e0c9905e SS |
937 | struct spi_message *message = NULL; |
938 | struct spi_transfer *transfer = NULL; | |
939 | struct spi_transfer *previous = NULL; | |
940 | struct chip_data *chip = NULL; | |
9708c121 SS |
941 | u32 clk_div = 0; |
942 | u8 bits = 0; | |
943 | u32 speed = 0; | |
944 | u32 cr0; | |
8d94cc50 SS |
945 | u32 cr1; |
946 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
947 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 948 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
7d1f1bf6 | 949 | int err; |
b6ced294 | 950 | int dma_mapped; |
e0c9905e SS |
951 | |
952 | /* Get current state information */ | |
953 | message = drv_data->cur_msg; | |
954 | transfer = drv_data->cur_transfer; | |
955 | chip = drv_data->cur_chip; | |
956 | ||
957 | /* Handle for abort */ | |
958 | if (message->state == ERROR_STATE) { | |
959 | message->status = -EIO; | |
5daa3ba0 | 960 | giveback(drv_data); |
e0c9905e SS |
961 | return; |
962 | } | |
963 | ||
964 | /* Handle end of message */ | |
965 | if (message->state == DONE_STATE) { | |
966 | message->status = 0; | |
5daa3ba0 | 967 | giveback(drv_data); |
e0c9905e SS |
968 | return; |
969 | } | |
970 | ||
8423597d | 971 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
972 | if (message->state == RUNNING_STATE) { |
973 | previous = list_entry(transfer->transfer_list.prev, | |
974 | struct spi_transfer, | |
975 | transfer_list); | |
976 | if (previous->delay_usecs) | |
977 | udelay(previous->delay_usecs); | |
8423597d NF |
978 | |
979 | /* Drop chip select only if cs_change is requested */ | |
980 | if (previous->cs_change) | |
a7bb3909 | 981 | cs_deassert(drv_data); |
e0c9905e SS |
982 | } |
983 | ||
cd7bed00 | 984 | /* Check if we can DMA this transfer */ |
b6ced294 | 985 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { |
7e964455 NF |
986 | |
987 | /* reject already-mapped transfers; PIO won't always work */ | |
988 | if (message->is_dma_mapped | |
989 | || transfer->rx_dma || transfer->tx_dma) { | |
990 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
991 | "pump_transfers: mapped transfer length of " |
992 | "%u is greater than %d\n", | |
7e964455 NF |
993 | transfer->len, MAX_DMA_LEN); |
994 | message->status = -EINVAL; | |
995 | giveback(drv_data); | |
996 | return; | |
997 | } | |
998 | ||
999 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
1000 | dev_warn_ratelimited(&message->spi->dev, |
1001 | "pump_transfers: DMA disabled for transfer length %ld " | |
1002 | "greater than %d\n", | |
1003 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
1004 | } |
1005 | ||
e0c9905e | 1006 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 1007 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
1008 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
1009 | message->status = -EIO; | |
5daa3ba0 | 1010 | giveback(drv_data); |
e0c9905e SS |
1011 | return; |
1012 | } | |
9708c121 | 1013 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
1014 | drv_data->tx = (void *)transfer->tx_buf; |
1015 | drv_data->tx_end = drv_data->tx + transfer->len; | |
1016 | drv_data->rx = transfer->rx_buf; | |
1017 | drv_data->rx_end = drv_data->rx + transfer->len; | |
cd7bed00 | 1018 | drv_data->len = transfer->len; |
e0c9905e SS |
1019 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
1020 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
1021 | |
1022 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
1023 | bits = transfer->bits_per_word; |
1024 | speed = transfer->speed_hz; | |
1025 | ||
d2c2f6a4 | 1026 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
1027 | |
1028 | if (bits <= 8) { | |
1029 | drv_data->n_bytes = 1; | |
1030 | drv_data->read = drv_data->read != null_reader ? | |
1031 | u8_reader : null_reader; | |
1032 | drv_data->write = drv_data->write != null_writer ? | |
1033 | u8_writer : null_writer; | |
1034 | } else if (bits <= 16) { | |
1035 | drv_data->n_bytes = 2; | |
1036 | drv_data->read = drv_data->read != null_reader ? | |
1037 | u16_reader : null_reader; | |
1038 | drv_data->write = drv_data->write != null_writer ? | |
1039 | u16_writer : null_writer; | |
1040 | } else if (bits <= 32) { | |
1041 | drv_data->n_bytes = 4; | |
1042 | drv_data->read = drv_data->read != null_reader ? | |
1043 | u32_reader : null_reader; | |
1044 | drv_data->write = drv_data->write != null_writer ? | |
1045 | u32_writer : null_writer; | |
9708c121 | 1046 | } |
196b0e2c JN |
1047 | /* |
1048 | * if bits/word is changed in dma mode, then must check the | |
1049 | * thresholds and burst also | |
1050 | */ | |
1051 | if (chip->enable_dma) { | |
1052 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
1053 | message->spi, | |
1054 | bits, &dma_burst, | |
1055 | &dma_thresh)) | |
1056 | dev_warn_ratelimited(&message->spi->dev, | |
1057 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
9708c121 SS |
1058 | } |
1059 | ||
e0c9905e SS |
1060 | message->state = RUNNING_STATE; |
1061 | ||
b6ced294 JN |
1062 | dma_mapped = master->can_dma && |
1063 | master->can_dma(master, message->spi, transfer) && | |
1064 | master->cur_msg_mapped; | |
1065 | if (dma_mapped) { | |
e0c9905e SS |
1066 | |
1067 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1068 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1069 | ||
7d1f1bf6 AS |
1070 | err = pxa2xx_spi_dma_prepare(drv_data, dma_burst); |
1071 | if (err) { | |
1072 | message->status = err; | |
1073 | giveback(drv_data); | |
1074 | return; | |
1075 | } | |
e0c9905e | 1076 | |
8d94cc50 SS |
1077 | /* Clear status and start DMA engine */ |
1078 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1079 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1080 | |
1081 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1082 | } else { |
1083 | /* Ensure we have the correct interrupt handler */ | |
1084 | drv_data->transfer_handler = interrupt_transfer; | |
1085 | ||
8d94cc50 SS |
1086 | /* Clear status */ |
1087 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1088 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1089 | } |
1090 | ||
ee03672d JN |
1091 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1092 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); | |
1093 | if (!pxa25x_ssp_comp(drv_data)) | |
1094 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
2d7537d8 | 1095 | master->max_speed_hz |
ee03672d | 1096 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), |
b6ced294 | 1097 | dma_mapped ? "DMA" : "PIO"); |
ee03672d JN |
1098 | else |
1099 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
2d7537d8 | 1100 | master->max_speed_hz / 2 |
ee03672d | 1101 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
b6ced294 | 1102 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1103 | |
a0d2642e | 1104 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1105 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1106 | != chip->lpss_rx_threshold) | |
1107 | pxa2xx_spi_write(drv_data, SSIRF, | |
1108 | chip->lpss_rx_threshold); | |
1109 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1110 | != chip->lpss_tx_threshold) | |
1111 | pxa2xx_spi_write(drv_data, SSITF, | |
1112 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1113 | } |
1114 | ||
e5262d05 | 1115 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1116 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1117 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1118 | |
8d94cc50 | 1119 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1120 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1121 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1122 | != (cr1 & change_mask)) { | |
b97c74bd | 1123 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1124 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1125 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1126 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1127 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1128 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1129 | /* restart the SSP */ |
c039dd27 | 1130 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1131 | |
8d94cc50 | 1132 | } else { |
2a8626a9 | 1133 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1134 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1135 | } |
b97c74bd | 1136 | |
a7bb3909 | 1137 | cs_assert(drv_data); |
b97c74bd NF |
1138 | |
1139 | /* after chip select, release the data by enabling service | |
1140 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1141 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1142 | } |
1143 | ||
7f86bde9 MW |
1144 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1145 | struct spi_message *msg) | |
e0c9905e | 1146 | { |
7f86bde9 | 1147 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1148 | |
7f86bde9 | 1149 | drv_data->cur_msg = msg; |
e0c9905e SS |
1150 | /* Initial message state*/ |
1151 | drv_data->cur_msg->state = START_STATE; | |
1152 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1153 | struct spi_transfer, | |
1154 | transfer_list); | |
1155 | ||
8d94cc50 SS |
1156 | /* prepare to setup the SSP, in pump_transfers, using the per |
1157 | * chip configuration */ | |
e0c9905e | 1158 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1159 | |
1160 | /* Mark as busy and launch transfers */ | |
1161 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1162 | return 0; |
1163 | } | |
1164 | ||
7d94a505 MW |
1165 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1166 | { | |
1167 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1168 | ||
1169 | /* Disable the SSP now */ | |
c039dd27 JN |
1170 | pxa2xx_spi_write(drv_data, SSCR0, |
1171 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1172 | |
7d94a505 MW |
1173 | return 0; |
1174 | } | |
1175 | ||
a7bb3909 EM |
1176 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1177 | struct pxa2xx_spi_chip *chip_info) | |
1178 | { | |
1179 | int err = 0; | |
1180 | ||
1181 | if (chip == NULL || chip_info == NULL) | |
1182 | return 0; | |
1183 | ||
1184 | /* NOTE: setup() can be called multiple times, possibly with | |
1185 | * different chip_info, release previously requested GPIO | |
1186 | */ | |
1187 | if (gpio_is_valid(chip->gpio_cs)) | |
1188 | gpio_free(chip->gpio_cs); | |
1189 | ||
1190 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1191 | if (chip_info->cs_control) { | |
1192 | chip->cs_control = chip_info->cs_control; | |
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1197 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1198 | if (err) { | |
f6bd03a7 JN |
1199 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1200 | chip_info->gpio_cs); | |
a7bb3909 EM |
1201 | return err; |
1202 | } | |
1203 | ||
1204 | chip->gpio_cs = chip_info->gpio_cs; | |
1205 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1206 | ||
1207 | err = gpio_direction_output(chip->gpio_cs, | |
1208 | !chip->gpio_cs_inverted); | |
1209 | } | |
1210 | ||
1211 | return err; | |
1212 | } | |
1213 | ||
e0c9905e SS |
1214 | static int setup(struct spi_device *spi) |
1215 | { | |
1216 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1217 | struct chip_data *chip; | |
dccf7369 | 1218 | const struct lpss_config *config; |
e0c9905e | 1219 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a0d2642e MW |
1220 | uint tx_thres, tx_hi_thres, rx_thres; |
1221 | ||
e5262d05 WC |
1222 | switch (drv_data->ssp_type) { |
1223 | case QUARK_X1000_SSP: | |
1224 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1225 | tx_hi_thres = 0; | |
1226 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1227 | break; | |
03fbf488 JN |
1228 | case LPSS_LPT_SSP: |
1229 | case LPSS_BYT_SSP: | |
30f3a6ab | 1230 | case LPSS_BSW_SSP: |
34cadd9c | 1231 | case LPSS_SPT_SSP: |
b7c08cf8 | 1232 | case LPSS_BXT_SSP: |
dccf7369 JN |
1233 | config = lpss_get_config(drv_data); |
1234 | tx_thres = config->tx_threshold_lo; | |
1235 | tx_hi_thres = config->tx_threshold_hi; | |
1236 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1237 | break; |
1238 | default: | |
a0d2642e MW |
1239 | tx_thres = TX_THRESH_DFLT; |
1240 | tx_hi_thres = 0; | |
1241 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1242 | break; |
a0d2642e | 1243 | } |
e0c9905e | 1244 | |
8d94cc50 | 1245 | /* Only alloc on first setup */ |
e0c9905e | 1246 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1247 | if (!chip) { |
e0c9905e | 1248 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1249 | if (!chip) |
e0c9905e SS |
1250 | return -ENOMEM; |
1251 | ||
2a8626a9 SAS |
1252 | if (drv_data->ssp_type == CE4100_SSP) { |
1253 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1254 | dev_err(&spi->dev, |
1255 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1256 | kfree(chip); |
1257 | return -EINVAL; | |
1258 | } | |
1259 | ||
1260 | chip->frm = spi->chip_select; | |
1261 | } else | |
1262 | chip->gpio_cs = -1; | |
c64e1265 | 1263 | chip->enable_dma = drv_data->master_info->enable_dma; |
f1f640a9 | 1264 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1265 | } |
1266 | ||
8d94cc50 SS |
1267 | /* protocol drivers may change the chip settings, so... |
1268 | * if chip_info exists, use it */ | |
1269 | chip_info = spi->controller_data; | |
1270 | ||
e0c9905e | 1271 | /* chip_info isn't always needed */ |
8d94cc50 | 1272 | chip->cr1 = 0; |
e0c9905e | 1273 | if (chip_info) { |
f1f640a9 VS |
1274 | if (chip_info->timeout) |
1275 | chip->timeout = chip_info->timeout; | |
1276 | if (chip_info->tx_threshold) | |
1277 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1278 | if (chip_info->tx_hi_threshold) |
1279 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1280 | if (chip_info->rx_threshold) |
1281 | rx_thres = chip_info->rx_threshold; | |
e0c9905e | 1282 | chip->dma_threshold = 0; |
e0c9905e SS |
1283 | if (chip_info->enable_loopback) |
1284 | chip->cr1 = SSCR1_LBM; | |
1285 | } | |
1286 | ||
a0d2642e MW |
1287 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1288 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1289 | | SSITF_TxHiThresh(tx_hi_thres); | |
1290 | ||
8d94cc50 SS |
1291 | /* set dma burst and threshold outside of chip_info path so that if |
1292 | * chip_info goes away after setting chip->enable_dma, the | |
1293 | * burst and threshold can still respond to changes in bits_per_word */ | |
1294 | if (chip->enable_dma) { | |
1295 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1296 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1297 | spi->bits_per_word, | |
8d94cc50 SS |
1298 | &chip->dma_burst_size, |
1299 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1300 | dev_warn(&spi->dev, |
1301 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1302 | } |
1303 | } | |
1304 | ||
e5262d05 WC |
1305 | switch (drv_data->ssp_type) { |
1306 | case QUARK_X1000_SSP: | |
1307 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1308 | & QUARK_X1000_SSCR1_RFT) | |
1309 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1310 | & QUARK_X1000_SSCR1_TFT); | |
1311 | break; | |
1312 | default: | |
1313 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1314 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1315 | break; | |
1316 | } | |
1317 | ||
7f6ee1ad JC |
1318 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1319 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1320 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1321 | |
b833172f MW |
1322 | if (spi->mode & SPI_LOOP) |
1323 | chip->cr1 |= SSCR1_LBM; | |
1324 | ||
e0c9905e SS |
1325 | if (spi->bits_per_word <= 8) { |
1326 | chip->n_bytes = 1; | |
e0c9905e SS |
1327 | chip->read = u8_reader; |
1328 | chip->write = u8_writer; | |
1329 | } else if (spi->bits_per_word <= 16) { | |
1330 | chip->n_bytes = 2; | |
e0c9905e SS |
1331 | chip->read = u16_reader; |
1332 | chip->write = u16_writer; | |
1333 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1334 | chip->n_bytes = 4; |
e0c9905e SS |
1335 | chip->read = u32_reader; |
1336 | chip->write = u32_writer; | |
e0c9905e SS |
1337 | } |
1338 | ||
1339 | spi_set_ctldata(spi, chip); | |
1340 | ||
2a8626a9 SAS |
1341 | if (drv_data->ssp_type == CE4100_SSP) |
1342 | return 0; | |
1343 | ||
a7bb3909 | 1344 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1345 | } |
1346 | ||
0ffa0285 | 1347 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1348 | { |
0ffa0285 | 1349 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1350 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1351 | |
7348d82a DR |
1352 | if (!chip) |
1353 | return; | |
1354 | ||
2a8626a9 | 1355 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1356 | gpio_free(chip->gpio_cs); |
1357 | ||
e0c9905e SS |
1358 | kfree(chip); |
1359 | } | |
1360 | ||
0db64215 | 1361 | #ifdef CONFIG_PCI |
a3496855 | 1362 | #ifdef CONFIG_ACPI |
03fbf488 | 1363 | |
8422ddf7 | 1364 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1365 | { "INT33C0", LPSS_LPT_SSP }, |
1366 | { "INT33C1", LPSS_LPT_SSP }, | |
1367 | { "INT3430", LPSS_LPT_SSP }, | |
1368 | { "INT3431", LPSS_LPT_SSP }, | |
1369 | { "80860F0E", LPSS_BYT_SSP }, | |
30f3a6ab | 1370 | { "8086228E", LPSS_BSW_SSP }, |
03fbf488 JN |
1371 | { }, |
1372 | }; | |
1373 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1374 | ||
0db64215 JN |
1375 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) |
1376 | { | |
1377 | unsigned int devid; | |
1378 | int port_id = -1; | |
1379 | ||
1380 | if (adev && adev->pnp.unique_id && | |
1381 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1382 | port_id = devid; | |
1383 | return port_id; | |
1384 | } | |
1385 | #else /* !CONFIG_ACPI */ | |
1386 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1387 | { | |
1388 | return -1; | |
1389 | } | |
1390 | #endif | |
1391 | ||
34cadd9c JN |
1392 | /* |
1393 | * PCI IDs of compound devices that integrate both host controller and private | |
1394 | * integrated DMA engine. Please note these are not used in module | |
1395 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1396 | */ | |
1397 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1398 | /* SPT-LP */ | |
1399 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1400 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1401 | /* SPT-H */ | |
1402 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1403 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
704d2b07 MW |
1404 | /* KBL-H */ |
1405 | { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, | |
1406 | { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, | |
c1b03f11 | 1407 | /* BXT A-Step */ |
b7c08cf8 JN |
1408 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, |
1409 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1410 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
c1b03f11 JN |
1411 | /* BXT B-Step */ |
1412 | { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, | |
1413 | { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, | |
1414 | { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, | |
b7c08cf8 JN |
1415 | /* APL */ |
1416 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1417 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1418 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
94e5c23d | 1419 | { }, |
34cadd9c JN |
1420 | }; |
1421 | ||
1422 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1423 | { | |
1424 | struct device *dev = param; | |
1425 | ||
1426 | if (dev != chan->device->dev->parent) | |
1427 | return false; | |
1428 | ||
1429 | return true; | |
1430 | } | |
1431 | ||
a3496855 | 1432 | static struct pxa2xx_spi_master * |
0db64215 | 1433 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1434 | { |
1435 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1436 | struct acpi_device *adev; |
1437 | struct ssp_device *ssp; | |
1438 | struct resource *res; | |
34cadd9c JN |
1439 | const struct acpi_device_id *adev_id = NULL; |
1440 | const struct pci_device_id *pcidev_id = NULL; | |
3b8b6d05 | 1441 | int type; |
a3496855 | 1442 | |
b9f6940a | 1443 | adev = ACPI_COMPANION(&pdev->dev); |
a3496855 | 1444 | |
34cadd9c JN |
1445 | if (dev_is_pci(pdev->dev.parent)) |
1446 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1447 | to_pci_dev(pdev->dev.parent)); | |
0db64215 | 1448 | else if (adev) |
34cadd9c JN |
1449 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
1450 | &pdev->dev); | |
0db64215 JN |
1451 | else |
1452 | return NULL; | |
34cadd9c JN |
1453 | |
1454 | if (adev_id) | |
1455 | type = (int)adev_id->driver_data; | |
1456 | else if (pcidev_id) | |
1457 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1458 | else |
1459 | return NULL; | |
1460 | ||
cc0ee987 | 1461 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1462 | if (!pdata) |
a3496855 | 1463 | return NULL; |
a3496855 MW |
1464 | |
1465 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1466 | if (!res) | |
1467 | return NULL; | |
1468 | ||
1469 | ssp = &pdata->ssp; | |
1470 | ||
1471 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1472 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1473 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1474 | return NULL; |
a3496855 | 1475 | |
34cadd9c JN |
1476 | if (pcidev_id) { |
1477 | pdata->tx_param = pdev->dev.parent; | |
1478 | pdata->rx_param = pdev->dev.parent; | |
1479 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1480 | } | |
1481 | ||
a3496855 MW |
1482 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1483 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1484 | ssp->type = type; |
a3496855 | 1485 | ssp->pdev = pdev; |
0db64215 | 1486 | ssp->port_id = pxa2xx_spi_get_port_id(adev); |
a3496855 MW |
1487 | |
1488 | pdata->num_chipselect = 1; | |
cddb339b | 1489 | pdata->enable_dma = true; |
a3496855 MW |
1490 | |
1491 | return pdata; | |
1492 | } | |
1493 | ||
0db64215 | 1494 | #else /* !CONFIG_PCI */ |
a3496855 | 1495 | static inline struct pxa2xx_spi_master * |
0db64215 | 1496 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1497 | { |
1498 | return NULL; | |
1499 | } | |
1500 | #endif | |
1501 | ||
0c27d9cf MW |
1502 | static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs) |
1503 | { | |
1504 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1505 | ||
1506 | if (has_acpi_companion(&drv_data->pdev->dev)) { | |
1507 | switch (drv_data->ssp_type) { | |
1508 | /* | |
1509 | * For Atoms the ACPI DeviceSelection used by the Windows | |
1510 | * driver starts from 1 instead of 0 so translate it here | |
1511 | * to match what Linux expects. | |
1512 | */ | |
1513 | case LPSS_BYT_SSP: | |
30f3a6ab | 1514 | case LPSS_BSW_SSP: |
0c27d9cf MW |
1515 | return cs - 1; |
1516 | ||
1517 | default: | |
1518 | break; | |
1519 | } | |
1520 | } | |
1521 | ||
1522 | return cs; | |
1523 | } | |
1524 | ||
fd4a319b | 1525 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1526 | { |
1527 | struct device *dev = &pdev->dev; | |
1528 | struct pxa2xx_spi_master *platform_info; | |
1529 | struct spi_master *master; | |
65a00a20 | 1530 | struct driver_data *drv_data; |
2f1a74e5 | 1531 | struct ssp_device *ssp; |
8b136baa | 1532 | const struct lpss_config *config; |
65a00a20 | 1533 | int status; |
c039dd27 | 1534 | u32 tmp; |
e0c9905e | 1535 | |
851bacf5 MW |
1536 | platform_info = dev_get_platdata(dev); |
1537 | if (!platform_info) { | |
0db64215 | 1538 | platform_info = pxa2xx_spi_init_pdata(pdev); |
a3496855 MW |
1539 | if (!platform_info) { |
1540 | dev_err(&pdev->dev, "missing platform data\n"); | |
1541 | return -ENODEV; | |
1542 | } | |
851bacf5 | 1543 | } |
e0c9905e | 1544 | |
baffe169 | 1545 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1546 | if (!ssp) |
1547 | ssp = &platform_info->ssp; | |
1548 | ||
1549 | if (!ssp->mmio_base) { | |
1550 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1551 | return -ENODEV; |
1552 | } | |
1553 | ||
757fe8d5 | 1554 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1555 | if (!master) { |
65a00a20 | 1556 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1557 | pxa_ssp_free(ssp); |
e0c9905e SS |
1558 | return -ENOMEM; |
1559 | } | |
1560 | drv_data = spi_master_get_devdata(master); | |
1561 | drv_data->master = master; | |
1562 | drv_data->master_info = platform_info; | |
1563 | drv_data->pdev = pdev; | |
2f1a74e5 | 1564 | drv_data->ssp = ssp; |
e0c9905e | 1565 | |
21486af0 | 1566 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1567 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1568 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1569 | |
851bacf5 | 1570 | master->bus_num = ssp->port_id; |
7ad0ba91 | 1571 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1572 | master->cleanup = cleanup; |
1573 | master->setup = setup; | |
7f86bde9 | 1574 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1575 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
0c27d9cf | 1576 | master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; |
7dd62787 | 1577 | master->auto_runtime_pm = true; |
8c3ad488 | 1578 | master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; |
e0c9905e | 1579 | |
2f1a74e5 | 1580 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1581 | |
2f1a74e5 | 1582 | drv_data->ioaddr = ssp->mmio_base; |
1583 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1584 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1585 | switch (drv_data->ssp_type) { |
1586 | case QUARK_X1000_SSP: | |
1587 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1588 | break; | |
1589 | default: | |
1590 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1591 | break; | |
1592 | } | |
1593 | ||
e0c9905e SS |
1594 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1595 | drv_data->dma_cr1 = 0; | |
1596 | drv_data->clear_sr = SSSR_ROR; | |
1597 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1598 | } else { | |
24778be2 | 1599 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1600 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1601 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1602 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1603 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1604 | } | |
1605 | ||
49cbb1e0 SAS |
1606 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1607 | drv_data); | |
e0c9905e | 1608 | if (status < 0) { |
65a00a20 | 1609 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1610 | goto out_error_master_alloc; |
1611 | } | |
1612 | ||
1613 | /* Setup DMA if requested */ | |
e0c9905e | 1614 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1615 | status = pxa2xx_spi_dma_setup(drv_data); |
1616 | if (status) { | |
cddb339b | 1617 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1618 | platform_info->enable_dma = false; |
b6ced294 JN |
1619 | } else { |
1620 | master->can_dma = pxa2xx_spi_can_dma; | |
e0c9905e | 1621 | } |
e0c9905e SS |
1622 | } |
1623 | ||
1624 | /* Enable SOC clock */ | |
3343b7a6 MW |
1625 | clk_prepare_enable(ssp->clk); |
1626 | ||
0eca7cf2 | 1627 | master->max_speed_hz = clk_get_rate(ssp->clk); |
e0c9905e SS |
1628 | |
1629 | /* Load default SSP configuration */ | |
c039dd27 | 1630 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1631 | switch (drv_data->ssp_type) { |
1632 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1633 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1634 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1635 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1636 | |
1637 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1638 | pxa2xx_spi_write(drv_data, SSCR0, |
1639 | QUARK_X1000_SSCR0_Motorola | |
1640 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1641 | break; |
1642 | default: | |
c039dd27 JN |
1643 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1644 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1645 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1646 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1647 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1648 | break; |
1649 | } | |
1650 | ||
2a8626a9 | 1651 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1652 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1653 | |
1654 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1655 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1656 | |
8b136baa JN |
1657 | if (is_lpss_ssp(drv_data)) { |
1658 | lpss_ssp_setup(drv_data); | |
1659 | config = lpss_get_config(drv_data); | |
1660 | if (config->reg_capabilities >= 0) { | |
1661 | tmp = __lpss_ssp_read_priv(drv_data, | |
1662 | config->reg_capabilities); | |
1663 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1664 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1665 | platform_info->num_chipselect = ffz(tmp); | |
30f3a6ab MW |
1666 | } else if (config->cs_num) { |
1667 | platform_info->num_chipselect = config->cs_num; | |
8b136baa JN |
1668 | } |
1669 | } | |
1670 | master->num_chipselect = platform_info->num_chipselect; | |
1671 | ||
7f86bde9 MW |
1672 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1673 | (unsigned long)drv_data); | |
e0c9905e | 1674 | |
836d1a22 AO |
1675 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1676 | pm_runtime_use_autosuspend(&pdev->dev); | |
1677 | pm_runtime_set_active(&pdev->dev); | |
1678 | pm_runtime_enable(&pdev->dev); | |
1679 | ||
e0c9905e SS |
1680 | /* Register with the SPI framework */ |
1681 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1682 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1683 | if (status != 0) { |
1684 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1685 | goto out_error_clock_enabled; |
e0c9905e SS |
1686 | } |
1687 | ||
1688 | return status; | |
1689 | ||
e0c9905e | 1690 | out_error_clock_enabled: |
3343b7a6 | 1691 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1692 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1693 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1694 | |
1695 | out_error_master_alloc: | |
1696 | spi_master_put(master); | |
baffe169 | 1697 | pxa_ssp_free(ssp); |
e0c9905e SS |
1698 | return status; |
1699 | } | |
1700 | ||
1701 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1702 | { | |
1703 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1704 | struct ssp_device *ssp; |
e0c9905e SS |
1705 | |
1706 | if (!drv_data) | |
1707 | return 0; | |
51e911e2 | 1708 | ssp = drv_data->ssp; |
e0c9905e | 1709 | |
7d94a505 MW |
1710 | pm_runtime_get_sync(&pdev->dev); |
1711 | ||
e0c9905e | 1712 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1713 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1714 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1715 | |
1716 | /* Release DMA */ | |
cd7bed00 MW |
1717 | if (drv_data->master_info->enable_dma) |
1718 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1719 | |
7d94a505 MW |
1720 | pm_runtime_put_noidle(&pdev->dev); |
1721 | pm_runtime_disable(&pdev->dev); | |
1722 | ||
e0c9905e | 1723 | /* Release IRQ */ |
2f1a74e5 | 1724 | free_irq(ssp->irq, drv_data); |
1725 | ||
1726 | /* Release SSP */ | |
baffe169 | 1727 | pxa_ssp_free(ssp); |
e0c9905e | 1728 | |
e0c9905e SS |
1729 | return 0; |
1730 | } | |
1731 | ||
1732 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1733 | { | |
1734 | int status = 0; | |
1735 | ||
1736 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1737 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1738 | } | |
1739 | ||
382cebb0 | 1740 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1741 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1742 | { |
86d2593a | 1743 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1744 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1745 | int status = 0; |
1746 | ||
7f86bde9 | 1747 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1748 | if (status != 0) |
1749 | return status; | |
c039dd27 | 1750 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1751 | |
1752 | if (!pm_runtime_suspended(dev)) | |
1753 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1754 | |
1755 | return 0; | |
1756 | } | |
1757 | ||
86d2593a | 1758 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1759 | { |
86d2593a | 1760 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1761 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1762 | int status = 0; |
1763 | ||
1764 | /* Enable the SSP clock */ | |
2b9375b9 DES |
1765 | if (!pm_runtime_suspended(dev)) |
1766 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1767 | |
c50325f7 | 1768 | /* Restore LPSS private register bits */ |
48421adf JN |
1769 | if (is_lpss_ssp(drv_data)) |
1770 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1771 | |
e0c9905e | 1772 | /* Start the queue running */ |
7f86bde9 | 1773 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1774 | if (status != 0) { |
86d2593a | 1775 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1776 | return status; |
1777 | } | |
1778 | ||
1779 | return 0; | |
1780 | } | |
7d94a505 MW |
1781 | #endif |
1782 | ||
ec833050 | 1783 | #ifdef CONFIG_PM |
7d94a505 MW |
1784 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1785 | { | |
1786 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1787 | ||
1788 | clk_disable_unprepare(drv_data->ssp->clk); | |
1789 | return 0; | |
1790 | } | |
1791 | ||
1792 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1793 | { | |
1794 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1795 | ||
1796 | clk_prepare_enable(drv_data->ssp->clk); | |
1797 | return 0; | |
1798 | } | |
1799 | #endif | |
86d2593a | 1800 | |
47145210 | 1801 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1802 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1803 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1804 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1805 | }; |
e0c9905e SS |
1806 | |
1807 | static struct platform_driver driver = { | |
1808 | .driver = { | |
86d2593a | 1809 | .name = "pxa2xx-spi", |
86d2593a | 1810 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1811 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1812 | }, |
fbd29a14 | 1813 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1814 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1815 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1816 | }; |
1817 | ||
1818 | static int __init pxa2xx_spi_init(void) | |
1819 | { | |
fbd29a14 | 1820 | return platform_driver_register(&driver); |
e0c9905e | 1821 | } |
5b61a749 | 1822 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1823 | |
1824 | static void __exit pxa2xx_spi_exit(void) | |
1825 | { | |
1826 | platform_driver_unregister(&driver); | |
1827 | } | |
1828 | module_exit(pxa2xx_spi_exit); |