[linux-block.git] / drivers / spi / spi-pxa2xx-pci.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * CE4100's SPI device is more or less the same one as found on PXA
 *
 * Copyright (C) 2016, Intel Corporation
 */
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/spi/pxa2xx_spi.h>

#include <linux/dmaengine.h>
#include <linux/platform_data/dma-dw.h>

enum {
	PORT_QUARK_X1000,
	PORT_BYT,
	PORT_MRFLD,
	PORT_BSW0,
	PORT_BSW1,
	PORT_BSW2,
	PORT_CE4100,
	PORT_LPT0,
	PORT_LPT1,
};

struct pxa_spi_info {
	enum pxa_ssp_type type;
	int port_id;
	int num_chipselect;
	unsigned long max_clk_rate;

	/* DMA channel request parameters */
	bool (*dma_filter)(struct dma_chan *chan, void *param);
	void *tx_param;
	void *rx_param;

	int dma_burst_size;

	int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c);
};

static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
static struct dw_dma_slave byt_rx_param = { .src_id = 1 };

static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };

static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };

static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };

static bool lpss_dma_filter(struct dma_chan *chan, void *param)
{
	struct dw_dma_slave *dws = param;

	if (dws->dma_dev != chan->device->dev)
		return false;

	chan->private = dws;
	return true;
}

static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
{
	struct pci_dev *dma_dev;

	c->num_chipselect = 1;
	c->max_clk_rate = 50000000;

	dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));

	if (c->tx_param) {
		struct dw_dma_slave *slave = c->tx_param;

		slave->dma_dev = &dma_dev->dev;
		slave->m_master = 0;
		slave->p_master = 1;
	}

	if (c->rx_param) {
		struct dw_dma_slave *slave = c->rx_param;

		slave->dma_dev = &dma_dev->dev;
		slave->m_master = 0;
		slave->p_master = 1;
	}

	c->dma_filter = lpss_dma_filter;
	return 0;
}

static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
{
	struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
	struct dw_dma_slave *tx, *rx;

	switch (PCI_FUNC(dev->devfn)) {
	case 0:
		c->port_id = 3;
		c->num_chipselect = 1;
		c->tx_param = &mrfld3_tx_param;
		c->rx_param = &mrfld3_rx_param;
		break;
	case 1:
		c->port_id = 5;
		c->num_chipselect = 4;
		c->tx_param = &mrfld5_tx_param;
		c->rx_param = &mrfld5_rx_param;
		break;
	case 2:
		c->port_id = 6;
		c->num_chipselect = 1;
		c->tx_param = &mrfld6_tx_param;
		c->rx_param = &mrfld6_rx_param;
		break;
	default:
		return -ENODEV;
	}

	tx = c->tx_param;
	tx->dma_dev = &dma_dev->dev;

	rx = c->rx_param;
	rx->dma_dev = &dma_dev->dev;

	c->dma_filter = lpss_dma_filter;
	c->dma_burst_size = 8;
	return 0;
}

static struct pxa_spi_info spi_info_configs[] = {
	[PORT_CE4100] = {
		.type = PXA25x_SSP,
		.port_id =  -1,
		.num_chipselect = -1,
		.max_clk_rate = 3686400,
	},
	[PORT_BYT] = {
		.type = LPSS_BYT_SSP,
		.port_id = 0,
		.setup = lpss_spi_setup,
		.tx_param = &byt_tx_param,
		.rx_param = &byt_rx_param,
	},
	[PORT_BSW0] = {
		.type = LPSS_BSW_SSP,
		.port_id = 0,
		.setup = lpss_spi_setup,
		.tx_param = &bsw0_tx_param,
		.rx_param = &bsw0_rx_param,
	},
	[PORT_BSW1] = {
		.type = LPSS_BSW_SSP,
		.port_id = 1,
		.setup = lpss_spi_setup,
		.tx_param = &bsw1_tx_param,
		.rx_param = &bsw1_rx_param,
	},
	[PORT_BSW2] = {
		.type = LPSS_BSW_SSP,
		.port_id = 2,
		.setup = lpss_spi_setup,
		.tx_param = &bsw2_tx_param,
		.rx_param = &bsw2_rx_param,
	},
	[PORT_MRFLD] = {
		.type = PXA27x_SSP,
		.max_clk_rate = 25000000,
		.setup = mrfld_spi_setup,
	},
	[PORT_QUARK_X1000] = {
		.type = QUARK_X1000_SSP,
		.port_id = -1,
		.num_chipselect = 1,
		.max_clk_rate = 50000000,
	},
	[PORT_LPT0] = {
		.type = LPSS_LPT_SSP,
		.port_id = 0,
		.setup = lpss_spi_setup,
		.tx_param = &lpt0_tx_param,
		.rx_param = &lpt0_rx_param,
	},
	[PORT_LPT1] = {
		.type = LPSS_LPT_SSP,
		.port_id = 1,
		.setup = lpss_spi_setup,
		.tx_param = &lpt1_tx_param,
		.rx_param = &lpt1_rx_param,
	},
};

static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
		const struct pci_device_id *ent)
{
	struct platform_device_info pi;
	int ret;
	struct platform_device *pdev;
	struct pxa2xx_spi_controller spi_pdata;
	struct ssp_device *ssp;
	struct pxa_spi_info *c;
	char buf[40];

	ret = pcim_enable_device(dev);
	if (ret)
		return ret;

	ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
	if (ret)
		return ret;

	c = &spi_info_configs[ent->driver_data];
	if (c->setup) {
		ret = c->setup(dev, c);
		if (ret)
			return ret;
	}

	memset(&spi_pdata, 0, sizeof(spi_pdata));
	spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn;
	spi_pdata.dma_filter = c->dma_filter;
	spi_pdata.tx_param = c->tx_param;
	spi_pdata.rx_param = c->rx_param;
	spi_pdata.enable_dma = c->rx_param && c->tx_param;
	spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1;

	ssp = &spi_pdata.ssp;
	ssp->phys_base = pci_resource_start(dev, 0);
	ssp->mmio_base = pcim_iomap_table(dev)[0];
	ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
	ssp->type = c->type;

	pci_set_master(dev);

	ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
	if (ret < 0)
		return ret;
	ssp->irq = pci_irq_vector(dev, 0);

	snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
	ssp->clk = clk_register_fixed_rate(&dev->dev, buf, NULL, 0,
					   c->max_clk_rate);
	 if (IS_ERR(ssp->clk))
		return PTR_ERR(ssp->clk);

	memset(&pi, 0, sizeof(pi));
	pi.fwnode = dev->dev.fwnode;
	pi.parent = &dev->dev;
	pi.name = "pxa2xx-spi";
	pi.id = ssp->port_id;
	pi.data = &spi_pdata;
	pi.size_data = sizeof(spi_pdata);

	pdev = platform_device_register_full(&pi);
	if (IS_ERR(pdev)) {
		clk_unregister(ssp->clk);
		return PTR_ERR(pdev);
	}

	pci_set_drvdata(dev, pdev);

	return 0;
}

static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
{
	struct platform_device *pdev = pci_get_drvdata(dev);
	struct pxa2xx_spi_controller *spi_pdata;

	spi_pdata = dev_get_platdata(&pdev->dev);

	platform_device_unregister(pdev);
	clk_unregister(spi_pdata->ssp.clk);
}

static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
	{ PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
	{ PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
	{ PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
	{ PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
	{ PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
	{ PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
	{ PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
	{ PCI_VDEVICE(INTEL, 0x9c65), PORT_LPT0 },
	{ PCI_VDEVICE(INTEL, 0x9c66), PORT_LPT1 },
	{ PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
	{ PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
	{ }
};
MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);

static struct pci_driver pxa2xx_spi_pci_driver = {
	.name           = "pxa2xx_spi_pci",
	.id_table       = pxa2xx_spi_pci_devices,
	.probe          = pxa2xx_spi_pci_probe,
	.remove         = pxa2xx_spi_pci_remove,
};

module_pci_driver(pxa2xx_spi_pci_driver);

MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
d6ea3df0 SAS	2	/*
	3	* CE4100's SPI device is more or less the same one as found on PXA
	4	*
e379d2cd	5	* Copyright (C) 2016, Intel Corporation
d6ea3df0	6	*/
e379d2cd AS	7	#include <linux/clk-provider.h>
e379d2cd AS	8	#include <linux/module.h>
d6ea3df0 SAS	9	#include <linux/pci.h>
d6ea3df0 SAS	10	#include <linux/platform_device.h>
d6ea3df0 SAS	11	#include <linux/spi/pxa2xx_spi.h>
d6ea3df0 SAS	12
b729bf34 MW	13	#include <linux/dmaengine.h>
	14	#include <linux/platform_data/dma-dw.h>
	15
d6ba32d5	16	enum {
e379d2cd	17	PORT_QUARK_X1000,
d6ba32d5	18	PORT_BYT,
4f470910	19	PORT_MRFLD,
39d36536 MW	20	PORT_BSW0,
	21	PORT_BSW1,
	22	PORT_BSW2,
e379d2cd	23	PORT_CE4100,
54c5d3bf AS	24	PORT_LPT0,
54c5d3bf AS	25	PORT_LPT1,
d6ba32d5 CCE	26	};
	27
	28	struct pxa_spi_info {
	29	enum pxa_ssp_type type;
	30	int port_id;
	31	int num_chipselect;
afa93c90	32	unsigned long max_clk_rate;
b729bf34 MW	33
b729bf34 MW	34	/* DMA channel request parameters */
743485ea	35	bool (dma_filter)(struct dma_chan chan, void *param);
b729bf34 MW	36	void *tx_param;
b729bf34 MW	37	void *rx_param;
743485ea	38
37821a82 AS	39	int dma_burst_size;
37821a82 AS	40
743485ea	41	int (setup)(struct pci_dev pdev, struct pxa_spi_info *c);
d6ba32d5 CCE	42	};
d6ba32d5 CCE	43
b729bf34 MW	44	static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
	45	static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
	46
25014521 AS	47	static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
	48	static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
	49	static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
	50	static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
	51	static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
	52	static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
	53
39d36536 MW	54	static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
	55	static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
	56	static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
	57	static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
	58	static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
	59	static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
	60
54c5d3bf AS	61	static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
	62	static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
	63	static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
	64	static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
caba248d	65
b729bf34 MW	66	static bool lpss_dma_filter(struct dma_chan chan, void param)
	67	{
	68	struct dw_dma_slave *dws = param;
	69
	70	if (dws->dma_dev != chan->device->dev)
	71	return false;
	72
	73	chan->private = dws;
	74	return true;
	75	}
	76
743485ea AS	77	static int lpss_spi_setup(struct pci_dev dev, struct pxa_spi_info c)
	78	{
	79	struct pci_dev *dma_dev;
	80
	81	c->num_chipselect = 1;
	82	c->max_clk_rate = 50000000;
	83
	84	dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	85
	86	if (c->tx_param) {
	87	struct dw_dma_slave *slave = c->tx_param;
	88
	89	slave->dma_dev = &dma_dev->dev;
	90	slave->m_master = 0;
	91	slave->p_master = 1;
	92	}
	93
	94	if (c->rx_param) {
	95	struct dw_dma_slave *slave = c->rx_param;
	96
	97	slave->dma_dev = &dma_dev->dev;
	98	slave->m_master = 0;
	99	slave->p_master = 1;
	100	}
	101
	102	c->dma_filter = lpss_dma_filter;
	103	return 0;
	104	}
	105
4f470910 AS	106	static int mrfld_spi_setup(struct pci_dev dev, struct pxa_spi_info c)
4f470910 AS	107	{
25014521 AS	108	struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
	109	struct dw_dma_slave tx, rx;
	110
4f470910 AS	111	switch (PCI_FUNC(dev->devfn)) {
	112	case 0:
	113	c->port_id = 3;
	114	c->num_chipselect = 1;
25014521 AS	115	c->tx_param = &mrfld3_tx_param;
25014521 AS	116	c->rx_param = &mrfld3_rx_param;
4f470910 AS	117	break;
	118	case 1:
	119	c->port_id = 5;
	120	c->num_chipselect = 4;
25014521 AS	121	c->tx_param = &mrfld5_tx_param;
25014521 AS	122	c->rx_param = &mrfld5_rx_param;
4f470910 AS	123	break;
	124	case 2:
	125	c->port_id = 6;
	126	c->num_chipselect = 1;
25014521 AS	127	c->tx_param = &mrfld6_tx_param;
25014521 AS	128	c->rx_param = &mrfld6_rx_param;
4f470910 AS	129	break;
	130	default:
	131	return -ENODEV;
	132	}
25014521 AS	133
	134	tx = c->tx_param;
	135	tx->dma_dev = &dma_dev->dev;
	136
	137	rx = c->rx_param;
	138	rx->dma_dev = &dma_dev->dev;
	139
	140	c->dma_filter = lpss_dma_filter;
37821a82	141	c->dma_burst_size = 8;
4f470910 AS	142	return 0;
	143	}
	144
d6ba32d5 CCE	145	static struct pxa_spi_info spi_info_configs[] = {
	146	[PORT_CE4100] = {
	147	.type = PXA25x_SSP,
	148	.port_id = -1,
	149	.num_chipselect = -1,
afa93c90	150	.max_clk_rate = 3686400,
d6ba32d5 CCE	151	},
d6ba32d5 CCE	152	[PORT_BYT] = {
03fbf488	153	.type = LPSS_BYT_SSP,
d6ba32d5	154	.port_id = 0,
743485ea	155	.setup = lpss_spi_setup,
b729bf34 MW	156	.tx_param = &byt_tx_param,
b729bf34 MW	157	.rx_param = &byt_rx_param,
d6ba32d5	158	},
39d36536	159	[PORT_BSW0] = {
ca80ef71	160	.type = LPSS_BSW_SSP,
39d36536	161	.port_id = 0,
743485ea	162	.setup = lpss_spi_setup,
39d36536 MW	163	.tx_param = &bsw0_tx_param,
	164	.rx_param = &bsw0_rx_param,
	165	},
	166	[PORT_BSW1] = {
ca80ef71	167	.type = LPSS_BSW_SSP,
39d36536	168	.port_id = 1,
743485ea	169	.setup = lpss_spi_setup,
39d36536 MW	170	.tx_param = &bsw1_tx_param,
	171	.rx_param = &bsw1_rx_param,
	172	},
	173	[PORT_BSW2] = {
ca80ef71	174	.type = LPSS_BSW_SSP,
39d36536	175	.port_id = 2,
743485ea	176	.setup = lpss_spi_setup,
39d36536 MW	177	.tx_param = &bsw2_tx_param,
39d36536 MW	178	.rx_param = &bsw2_rx_param,
d6ba32d5	179	},
4f470910 AS	180	[PORT_MRFLD] = {
	181	.type = PXA27x_SSP,
	182	.max_clk_rate = 25000000,
	183	.setup = mrfld_spi_setup,
	184	},
e5262d05 WC	185	[PORT_QUARK_X1000] = {
	186	.type = QUARK_X1000_SSP,
	187	.port_id = -1,
	188	.num_chipselect = 1,
	189	.max_clk_rate = 50000000,
	190	},
54c5d3bf	191	[PORT_LPT0] = {
caba248d LL	192	.type = LPSS_LPT_SSP,
caba248d LL	193	.port_id = 0,
743485ea	194	.setup = lpss_spi_setup,
54c5d3bf AS	195	.tx_param = &lpt0_tx_param,
	196	.rx_param = &lpt0_rx_param,
	197	},
	198	[PORT_LPT1] = {
	199	.type = LPSS_LPT_SSP,
	200	.port_id = 1,
	201	.setup = lpss_spi_setup,
	202	.tx_param = &lpt1_tx_param,
	203	.rx_param = &lpt1_rx_param,
caba248d	204	},
d6ba32d5 CCE	205	};
	206
	207	static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
d6ea3df0 SAS	208	const struct pci_device_id *ent)
d6ea3df0 SAS	209	{
0202775b	210	struct platform_device_info pi;
d6ea3df0	211	int ret;
d6ea3df0	212	struct platform_device *pdev;
51eea52d	213	struct pxa2xx_spi_controller spi_pdata;
d6ea3df0	214	struct ssp_device *ssp;
d6ba32d5	215	struct pxa_spi_info *c;
afa93c90	216	char buf[40];
d6ea3df0	217
0202775b	218	ret = pcim_enable_device(dev);
d6ea3df0 SAS	219	if (ret)
	220	return ret;
	221
0202775b	222	ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
c1346340	223	if (ret)
d6ea3df0	224	return ret;
d6ea3df0	225
d6ba32d5	226	c = &spi_info_configs[ent->driver_data];
743485ea AS	227	if (c->setup) {
	228	ret = c->setup(dev, c);
	229	if (ret)
	230	return ret;
b729bf34 MW	231	}
b729bf34 MW	232
743485ea AS	233	memset(&spi_pdata, 0, sizeof(spi_pdata));
	234	spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn;
	235	spi_pdata.dma_filter = c->dma_filter;
b729bf34 MW	236	spi_pdata.tx_param = c->tx_param;
	237	spi_pdata.rx_param = c->rx_param;
	238	spi_pdata.enable_dma = c->rx_param && c->tx_param;
37821a82	239	spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1;
d6ea3df0	240
851bacf5	241	ssp = &spi_pdata.ssp;
d6ea3df0	242	ssp->phys_base = pci_resource_start(dev, 0);
0202775b	243	ssp->mmio_base = pcim_iomap_table(dev)[0];
d6ba32d5 CCE	244	ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
d6ba32d5 CCE	245	ssp->type = c->type;
d6ea3df0	246
64e02cb0 JK	247	pci_set_master(dev);
	248
	249	ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
	250	if (ret < 0)
	251	return ret;
	252	ssp->irq = pci_irq_vector(dev, 0);
	253
afa93c90	254	snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
c07caca3	255	ssp->clk = clk_register_fixed_rate(&dev->dev, buf, NULL, 0,
280af2b8	256	c->max_clk_rate);
afa93c90 CCE	257	if (IS_ERR(ssp->clk))
	258	return PTR_ERR(ssp->clk);
	259
0202775b	260	memset(&pi, 0, sizeof(pi));
b70cd2de	261	pi.fwnode = dev->dev.fwnode;
0202775b MW	262	pi.parent = &dev->dev;
	263	pi.name = "pxa2xx-spi";
	264	pi.id = ssp->port_id;
	265	pi.data = &spi_pdata;
	266	pi.size_data = sizeof(spi_pdata);
d6ea3df0	267
0202775b	268	pdev = platform_device_register_full(&pi);
afa93c90 CCE	269	if (IS_ERR(pdev)) {
afa93c90 CCE	270	clk_unregister(ssp->clk);
d77b5382	271	return PTR_ERR(pdev);
afa93c90	272	}
d6ea3df0	273
851bacf5	274	pci_set_drvdata(dev, pdev);
d6ea3df0	275
0202775b	276	return 0;
d6ea3df0 SAS	277	}
d6ea3df0 SAS	278
d6ba32d5	279	static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
d6ea3df0	280	{
851bacf5	281	struct platform_device *pdev = pci_get_drvdata(dev);
51eea52d	282	struct pxa2xx_spi_controller *spi_pdata;
afa93c90 CCE	283
afa93c90 CCE	284	spi_pdata = dev_get_platdata(&pdev->dev);
d6ea3df0	285
851bacf5	286	platform_device_unregister(pdev);
afa93c90	287	clk_unregister(spi_pdata->ssp.clk);
d6ea3df0 SAS	288	}
d6ea3df0 SAS	289
d6ba32d5	290	static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
e5262d05	291	{ PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
d6ba32d5	292	{ PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
4f470910	293	{ PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
39d36536 MW	294	{ PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
	295	{ PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
	296	{ PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
e379d2cd	297	{ PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
23951837 AS	298	{ PCI_VDEVICE(INTEL, 0x9c65), PORT_LPT0 },
23951837 AS	299	{ PCI_VDEVICE(INTEL, 0x9c66), PORT_LPT1 },
54c5d3bf AS	300	{ PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
	301	{ PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
	302	{ }
d6ea3df0	303	};
d6ba32d5	304	MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
d6ea3df0	305
d6ba32d5 CCE	306	static struct pci_driver pxa2xx_spi_pci_driver = {
	307	.name = "pxa2xx_spi_pci",
	308	.id_table = pxa2xx_spi_pci_devices,
	309	.probe = pxa2xx_spi_pci_probe,
	310	.remove = pxa2xx_spi_pci_remove,
d6ea3df0 SAS	311	};
d6ea3df0 SAS	312
d6ba32d5	313	module_pci_driver(pxa2xx_spi_pci_driver);
d6ea3df0	314
d6ba32d5	315	MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
d6ea3df0 SAS	316	MODULE_LICENSE("GPL v2");
d6ea3df0 SAS	317	MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");