Commit | Line | Data |
---|---|---|
d6ea3df0 SAS |
1 | /* |
2 | * CE4100's SPI device is more or less the same one as found on PXA | |
3 | * | |
e379d2cd | 4 | * Copyright (C) 2016, Intel Corporation |
d6ea3df0 | 5 | */ |
e379d2cd AS |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/module.h> | |
8 | #include <linux/of_device.h> | |
d6ea3df0 SAS |
9 | #include <linux/pci.h> |
10 | #include <linux/platform_device.h> | |
d6ea3df0 SAS |
11 | #include <linux/spi/pxa2xx_spi.h> |
12 | ||
b729bf34 MW |
13 | #include <linux/dmaengine.h> |
14 | #include <linux/platform_data/dma-dw.h> | |
15 | ||
d6ba32d5 | 16 | enum { |
e379d2cd | 17 | PORT_QUARK_X1000, |
d6ba32d5 | 18 | PORT_BYT, |
4f470910 | 19 | PORT_MRFLD, |
39d36536 MW |
20 | PORT_BSW0, |
21 | PORT_BSW1, | |
22 | PORT_BSW2, | |
e379d2cd | 23 | PORT_CE4100, |
caba248d | 24 | PORT_LPT, |
d6ba32d5 CCE |
25 | }; |
26 | ||
27 | struct pxa_spi_info { | |
28 | enum pxa_ssp_type type; | |
29 | int port_id; | |
30 | int num_chipselect; | |
afa93c90 | 31 | unsigned long max_clk_rate; |
b729bf34 MW |
32 | |
33 | /* DMA channel request parameters */ | |
743485ea | 34 | bool (*dma_filter)(struct dma_chan *chan, void *param); |
b729bf34 MW |
35 | void *tx_param; |
36 | void *rx_param; | |
743485ea AS |
37 | |
38 | int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c); | |
d6ba32d5 CCE |
39 | }; |
40 | ||
b729bf34 MW |
41 | static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; |
42 | static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; | |
43 | ||
25014521 AS |
44 | static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 }; |
45 | static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 }; | |
46 | static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 }; | |
47 | static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 }; | |
48 | static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 }; | |
49 | static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 }; | |
50 | ||
39d36536 MW |
51 | static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; |
52 | static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; | |
53 | static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; | |
54 | static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; | |
55 | static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 }; | |
56 | static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 }; | |
57 | ||
caba248d LL |
58 | static struct dw_dma_slave lpt_tx_param = { .dst_id = 0 }; |
59 | static struct dw_dma_slave lpt_rx_param = { .src_id = 1 }; | |
60 | ||
b729bf34 MW |
61 | static bool lpss_dma_filter(struct dma_chan *chan, void *param) |
62 | { | |
63 | struct dw_dma_slave *dws = param; | |
64 | ||
65 | if (dws->dma_dev != chan->device->dev) | |
66 | return false; | |
67 | ||
68 | chan->private = dws; | |
69 | return true; | |
70 | } | |
71 | ||
743485ea AS |
72 | static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) |
73 | { | |
74 | struct pci_dev *dma_dev; | |
75 | ||
76 | c->num_chipselect = 1; | |
77 | c->max_clk_rate = 50000000; | |
78 | ||
79 | dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
80 | ||
81 | if (c->tx_param) { | |
82 | struct dw_dma_slave *slave = c->tx_param; | |
83 | ||
84 | slave->dma_dev = &dma_dev->dev; | |
85 | slave->m_master = 0; | |
86 | slave->p_master = 1; | |
87 | } | |
88 | ||
89 | if (c->rx_param) { | |
90 | struct dw_dma_slave *slave = c->rx_param; | |
91 | ||
92 | slave->dma_dev = &dma_dev->dev; | |
93 | slave->m_master = 0; | |
94 | slave->p_master = 1; | |
95 | } | |
96 | ||
97 | c->dma_filter = lpss_dma_filter; | |
98 | return 0; | |
99 | } | |
100 | ||
4f470910 AS |
101 | static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) |
102 | { | |
25014521 AS |
103 | struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0)); |
104 | struct dw_dma_slave *tx, *rx; | |
105 | ||
4f470910 AS |
106 | switch (PCI_FUNC(dev->devfn)) { |
107 | case 0: | |
108 | c->port_id = 3; | |
109 | c->num_chipselect = 1; | |
25014521 AS |
110 | c->tx_param = &mrfld3_tx_param; |
111 | c->rx_param = &mrfld3_rx_param; | |
4f470910 AS |
112 | break; |
113 | case 1: | |
114 | c->port_id = 5; | |
115 | c->num_chipselect = 4; | |
25014521 AS |
116 | c->tx_param = &mrfld5_tx_param; |
117 | c->rx_param = &mrfld5_rx_param; | |
4f470910 AS |
118 | break; |
119 | case 2: | |
120 | c->port_id = 6; | |
121 | c->num_chipselect = 1; | |
25014521 AS |
122 | c->tx_param = &mrfld6_tx_param; |
123 | c->rx_param = &mrfld6_rx_param; | |
4f470910 AS |
124 | break; |
125 | default: | |
126 | return -ENODEV; | |
127 | } | |
25014521 AS |
128 | |
129 | tx = c->tx_param; | |
130 | tx->dma_dev = &dma_dev->dev; | |
131 | ||
132 | rx = c->rx_param; | |
133 | rx->dma_dev = &dma_dev->dev; | |
134 | ||
135 | c->dma_filter = lpss_dma_filter; | |
4f470910 AS |
136 | return 0; |
137 | } | |
138 | ||
d6ba32d5 CCE |
139 | static struct pxa_spi_info spi_info_configs[] = { |
140 | [PORT_CE4100] = { | |
141 | .type = PXA25x_SSP, | |
142 | .port_id = -1, | |
143 | .num_chipselect = -1, | |
afa93c90 | 144 | .max_clk_rate = 3686400, |
d6ba32d5 CCE |
145 | }, |
146 | [PORT_BYT] = { | |
03fbf488 | 147 | .type = LPSS_BYT_SSP, |
d6ba32d5 | 148 | .port_id = 0, |
743485ea | 149 | .setup = lpss_spi_setup, |
b729bf34 MW |
150 | .tx_param = &byt_tx_param, |
151 | .rx_param = &byt_rx_param, | |
d6ba32d5 | 152 | }, |
39d36536 | 153 | [PORT_BSW0] = { |
ca80ef71 | 154 | .type = LPSS_BSW_SSP, |
39d36536 | 155 | .port_id = 0, |
743485ea | 156 | .setup = lpss_spi_setup, |
39d36536 MW |
157 | .tx_param = &bsw0_tx_param, |
158 | .rx_param = &bsw0_rx_param, | |
159 | }, | |
160 | [PORT_BSW1] = { | |
ca80ef71 | 161 | .type = LPSS_BSW_SSP, |
39d36536 | 162 | .port_id = 1, |
743485ea | 163 | .setup = lpss_spi_setup, |
39d36536 MW |
164 | .tx_param = &bsw1_tx_param, |
165 | .rx_param = &bsw1_rx_param, | |
166 | }, | |
167 | [PORT_BSW2] = { | |
ca80ef71 | 168 | .type = LPSS_BSW_SSP, |
39d36536 | 169 | .port_id = 2, |
743485ea | 170 | .setup = lpss_spi_setup, |
39d36536 MW |
171 | .tx_param = &bsw2_tx_param, |
172 | .rx_param = &bsw2_rx_param, | |
d6ba32d5 | 173 | }, |
4f470910 AS |
174 | [PORT_MRFLD] = { |
175 | .type = PXA27x_SSP, | |
176 | .max_clk_rate = 25000000, | |
177 | .setup = mrfld_spi_setup, | |
178 | }, | |
e5262d05 WC |
179 | [PORT_QUARK_X1000] = { |
180 | .type = QUARK_X1000_SSP, | |
181 | .port_id = -1, | |
182 | .num_chipselect = 1, | |
183 | .max_clk_rate = 50000000, | |
184 | }, | |
caba248d LL |
185 | [PORT_LPT] = { |
186 | .type = LPSS_LPT_SSP, | |
187 | .port_id = 0, | |
743485ea | 188 | .setup = lpss_spi_setup, |
caba248d LL |
189 | .tx_param = &lpt_tx_param, |
190 | .rx_param = &lpt_rx_param, | |
191 | }, | |
d6ba32d5 CCE |
192 | }; |
193 | ||
194 | static int pxa2xx_spi_pci_probe(struct pci_dev *dev, | |
d6ea3df0 SAS |
195 | const struct pci_device_id *ent) |
196 | { | |
0202775b | 197 | struct platform_device_info pi; |
d6ea3df0 | 198 | int ret; |
d6ea3df0 | 199 | struct platform_device *pdev; |
51eea52d | 200 | struct pxa2xx_spi_controller spi_pdata; |
d6ea3df0 | 201 | struct ssp_device *ssp; |
d6ba32d5 | 202 | struct pxa_spi_info *c; |
afa93c90 | 203 | char buf[40]; |
d6ea3df0 | 204 | |
0202775b | 205 | ret = pcim_enable_device(dev); |
d6ea3df0 SAS |
206 | if (ret) |
207 | return ret; | |
208 | ||
0202775b | 209 | ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI"); |
c1346340 | 210 | if (ret) |
d6ea3df0 | 211 | return ret; |
d6ea3df0 | 212 | |
d6ba32d5 | 213 | c = &spi_info_configs[ent->driver_data]; |
743485ea AS |
214 | if (c->setup) { |
215 | ret = c->setup(dev, c); | |
216 | if (ret) | |
217 | return ret; | |
b729bf34 MW |
218 | } |
219 | ||
743485ea AS |
220 | memset(&spi_pdata, 0, sizeof(spi_pdata)); |
221 | spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn; | |
222 | spi_pdata.dma_filter = c->dma_filter; | |
b729bf34 MW |
223 | spi_pdata.tx_param = c->tx_param; |
224 | spi_pdata.rx_param = c->rx_param; | |
225 | spi_pdata.enable_dma = c->rx_param && c->tx_param; | |
d6ea3df0 | 226 | |
851bacf5 | 227 | ssp = &spi_pdata.ssp; |
d6ea3df0 | 228 | ssp->phys_base = pci_resource_start(dev, 0); |
0202775b | 229 | ssp->mmio_base = pcim_iomap_table(dev)[0]; |
d6ba32d5 CCE |
230 | ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; |
231 | ssp->type = c->type; | |
d6ea3df0 | 232 | |
64e02cb0 JK |
233 | pci_set_master(dev); |
234 | ||
235 | ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); | |
236 | if (ret < 0) | |
237 | return ret; | |
238 | ssp->irq = pci_irq_vector(dev, 0); | |
239 | ||
afa93c90 | 240 | snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); |
280af2b8 SB |
241 | ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0, |
242 | c->max_clk_rate); | |
afa93c90 CCE |
243 | if (IS_ERR(ssp->clk)) |
244 | return PTR_ERR(ssp->clk); | |
245 | ||
0202775b | 246 | memset(&pi, 0, sizeof(pi)); |
b70cd2de | 247 | pi.fwnode = dev->dev.fwnode; |
0202775b MW |
248 | pi.parent = &dev->dev; |
249 | pi.name = "pxa2xx-spi"; | |
250 | pi.id = ssp->port_id; | |
251 | pi.data = &spi_pdata; | |
252 | pi.size_data = sizeof(spi_pdata); | |
d6ea3df0 | 253 | |
0202775b | 254 | pdev = platform_device_register_full(&pi); |
afa93c90 CCE |
255 | if (IS_ERR(pdev)) { |
256 | clk_unregister(ssp->clk); | |
d77b5382 | 257 | return PTR_ERR(pdev); |
afa93c90 | 258 | } |
d6ea3df0 | 259 | |
851bacf5 | 260 | pci_set_drvdata(dev, pdev); |
d6ea3df0 | 261 | |
0202775b | 262 | return 0; |
d6ea3df0 SAS |
263 | } |
264 | ||
d6ba32d5 | 265 | static void pxa2xx_spi_pci_remove(struct pci_dev *dev) |
d6ea3df0 | 266 | { |
851bacf5 | 267 | struct platform_device *pdev = pci_get_drvdata(dev); |
51eea52d | 268 | struct pxa2xx_spi_controller *spi_pdata; |
afa93c90 CCE |
269 | |
270 | spi_pdata = dev_get_platdata(&pdev->dev); | |
d6ea3df0 | 271 | |
851bacf5 | 272 | platform_device_unregister(pdev); |
afa93c90 | 273 | clk_unregister(spi_pdata->ssp.clk); |
d6ea3df0 SAS |
274 | } |
275 | ||
d6ba32d5 | 276 | static const struct pci_device_id pxa2xx_spi_pci_devices[] = { |
e5262d05 | 277 | { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 }, |
d6ba32d5 | 278 | { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, |
4f470910 | 279 | { PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD }, |
39d36536 MW |
280 | { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, |
281 | { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, | |
282 | { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 }, | |
e379d2cd | 283 | { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, |
caba248d | 284 | { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT }, |
d6ea3df0 SAS |
285 | { }, |
286 | }; | |
d6ba32d5 | 287 | MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices); |
d6ea3df0 | 288 | |
d6ba32d5 CCE |
289 | static struct pci_driver pxa2xx_spi_pci_driver = { |
290 | .name = "pxa2xx_spi_pci", | |
291 | .id_table = pxa2xx_spi_pci_devices, | |
292 | .probe = pxa2xx_spi_pci_probe, | |
293 | .remove = pxa2xx_spi_pci_remove, | |
d6ea3df0 SAS |
294 | }; |
295 | ||
d6ba32d5 | 296 | module_pci_driver(pxa2xx_spi_pci_driver); |
d6ea3df0 | 297 | |
d6ba32d5 | 298 | MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver"); |
d6ea3df0 SAS |
299 | MODULE_LICENSE("GPL v2"); |
300 | MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>"); |