[linux-2.6-block.git] / drivers / spi / spi-pxa2xx-dma.c

/*
 * PXA2xx SPI DMA engine support.
 *
 * Copyright (C) 2013, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/pxa2xx_ssp.h>
#include <linux/scatterlist.h>
#include <linux/sizes.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>

#include "spi-pxa2xx.h"

static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
					     bool error)
{
	struct spi_message *msg = drv_data->controller->cur_msg;

	/*
	 * It is possible that one CPU is handling ROR interrupt and other
	 * just gets DMA completion. Calling pump_transfers() twice for the
	 * same transfer leads to problems thus we prevent concurrent calls
	 * by using ->dma_running.
	 */
	if (atomic_dec_and_test(&drv_data->dma_running)) {
		/*
		 * If the other CPU is still handling the ROR interrupt we
		 * might not know about the error yet. So we re-check the
		 * ROR bit here before we clear the status register.
		 */
		if (!error) {
			u32 status = pxa2xx_spi_read(drv_data, SSSR)
				     & drv_data->mask_sr;
			error = status & SSSR_ROR;
		}

		/* Clear status & disable interrupts */
		pxa2xx_spi_write(drv_data, SSCR1,
				 pxa2xx_spi_read(drv_data, SSCR1)
				 & ~drv_data->dma_cr1);
		write_SSSR_CS(drv_data, drv_data->clear_sr);
		if (!pxa25x_ssp_comp(drv_data))
			pxa2xx_spi_write(drv_data, SSTO, 0);

		if (error) {
			/* In case we got an error we disable the SSP now */
			pxa2xx_spi_write(drv_data, SSCR0,
					 pxa2xx_spi_read(drv_data, SSCR0)
					 & ~SSCR0_SSE);
			msg->status = -EIO;
		}

		spi_finalize_current_transfer(drv_data->controller);
	}
}

static void pxa2xx_spi_dma_callback(void *data)
{
	pxa2xx_spi_dma_transfer_complete(data, false);
}

static struct dma_async_tx_descriptor *
pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
			   enum dma_transfer_direction dir,
			   struct spi_transfer *xfer)
{
	struct chip_data *chip =
		spi_get_ctldata(drv_data->controller->cur_msg->spi);
	enum dma_slave_buswidth width;
	struct dma_slave_config cfg;
	struct dma_chan *chan;
	struct sg_table *sgt;
	int ret;

	switch (drv_data->n_bytes) {
	case 1:
		width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		break;
	case 2:
		width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		break;
	default:
		width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		break;
	}

	memset(&cfg, 0, sizeof(cfg));
	cfg.direction = dir;

	if (dir == DMA_MEM_TO_DEV) {
		cfg.dst_addr = drv_data->ssdr_physical;
		cfg.dst_addr_width = width;
		cfg.dst_maxburst = chip->dma_burst_size;

		sgt = &xfer->tx_sg;
		chan = drv_data->controller->dma_tx;
	} else {
		cfg.src_addr = drv_data->ssdr_physical;
		cfg.src_addr_width = width;
		cfg.src_maxburst = chip->dma_burst_size;

		sgt = &xfer->rx_sg;
		chan = drv_data->controller->dma_rx;
	}

	ret = dmaengine_slave_config(chan, &cfg);
	if (ret) {
		dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
		return NULL;
	}

	return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
}

irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
{
	u32 status;

	status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
	if (status & SSSR_ROR) {
		dev_err(&drv_data->pdev->dev, "FIFO overrun\n");

		dmaengine_terminate_async(drv_data->controller->dma_rx);
		dmaengine_terminate_async(drv_data->controller->dma_tx);

		pxa2xx_spi_dma_transfer_complete(drv_data, true);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
			   struct spi_transfer *xfer)
{
	struct dma_async_tx_descriptor *tx_desc, *rx_desc;
	int err;

	tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer);
	if (!tx_desc) {
		dev_err(&drv_data->pdev->dev,
			"failed to get DMA TX descriptor\n");
		err = -EBUSY;
		goto err_tx;
	}

	rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer);
	if (!rx_desc) {
		dev_err(&drv_data->pdev->dev,
			"failed to get DMA RX descriptor\n");
		err = -EBUSY;
		goto err_rx;
	}

	/* We are ready when RX completes */
	rx_desc->callback = pxa2xx_spi_dma_callback;
	rx_desc->callback_param = drv_data;

	dmaengine_submit(rx_desc);
	dmaengine_submit(tx_desc);
	return 0;

err_rx:
	dmaengine_terminate_async(drv_data->controller->dma_tx);
err_tx:
	return err;
}

void pxa2xx_spi_dma_start(struct driver_data *drv_data)
{
	dma_async_issue_pending(drv_data->controller->dma_rx);
	dma_async_issue_pending(drv_data->controller->dma_tx);

	atomic_set(&drv_data->dma_running, 1);
}

void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
{
	atomic_set(&drv_data->dma_running, 0);
	dmaengine_terminate_sync(drv_data->controller->dma_rx);
	dmaengine_terminate_sync(drv_data->controller->dma_tx);
}

int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
{
	struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
	struct device *dev = &drv_data->pdev->dev;
	struct spi_controller *controller = drv_data->controller;
	dma_cap_mask_t mask;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	controller->dma_tx = dma_request_slave_channel_compat(mask,
				pdata->dma_filter, pdata->tx_param, dev, "tx");
	if (!controller->dma_tx)
		return -ENODEV;

	controller->dma_rx = dma_request_slave_channel_compat(mask,
				pdata->dma_filter, pdata->rx_param, dev, "rx");
	if (!controller->dma_rx) {
		dma_release_channel(controller->dma_tx);
		controller->dma_tx = NULL;
		return -ENODEV;
	}

	return 0;
}

void pxa2xx_spi_dma_release(struct driver_data *drv_data)
{
	struct spi_controller *controller = drv_data->controller;

	if (controller->dma_rx) {
		dmaengine_terminate_sync(controller->dma_rx);
		dma_release_channel(controller->dma_rx);
		controller->dma_rx = NULL;
	}
	if (controller->dma_tx) {
		dmaengine_terminate_sync(controller->dma_tx);
		dma_release_channel(controller->dma_tx);
		controller->dma_tx = NULL;
	}
}

int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
					   struct spi_device *spi,
					   u8 bits_per_word, u32 *burst_code,
					   u32 *threshold)
{
	struct pxa2xx_spi_chip *chip_info = spi->controller_data;

	/*
	 * If the DMA burst size is given in chip_info we use that,
	 * otherwise we use the default. Also we use the default FIFO
	 * thresholds for now.
	 */
	*burst_code = chip_info ? chip_info->dma_burst_size : 1;
	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
		   | SSCR1_TxTresh(TX_THRESH_DFLT);

	return 0;
}
Commit	Line	Data
5928808e MW	1	/*
	2	* PXA2xx SPI DMA engine support.
	3	*
	4	* Copyright (C) 2013, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
5928808e MW	12	#include <linux/device.h>
	13	#include <linux/dma-mapping.h>
	14	#include <linux/dmaengine.h>
	15	#include <linux/pxa2xx_ssp.h>
	16	#include <linux/scatterlist.h>
	17	#include <linux/sizes.h>
	18	#include <linux/spi/spi.h>
	19	#include <linux/spi/pxa2xx_spi.h>
	20
	21	#include "spi-pxa2xx.h"
	22
5928808e MW	23	static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
	24	bool error)
	25	{
51eea52d	26	struct spi_message *msg = drv_data->controller->cur_msg;
5928808e MW	27
	28	/*
	29	* It is possible that one CPU is handling ROR interrupt and other
	30	* just gets DMA completion. Calling pump_transfers() twice for the
	31	* same transfer leads to problems thus we prevent concurrent calls
	32	* by using ->dma_running.
	33	*/
	34	if (atomic_dec_and_test(&drv_data->dma_running)) {
5928808e MW	35	/*
	36	* If the other CPU is still handling the ROR interrupt we
	37	* might not know about the error yet. So we re-check the
	38	* ROR bit here before we clear the status register.
	39	*/
	40	if (!error) {
c039dd27 JN	41	u32 status = pxa2xx_spi_read(drv_data, SSSR)
c039dd27 JN	42	& drv_data->mask_sr;
5928808e MW	43	error = status & SSSR_ROR;
	44	}
	45
	46	/* Clear status & disable interrupts */
c039dd27 JN	47	pxa2xx_spi_write(drv_data, SSCR1,
	48	pxa2xx_spi_read(drv_data, SSCR1)
	49	& ~drv_data->dma_cr1);
5928808e MW	50	write_SSSR_CS(drv_data, drv_data->clear_sr);
5928808e MW	51	if (!pxa25x_ssp_comp(drv_data))
c039dd27	52	pxa2xx_spi_write(drv_data, SSTO, 0);
5928808e	53
d5898e19	54	if (error) {
5928808e	55	/* In case we got an error we disable the SSP now */
c039dd27 JN	56	pxa2xx_spi_write(drv_data, SSCR0,
	57	pxa2xx_spi_read(drv_data, SSCR0)
	58	& ~SSCR0_SSE);
d5898e19	59	msg->status = -EIO;
5928808e MW	60	}
5928808e MW	61
51eea52d	62	spi_finalize_current_transfer(drv_data->controller);
5928808e MW	63	}
	64	}
	65
	66	static void pxa2xx_spi_dma_callback(void *data)
	67	{
	68	pxa2xx_spi_dma_transfer_complete(data, false);
	69	}
	70
	71	static struct dma_async_tx_descriptor *
	72	pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
d5898e19 JN	73	enum dma_transfer_direction dir,
d5898e19 JN	74	struct spi_transfer *xfer)
5928808e	75	{
96579a4e	76	struct chip_data *chip =
51eea52d	77	spi_get_ctldata(drv_data->controller->cur_msg->spi);
5928808e MW	78	enum dma_slave_buswidth width;
	79	struct dma_slave_config cfg;
	80	struct dma_chan *chan;
	81	struct sg_table *sgt;
b6ced294	82	int ret;
5928808e MW	83
	84	switch (drv_data->n_bytes) {
	85	case 1:
	86	width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	87	break;
	88	case 2:
	89	width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	90	break;
	91	default:
	92	width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	93	break;
	94	}
	95
	96	memset(&cfg, 0, sizeof(cfg));
	97	cfg.direction = dir;
	98
	99	if (dir == DMA_MEM_TO_DEV) {
	100	cfg.dst_addr = drv_data->ssdr_physical;
	101	cfg.dst_addr_width = width;
	102	cfg.dst_maxburst = chip->dma_burst_size;
5928808e	103
b6ced294	104	sgt = &xfer->tx_sg;
51eea52d	105	chan = drv_data->controller->dma_tx;
5928808e MW	106	} else {
	107	cfg.src_addr = drv_data->ssdr_physical;
	108	cfg.src_addr_width = width;
	109	cfg.src_maxburst = chip->dma_burst_size;
5928808e	110
b6ced294	111	sgt = &xfer->rx_sg;
51eea52d	112	chan = drv_data->controller->dma_rx;
5928808e MW	113	}
	114
	115	ret = dmaengine_slave_config(chan, &cfg);
	116	if (ret) {
	117	dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
	118	return NULL;
	119	}
	120
b6ced294	121	return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
5928808e MW	122	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	123	}
	124
5928808e MW	125	irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
	126	{
	127	u32 status;
	128
c039dd27	129	status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
5928808e MW	130	if (status & SSSR_ROR) {
	131	dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
	132
51eea52d LR	133	dmaengine_terminate_async(drv_data->controller->dma_rx);
51eea52d LR	134	dmaengine_terminate_async(drv_data->controller->dma_tx);
5928808e MW	135
	136	pxa2xx_spi_dma_transfer_complete(drv_data, true);
	137	return IRQ_HANDLED;
	138	}
	139
	140	return IRQ_NONE;
	141	}
	142
d5898e19 JN	143	int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
d5898e19 JN	144	struct spi_transfer *xfer)
5928808e MW	145	{
5928808e MW	146	struct dma_async_tx_descriptor tx_desc, rx_desc;
bffc967e	147	int err;
5928808e	148
d5898e19	149	tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer);
5928808e MW	150	if (!tx_desc) {
	151	dev_err(&drv_data->pdev->dev,
	152	"failed to get DMA TX descriptor\n");
7d1f1bf6 AS	153	err = -EBUSY;
7d1f1bf6 AS	154	goto err_tx;
5928808e MW	155	}
5928808e MW	156
d5898e19	157	rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer);
5928808e MW	158	if (!rx_desc) {
	159	dev_err(&drv_data->pdev->dev,
	160	"failed to get DMA RX descriptor\n");
7d1f1bf6 AS	161	err = -EBUSY;
7d1f1bf6 AS	162	goto err_rx;
5928808e MW	163	}
	164
	165	/* We are ready when RX completes */
	166	rx_desc->callback = pxa2xx_spi_dma_callback;
	167	rx_desc->callback_param = drv_data;
	168
	169	dmaengine_submit(rx_desc);
	170	dmaengine_submit(tx_desc);
	171	return 0;
7d1f1bf6 AS	172
7d1f1bf6 AS	173	err_rx:
51eea52d	174	dmaengine_terminate_async(drv_data->controller->dma_tx);
7d1f1bf6	175	err_tx:
7d1f1bf6	176	return err;
5928808e MW	177	}
	178
	179	void pxa2xx_spi_dma_start(struct driver_data *drv_data)
	180	{
51eea52d LR	181	dma_async_issue_pending(drv_data->controller->dma_rx);
51eea52d LR	182	dma_async_issue_pending(drv_data->controller->dma_tx);
5928808e MW	183
	184	atomic_set(&drv_data->dma_running, 1);
	185	}
	186
d5898e19 JN	187	void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
	188	{
	189	atomic_set(&drv_data->dma_running, 0);
51eea52d LR	190	dmaengine_terminate_sync(drv_data->controller->dma_rx);
51eea52d LR	191	dmaengine_terminate_sync(drv_data->controller->dma_tx);
d5898e19 JN	192	}
d5898e19 JN	193
5928808e MW	194	int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
5928808e MW	195	{
51eea52d	196	struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
cddb339b	197	struct device *dev = &drv_data->pdev->dev;
51eea52d	198	struct spi_controller *controller = drv_data->controller;
5928808e MW	199	dma_cap_mask_t mask;
	200
	201	dma_cap_zero(mask);
	202	dma_cap_set(DMA_SLAVE, mask);
	203
51eea52d	204	controller->dma_tx = dma_request_slave_channel_compat(mask,
b729bf34	205	pdata->dma_filter, pdata->tx_param, dev, "tx");
51eea52d	206	if (!controller->dma_tx)
5928808e MW	207	return -ENODEV;
5928808e MW	208
51eea52d	209	controller->dma_rx = dma_request_slave_channel_compat(mask,
b729bf34	210	pdata->dma_filter, pdata->rx_param, dev, "rx");
51eea52d LR	211	if (!controller->dma_rx) {
	212	dma_release_channel(controller->dma_tx);
	213	controller->dma_tx = NULL;
5928808e MW	214	return -ENODEV;
	215	}
	216
	217	return 0;
	218	}
	219
	220	void pxa2xx_spi_dma_release(struct driver_data *drv_data)
	221	{
51eea52d	222	struct spi_controller *controller = drv_data->controller;
b6ced294	223
51eea52d LR	224	if (controller->dma_rx) {
	225	dmaengine_terminate_sync(controller->dma_rx);
	226	dma_release_channel(controller->dma_rx);
	227	controller->dma_rx = NULL;
5928808e	228	}
51eea52d LR	229	if (controller->dma_tx) {
	230	dmaengine_terminate_sync(controller->dma_tx);
	231	dma_release_channel(controller->dma_tx);
	232	controller->dma_tx = NULL;
5928808e MW	233	}
	234	}
	235
5928808e MW	236	int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
	237	struct spi_device *spi,
	238	u8 bits_per_word, u32 *burst_code,
	239	u32 *threshold)
	240	{
	241	struct pxa2xx_spi_chip *chip_info = spi->controller_data;
	242
	243	/*
	244	* If the DMA burst size is given in chip_info we use that,
	245	* otherwise we use the default. Also we use the default FIFO
	246	* thresholds for now.
	247	*/
01d7aafb	248	*burst_code = chip_info ? chip_info->dma_burst_size : 1;
5928808e MW	249	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
	250	\| SSCR1_TxTresh(TX_THRESH_DFLT);
	251
	252	return 0;
	253	}