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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
44dab88e SF |
2 | /* |
3 | * SPI_PPC4XX SPI controller driver. | |
4 | * | |
5 | * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de> | |
6 | * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering | |
7 | * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com> | |
8 | * | |
9 | * Based in part on drivers/spi/spi_s3c24xx.c | |
10 | * | |
11 | * Copyright (c) 2006 Ben Dooks | |
12 | * Copyright (c) 2006 Simtec Electronics | |
13 | * Ben Dooks <ben@simtec.co.uk> | |
44dab88e SF |
14 | */ |
15 | ||
16 | /* | |
17 | * The PPC4xx SPI controller has no FIFO so each sent/received byte will | |
18 | * generate an interrupt to the CPU. This can cause high CPU utilization. | |
19 | * This driver allows platforms to reduce the interrupt load on the CPU | |
20 | * during SPI transfers by setting max_speed_hz via the device tree. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
44dab88e | 24 | #include <linux/sched.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
44dab88e SF |
26 | #include <linux/errno.h> |
27 | #include <linux/wait.h> | |
9f208e09 | 28 | #include <linux/platform_device.h> |
c11eede6 RH |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
44dab88e | 31 | #include <linux/of_platform.h> |
44dab88e SF |
32 | #include <linux/interrupt.h> |
33 | #include <linux/delay.h> | |
6f98e449 | 34 | #include <linux/platform_device.h> |
44dab88e | 35 | |
44dab88e SF |
36 | #include <linux/spi/spi.h> |
37 | #include <linux/spi/spi_bitbang.h> | |
38 | ||
66fe7403 | 39 | #include <linux/io.h> |
44dab88e SF |
40 | #include <asm/dcr.h> |
41 | #include <asm/dcr-regs.h> | |
42 | ||
43 | /* bits in mode register - bit 0 is MSb */ | |
44 | ||
45 | /* | |
46 | * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock" | |
47 | * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock" | |
48 | * Note: This is the inverse of CPHA. | |
49 | */ | |
50 | #define SPI_PPC4XX_MODE_SCP (0x80 >> 3) | |
51 | ||
52 | /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */ | |
53 | #define SPI_PPC4XX_MODE_SPE (0x80 >> 4) | |
54 | ||
55 | /* | |
56 | * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode | |
57 | * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode | |
58 | * Note: This is identical to SPI_LSB_FIRST. | |
59 | */ | |
60 | #define SPI_PPC4XX_MODE_RD (0x80 >> 5) | |
61 | ||
62 | /* | |
63 | * SPI_PPC4XX_MODE_CI = 0 means "clock idles low" | |
64 | * SPI_PPC4XX_MODE_CI = 1 means "clock idles high" | |
65 | * Note: This is identical to CPOL. | |
66 | */ | |
67 | #define SPI_PPC4XX_MODE_CI (0x80 >> 6) | |
68 | ||
69 | /* | |
70 | * SPI_PPC4XX_MODE_IL = 0 means "loopback disable" | |
71 | * SPI_PPC4XX_MODE_IL = 1 means "loopback enable" | |
72 | */ | |
73 | #define SPI_PPC4XX_MODE_IL (0x80 >> 7) | |
74 | ||
75 | /* bits in control register */ | |
76 | /* starts a transfer when set */ | |
77 | #define SPI_PPC4XX_CR_STR (0x80 >> 7) | |
78 | ||
79 | /* bits in status register */ | |
80 | /* port is busy with a transfer */ | |
81 | #define SPI_PPC4XX_SR_BSY (0x80 >> 6) | |
82 | /* RxD ready */ | |
83 | #define SPI_PPC4XX_SR_RBR (0x80 >> 7) | |
84 | ||
85 | /* clock settings (SCP and CI) for various SPI modes */ | |
86 | #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0) | |
87 | #define SPI_CLK_MODE1 (0 | 0) | |
88 | #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI) | |
89 | #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI) | |
90 | ||
91 | #define DRIVER_NAME "spi_ppc4xx_of" | |
92 | ||
93 | struct spi_ppc4xx_regs { | |
94 | u8 mode; | |
95 | u8 rxd; | |
96 | u8 txd; | |
97 | u8 cr; | |
98 | u8 sr; | |
99 | u8 dummy; | |
100 | /* | |
101 | * Clock divisor modulus register | |
886db6ac | 102 | * This uses the following formula: |
44dab88e SF |
103 | * SCPClkOut = OPBCLK/(4(CDM + 1)) |
104 | * or | |
105 | * CDM = (OPBCLK/4*SCPClkOut) - 1 | |
106 | * bit 0 is the MSb! | |
107 | */ | |
108 | u8 cdm; | |
109 | }; | |
110 | ||
111 | /* SPI Controller driver's private data. */ | |
112 | struct ppc4xx_spi { | |
113 | /* bitbang has to be first */ | |
114 | struct spi_bitbang bitbang; | |
115 | struct completion done; | |
116 | ||
117 | u64 mapbase; | |
118 | u64 mapsize; | |
119 | int irqnum; | |
120 | /* need this to set the SPI clock */ | |
121 | unsigned int opb_freq; | |
122 | ||
123 | /* for transfers */ | |
124 | int len; | |
125 | int count; | |
126 | /* data buffers */ | |
127 | const unsigned char *tx; | |
128 | unsigned char *rx; | |
129 | ||
44dab88e | 130 | struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */ |
71345830 | 131 | struct spi_controller *host; |
44dab88e SF |
132 | struct device *dev; |
133 | }; | |
134 | ||
135 | /* need this so we can set the clock in the chipselect routine */ | |
136 | struct spi_ppc4xx_cs { | |
137 | u8 mode; | |
138 | }; | |
139 | ||
140 | static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t) | |
141 | { | |
142 | struct ppc4xx_spi *hw; | |
143 | u8 data; | |
144 | ||
145 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | |
146 | t->tx_buf, t->rx_buf, t->len); | |
147 | ||
71345830 | 148 | hw = spi_controller_get_devdata(spi->controller); |
44dab88e SF |
149 | |
150 | hw->tx = t->tx_buf; | |
151 | hw->rx = t->rx_buf; | |
152 | hw->len = t->len; | |
153 | hw->count = 0; | |
154 | ||
155 | /* send the first byte */ | |
156 | data = hw->tx ? hw->tx[0] : 0; | |
157 | out_8(&hw->regs->txd, data); | |
158 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); | |
159 | wait_for_completion(&hw->done); | |
160 | ||
161 | return hw->count; | |
162 | } | |
163 | ||
164 | static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |
165 | { | |
71345830 | 166 | struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller); |
44dab88e SF |
167 | struct spi_ppc4xx_cs *cs = spi->controller_state; |
168 | int scr; | |
169 | u8 cdm = 0; | |
170 | u32 speed; | |
44dab88e SF |
171 | |
172 | /* Start with the generic configuration for this device. */ | |
44dab88e SF |
173 | speed = spi->max_speed_hz; |
174 | ||
175 | /* | |
176 | * Modify the configuration if the transfer overrides it. Do not allow | |
177 | * the transfer to overwrite the generic configuration with zeros. | |
178 | */ | |
179 | if (t) { | |
44dab88e SF |
180 | if (t->speed_hz) |
181 | speed = min(t->speed_hz, spi->max_speed_hz); | |
182 | } | |
183 | ||
44dab88e SF |
184 | if (!speed || (speed > spi->max_speed_hz)) { |
185 | dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); | |
186 | return -EINVAL; | |
187 | } | |
188 | ||
886db6ac | 189 | /* Write new configuration */ |
44dab88e SF |
190 | out_8(&hw->regs->mode, cs->mode); |
191 | ||
192 | /* Set the clock */ | |
193 | /* opb_freq was already divided by 4 */ | |
194 | scr = (hw->opb_freq / speed) - 1; | |
195 | if (scr > 0) | |
196 | cdm = min(scr, 0xff); | |
197 | ||
198 | dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); | |
199 | ||
200 | if (in_8(&hw->regs->cdm) != cdm) | |
201 | out_8(&hw->regs->cdm, cdm); | |
202 | ||
c15f6ed3 | 203 | mutex_lock(&hw->bitbang.lock); |
44dab88e SF |
204 | if (!hw->bitbang.busy) { |
205 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
206 | /* Need to ndelay here? */ | |
207 | } | |
c15f6ed3 | 208 | mutex_unlock(&hw->bitbang.lock); |
44dab88e SF |
209 | |
210 | return 0; | |
211 | } | |
212 | ||
213 | static int spi_ppc4xx_setup(struct spi_device *spi) | |
214 | { | |
215 | struct spi_ppc4xx_cs *cs = spi->controller_state; | |
216 | ||
44dab88e SF |
217 | if (!spi->max_speed_hz) { |
218 | dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n"); | |
219 | return -EINVAL; | |
220 | } | |
221 | ||
222 | if (cs == NULL) { | |
07c74f84 | 223 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
44dab88e SF |
224 | if (!cs) |
225 | return -ENOMEM; | |
226 | spi->controller_state = cs; | |
227 | } | |
228 | ||
229 | /* | |
230 | * We set all bits of the SPI0_MODE register, so, | |
231 | * no need to read-modify-write | |
232 | */ | |
233 | cs->mode = SPI_PPC4XX_MODE_SPE; | |
234 | ||
4ccf0557 | 235 | switch (spi->mode & SPI_MODE_X_MASK) { |
44dab88e SF |
236 | case SPI_MODE_0: |
237 | cs->mode |= SPI_CLK_MODE0; | |
238 | break; | |
239 | case SPI_MODE_1: | |
240 | cs->mode |= SPI_CLK_MODE1; | |
241 | break; | |
242 | case SPI_MODE_2: | |
243 | cs->mode |= SPI_CLK_MODE2; | |
244 | break; | |
245 | case SPI_MODE_3: | |
246 | cs->mode |= SPI_CLK_MODE3; | |
247 | break; | |
248 | } | |
249 | ||
250 | if (spi->mode & SPI_LSB_FIRST) | |
251 | cs->mode |= SPI_PPC4XX_MODE_RD; | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
44dab88e SF |
256 | static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id) |
257 | { | |
258 | struct ppc4xx_spi *hw; | |
259 | u8 status; | |
260 | u8 data; | |
261 | unsigned int count; | |
262 | ||
263 | hw = (struct ppc4xx_spi *)dev_id; | |
264 | ||
265 | status = in_8(&hw->regs->sr); | |
266 | if (!status) | |
267 | return IRQ_NONE; | |
268 | ||
269 | /* | |
270 | * BSY de-asserts one cycle after the transfer is complete. The | |
271 | * interrupt is asserted after the transfer is complete. The exact | |
272 | * relationship is not documented, hence this code. | |
273 | */ | |
274 | ||
275 | if (unlikely(status & SPI_PPC4XX_SR_BSY)) { | |
276 | u8 lstatus; | |
277 | int cnt = 0; | |
278 | ||
279 | dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); | |
280 | do { | |
281 | ndelay(10); | |
282 | lstatus = in_8(&hw->regs->sr); | |
283 | } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY); | |
284 | ||
285 | if (cnt >= 100) { | |
286 | dev_err(hw->dev, "busywait: too many loops!\n"); | |
287 | complete(&hw->done); | |
288 | return IRQ_HANDLED; | |
289 | } else { | |
290 | /* status is always 1 (RBR) here */ | |
291 | status = in_8(&hw->regs->sr); | |
292 | dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); | |
293 | } | |
294 | } | |
295 | ||
296 | count = hw->count; | |
297 | hw->count++; | |
298 | ||
299 | /* RBR triggered this interrupt. Therefore, data must be ready. */ | |
300 | data = in_8(&hw->regs->rxd); | |
301 | if (hw->rx) | |
302 | hw->rx[count] = data; | |
303 | ||
304 | count++; | |
305 | ||
306 | if (count < hw->len) { | |
307 | data = hw->tx ? hw->tx[count] : 0; | |
308 | out_8(&hw->regs->txd, data); | |
309 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); | |
310 | } else { | |
311 | complete(&hw->done); | |
312 | } | |
313 | ||
314 | return IRQ_HANDLED; | |
315 | } | |
316 | ||
317 | static void spi_ppc4xx_cleanup(struct spi_device *spi) | |
318 | { | |
319 | kfree(spi->controller_state); | |
320 | } | |
321 | ||
322 | static void spi_ppc4xx_enable(struct ppc4xx_spi *hw) | |
323 | { | |
324 | /* | |
325 | * On all 4xx PPC's the SPI bus is shared/multiplexed with | |
db56d030 | 326 | * the 2nd I2C bus. We need to enable the SPI bus before |
44dab88e SF |
327 | * using it. |
328 | */ | |
329 | ||
330 | /* need to clear bit 14 to enable SPC */ | |
331 | dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0); | |
332 | } | |
333 | ||
44dab88e | 334 | /* |
2dc11581 | 335 | * platform_device layer stuff... |
44dab88e | 336 | */ |
2deff8d6 | 337 | static int spi_ppc4xx_of_probe(struct platform_device *op) |
44dab88e SF |
338 | { |
339 | struct ppc4xx_spi *hw; | |
71345830 | 340 | struct spi_controller *host; |
44dab88e SF |
341 | struct spi_bitbang *bbp; |
342 | struct resource resource; | |
b5355078 | 343 | struct device_node *np = op->dev.of_node; |
44dab88e SF |
344 | struct device *dev = &op->dev; |
345 | struct device_node *opbnp; | |
346 | int ret; | |
44dab88e SF |
347 | const unsigned int *clk; |
348 | ||
71345830 YY |
349 | host = spi_alloc_host(dev, sizeof(*hw)); |
350 | if (host == NULL) | |
44dab88e | 351 | return -ENOMEM; |
71345830 YY |
352 | host->dev.of_node = np; |
353 | platform_set_drvdata(op, host); | |
354 | hw = spi_controller_get_devdata(host); | |
355 | hw->host = host; | |
44dab88e SF |
356 | hw->dev = dev; |
357 | ||
358 | init_completion(&hw->done); | |
359 | ||
44dab88e SF |
360 | /* Setup the state for the bitbang driver */ |
361 | bbp = &hw->bitbang; | |
d748b48e | 362 | bbp->ctlr = hw->host; |
44dab88e | 363 | bbp->setup_transfer = spi_ppc4xx_setupxfer; |
44dab88e SF |
364 | bbp->txrx_bufs = spi_ppc4xx_txrx; |
365 | bbp->use_dma = 0; | |
d748b48e UKK |
366 | bbp->ctlr->setup = spi_ppc4xx_setup; |
367 | bbp->ctlr->cleanup = spi_ppc4xx_cleanup; | |
368 | bbp->ctlr->bits_per_word_mask = SPI_BPW_MASK(8); | |
369 | bbp->ctlr->use_gpio_descriptors = true; | |
47267732 LW |
370 | /* |
371 | * The SPI core will count the number of GPIO descriptors to figure | |
372 | * out the number of chip selects available on the platform. | |
373 | */ | |
d748b48e | 374 | bbp->ctlr->num_chipselect = 0; |
44dab88e | 375 | |
44dab88e | 376 | /* the spi->mode bits understood by this driver: */ |
d748b48e | 377 | bbp->ctlr->mode_bits = |
44dab88e SF |
378 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; |
379 | ||
44dab88e SF |
380 | /* Get the clock for the OPB */ |
381 | opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); | |
382 | if (opbnp == NULL) { | |
383 | dev_err(dev, "OPB: cannot find node\n"); | |
384 | ret = -ENODEV; | |
71345830 | 385 | goto free_host; |
44dab88e SF |
386 | } |
387 | /* Get the clock (Hz) for the OPB */ | |
388 | clk = of_get_property(opbnp, "clock-frequency", NULL); | |
389 | if (clk == NULL) { | |
390 | dev_err(dev, "OPB: no clock-frequency property set\n"); | |
391 | of_node_put(opbnp); | |
392 | ret = -ENODEV; | |
71345830 | 393 | goto free_host; |
44dab88e SF |
394 | } |
395 | hw->opb_freq = *clk; | |
396 | hw->opb_freq >>= 2; | |
397 | of_node_put(opbnp); | |
398 | ||
399 | ret = of_address_to_resource(np, 0, &resource); | |
400 | if (ret) { | |
401 | dev_err(dev, "error while parsing device node resource\n"); | |
71345830 | 402 | goto free_host; |
44dab88e SF |
403 | } |
404 | hw->mapbase = resource.start; | |
8e2943c0 | 405 | hw->mapsize = resource_size(&resource); |
44dab88e SF |
406 | |
407 | /* Sanity check */ | |
408 | if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { | |
409 | dev_err(dev, "too small to map registers\n"); | |
410 | ret = -EINVAL; | |
71345830 | 411 | goto free_host; |
44dab88e SF |
412 | } |
413 | ||
414 | /* Request IRQ */ | |
415 | hw->irqnum = irq_of_parse_and_map(np, 0); | |
416 | ret = request_irq(hw->irqnum, spi_ppc4xx_int, | |
38ada214 | 417 | 0, "spi_ppc4xx_of", (void *)hw); |
44dab88e SF |
418 | if (ret) { |
419 | dev_err(dev, "unable to allocate interrupt\n"); | |
71345830 | 420 | goto free_host; |
44dab88e SF |
421 | } |
422 | ||
423 | if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { | |
424 | dev_err(dev, "resource unavailable\n"); | |
425 | ret = -EBUSY; | |
426 | goto request_mem_error; | |
427 | } | |
428 | ||
429 | hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); | |
430 | ||
431 | if (!hw->regs) { | |
432 | dev_err(dev, "unable to memory map registers\n"); | |
433 | ret = -ENXIO; | |
434 | goto map_io_error; | |
435 | } | |
436 | ||
437 | spi_ppc4xx_enable(hw); | |
438 | ||
439 | /* Finally register our spi controller */ | |
440 | dev->dma_mask = 0; | |
441 | ret = spi_bitbang_start(bbp); | |
442 | if (ret) { | |
71345830 | 443 | dev_err(dev, "failed to register SPI host\n"); |
44dab88e SF |
444 | goto unmap_regs; |
445 | } | |
446 | ||
447 | dev_info(dev, "driver initialized\n"); | |
44dab88e SF |
448 | |
449 | return 0; | |
450 | ||
451 | unmap_regs: | |
452 | iounmap(hw->regs); | |
453 | map_io_error: | |
454 | release_mem_region(hw->mapbase, hw->mapsize); | |
455 | request_mem_error: | |
456 | free_irq(hw->irqnum, hw); | |
71345830 YY |
457 | free_host: |
458 | spi_controller_put(host); | |
44dab88e SF |
459 | |
460 | dev_err(dev, "initialization failed\n"); | |
461 | return ret; | |
462 | } | |
463 | ||
224d9437 | 464 | static void spi_ppc4xx_of_remove(struct platform_device *op) |
44dab88e | 465 | { |
71345830 YY |
466 | struct spi_controller *host = platform_get_drvdata(op); |
467 | struct ppc4xx_spi *hw = spi_controller_get_devdata(host); | |
44dab88e SF |
468 | |
469 | spi_bitbang_stop(&hw->bitbang); | |
44dab88e SF |
470 | release_mem_region(hw->mapbase, hw->mapsize); |
471 | free_irq(hw->irqnum, hw); | |
472 | iounmap(hw->regs); | |
71345830 | 473 | spi_controller_put(host); |
44dab88e SF |
474 | } |
475 | ||
631e61b7 | 476 | static const struct of_device_id spi_ppc4xx_of_match[] = { |
44dab88e SF |
477 | { .compatible = "ibm,ppc4xx-spi", }, |
478 | {}, | |
479 | }; | |
480 | ||
481 | MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match); | |
482 | ||
18d306d1 | 483 | static struct platform_driver spi_ppc4xx_of_driver = { |
44dab88e | 484 | .probe = spi_ppc4xx_of_probe, |
224d9437 | 485 | .remove_new = spi_ppc4xx_of_remove, |
44dab88e SF |
486 | .driver = { |
487 | .name = DRIVER_NAME, | |
4018294b | 488 | .of_match_table = spi_ppc4xx_of_match, |
44dab88e SF |
489 | }, |
490 | }; | |
940ab889 | 491 | module_platform_driver(spi_ppc4xx_of_driver); |
44dab88e SF |
492 | |
493 | MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); | |
494 | MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); | |
495 | MODULE_LICENSE("GPL"); |