Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
60cadec9 | 2 | /* |
ca632f55 | 3 | * Marvell Orion SPI controller driver |
60cadec9 SA |
4 | * |
5 | * Author: Shadi Ammouri <shadi@marvell.com> | |
6 | * Copyright (C) 2007-2008 Marvell Ltd. | |
60cadec9 SA |
7 | */ |
8 | ||
60cadec9 SA |
9 | #include <linux/interrupt.h> |
10 | #include <linux/delay.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/spi/spi.h> | |
d7614de4 | 15 | #include <linux/module.h> |
5c678694 | 16 | #include <linux/pm_runtime.h> |
f814f9ac | 17 | #include <linux/of.h> |
b3c195b3 | 18 | #include <linux/of_address.h> |
df59fa7f | 19 | #include <linux/of_device.h> |
fb9acf5f | 20 | #include <linux/of_gpio.h> |
4574b886 | 21 | #include <linux/clk.h> |
895248f8 | 22 | #include <linux/sizes.h> |
b28b9149 | 23 | #include <linux/gpio.h> |
60cadec9 SA |
24 | #include <asm/unaligned.h> |
25 | ||
26 | #define DRIVER_NAME "orion_spi" | |
27 | ||
5c678694 RK |
28 | /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ |
29 | #define SPI_AUTOSUSPEND_TIMEOUT 200 | |
30 | ||
23244404 KW |
31 | /* Some SoCs using this driver support up to 8 chip selects. |
32 | * It is up to the implementer to only use the chip selects | |
33 | * that are available. | |
34 | */ | |
35 | #define ORION_NUM_CHIPSELECTS 8 | |
36 | ||
60cadec9 SA |
37 | #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ |
38 | ||
39 | #define ORION_SPI_IF_CTRL_REG 0x00 | |
40 | #define ORION_SPI_IF_CONFIG_REG 0x04 | |
1017f424 BS |
41 | #define ORION_SPI_IF_RXLSBF BIT(14) |
42 | #define ORION_SPI_IF_TXLSBF BIT(13) | |
60cadec9 SA |
43 | #define ORION_SPI_DATA_OUT_REG 0x08 |
44 | #define ORION_SPI_DATA_IN_REG 0x0c | |
45 | #define ORION_SPI_INT_CAUSE_REG 0x10 | |
38d6211e NH |
46 | #define ORION_SPI_TIMING_PARAMS_REG 0x18 |
47 | ||
b3c195b3 SR |
48 | /* Register for the "Direct Mode" */ |
49 | #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 | |
50 | ||
38d6211e NH |
51 | #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) |
52 | #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) | |
53 | #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) | |
60cadec9 | 54 | |
b15d5d70 JG |
55 | #define ORION_SPI_MODE_CPOL (1 << 11) |
56 | #define ORION_SPI_MODE_CPHA (1 << 12) | |
60cadec9 SA |
57 | #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) |
58 | #define ORION_SPI_CLK_PRESCALE_MASK 0x1F | |
df59fa7f | 59 | #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF |
b15d5d70 JG |
60 | #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ |
61 | ORION_SPI_MODE_CPHA) | |
23244404 KW |
62 | #define ORION_SPI_CS_MASK 0x1C |
63 | #define ORION_SPI_CS_SHIFT 2 | |
64 | #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ | |
65 | ORION_SPI_CS_MASK) | |
60cadec9 | 66 | |
df59fa7f GU |
67 | enum orion_spi_type { |
68 | ORION_SPI, | |
69 | ARMADA_SPI, | |
70 | }; | |
71 | ||
72 | struct orion_spi_dev { | |
73 | enum orion_spi_type typ; | |
ce2f6ea1 GC |
74 | /* |
75 | * min_divisor and max_hz should be exclusive, the only we can | |
76 | * have both is for managing the armada-370-spi case with old | |
77 | * device tree | |
78 | */ | |
79 | unsigned long max_hz; | |
df59fa7f GU |
80 | unsigned int min_divisor; |
81 | unsigned int max_divisor; | |
82 | u32 prescale_mask; | |
38d6211e | 83 | bool is_errata_50mhz_ac; |
df59fa7f GU |
84 | }; |
85 | ||
b3c195b3 SR |
86 | struct orion_direct_acc { |
87 | void __iomem *vaddr; | |
88 | u32 size; | |
89 | }; | |
90 | ||
5c22af7e JK |
91 | struct orion_child_options { |
92 | struct orion_direct_acc direct_access; | |
93 | }; | |
94 | ||
60cadec9 | 95 | struct orion_spi { |
60cadec9 SA |
96 | struct spi_master *master; |
97 | void __iomem *base; | |
4574b886 | 98 | struct clk *clk; |
92ae112e | 99 | struct clk *axi_clk; |
df59fa7f | 100 | const struct orion_spi_dev *devdata; |
54424862 | 101 | int unused_hw_gpio; |
b3c195b3 | 102 | |
5c22af7e | 103 | struct orion_child_options child[ORION_NUM_CHIPSELECTS]; |
60cadec9 SA |
104 | }; |
105 | ||
60cadec9 SA |
106 | static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
107 | { | |
108 | return orion_spi->base + reg; | |
109 | } | |
110 | ||
111 | static inline void | |
112 | orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
113 | { | |
114 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
115 | u32 val; | |
116 | ||
117 | val = readl(reg_addr); | |
118 | val |= mask; | |
119 | writel(val, reg_addr); | |
120 | } | |
121 | ||
122 | static inline void | |
123 | orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
124 | { | |
125 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
126 | u32 val; | |
127 | ||
128 | val = readl(reg_addr); | |
129 | val &= ~mask; | |
130 | writel(val, reg_addr); | |
131 | } | |
132 | ||
60cadec9 SA |
133 | static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) |
134 | { | |
135 | u32 tclk_hz; | |
136 | u32 rate; | |
137 | u32 prescale; | |
138 | u32 reg; | |
139 | struct orion_spi *orion_spi; | |
df59fa7f | 140 | const struct orion_spi_dev *devdata; |
60cadec9 SA |
141 | |
142 | orion_spi = spi_master_get_devdata(spi->master); | |
df59fa7f | 143 | devdata = orion_spi->devdata; |
60cadec9 | 144 | |
4574b886 | 145 | tclk_hz = clk_get_rate(orion_spi->clk); |
60cadec9 | 146 | |
df59fa7f | 147 | if (devdata->typ == ARMADA_SPI) { |
7243e0b2 UKK |
148 | /* |
149 | * Given the core_clk (tclk_hz) and the target rate (speed) we | |
150 | * determine the best values for SPR (in [0 .. 15]) and SPPR (in | |
151 | * [0..7]) such that | |
152 | * | |
153 | * core_clk / (SPR * 2 ** SPPR) | |
154 | * | |
155 | * is as big as possible but not bigger than speed. | |
156 | */ | |
60cadec9 | 157 | |
7243e0b2 UKK |
158 | /* best integer divider: */ |
159 | unsigned divider = DIV_ROUND_UP(tclk_hz, speed); | |
160 | unsigned spr, sppr; | |
161 | ||
162 | if (divider < 16) { | |
163 | /* This is the easy case, divider is less than 16 */ | |
164 | spr = divider; | |
165 | sppr = 0; | |
166 | ||
167 | } else { | |
168 | unsigned two_pow_sppr; | |
169 | /* | |
170 | * Find the highest bit set in divider. This and the | |
171 | * three next bits define SPR (apart from rounding). | |
172 | * SPPR is then the number of zero bits that must be | |
173 | * appended: | |
174 | */ | |
175 | sppr = fls(divider) - 4; | |
176 | ||
177 | /* | |
178 | * As SPR only has 4 bits, we have to round divider up | |
179 | * to the next multiple of 2 ** sppr. | |
180 | */ | |
181 | two_pow_sppr = 1 << sppr; | |
182 | divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; | |
183 | ||
184 | /* | |
185 | * recalculate sppr as rounding up divider might have | |
186 | * increased it enough to change the position of the | |
187 | * highest set bit. In this case the bit that now | |
188 | * doesn't make it into SPR is 0, so there is no need to | |
189 | * round again. | |
190 | */ | |
191 | sppr = fls(divider) - 4; | |
192 | spr = divider >> sppr; | |
193 | ||
194 | /* | |
195 | * Now do range checking. SPR is constructed to have a | |
196 | * width of 4 bits, so this is fine for sure. So we | |
197 | * still need to check for sppr to fit into 3 bits: | |
198 | */ | |
199 | if (sppr > 7) | |
200 | return -EINVAL; | |
201 | } | |
df59fa7f | 202 | |
7243e0b2 | 203 | prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; |
df59fa7f GU |
204 | } else { |
205 | /* | |
206 | * the supported rates are: 4,6,8...30 | |
207 | * round up as we look for equal or less speed | |
208 | */ | |
209 | rate = DIV_ROUND_UP(tclk_hz, speed); | |
210 | rate = roundup(rate, 2); | |
211 | ||
212 | /* check if requested speed is too small */ | |
213 | if (rate > 30) | |
214 | return -EINVAL; | |
60cadec9 | 215 | |
df59fa7f GU |
216 | if (rate < 4) |
217 | rate = 4; | |
218 | ||
219 | /* Convert the rate to SPI clock divisor value. */ | |
220 | prescale = 0x10 + rate/2; | |
221 | } | |
60cadec9 SA |
222 | |
223 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
df59fa7f | 224 | reg = ((reg & ~devdata->prescale_mask) | prescale); |
60cadec9 SA |
225 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
b15d5d70 JG |
230 | static void |
231 | orion_spi_mode_set(struct spi_device *spi) | |
232 | { | |
233 | u32 reg; | |
234 | struct orion_spi *orion_spi; | |
235 | ||
236 | orion_spi = spi_master_get_devdata(spi->master); | |
237 | ||
238 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
239 | reg &= ~ORION_SPI_MODE_MASK; | |
240 | if (spi->mode & SPI_CPOL) | |
241 | reg |= ORION_SPI_MODE_CPOL; | |
242 | if (spi->mode & SPI_CPHA) | |
243 | reg |= ORION_SPI_MODE_CPHA; | |
1017f424 BS |
244 | if (spi->mode & SPI_LSB_FIRST) |
245 | reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; | |
246 | else | |
247 | reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); | |
248 | ||
b15d5d70 JG |
249 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
250 | } | |
251 | ||
38d6211e NH |
252 | static void |
253 | orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) | |
254 | { | |
255 | u32 reg; | |
256 | struct orion_spi *orion_spi; | |
257 | ||
258 | orion_spi = spi_master_get_devdata(spi->master); | |
259 | ||
260 | /* | |
261 | * Erratum description: (Erratum NO. FE-9144572) The device | |
262 | * SPI interface supports frequencies of up to 50 MHz. | |
263 | * However, due to this erratum, when the device core clock is | |
264 | * 250 MHz and the SPI interfaces is configured for 50MHz SPI | |
265 | * clock and CPOL=CPHA=1 there might occur data corruption on | |
266 | * reads from the SPI device. | |
267 | * Erratum Workaround: | |
268 | * Work in one of the following configurations: | |
269 | * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration | |
270 | * Register". | |
271 | * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 | |
272 | * Register" before setting the interface. | |
273 | */ | |
274 | reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); | |
275 | reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; | |
276 | ||
277 | if (clk_get_rate(orion_spi->clk) == 250000000 && | |
278 | speed == 50000000 && spi->mode & SPI_CPOL && | |
279 | spi->mode & SPI_CPHA) | |
280 | reg |= ORION_SPI_TMISO_SAMPLE_2; | |
281 | else | |
282 | reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ | |
283 | ||
284 | writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); | |
285 | } | |
286 | ||
60cadec9 SA |
287 | /* |
288 | * called only when no transfer is active on the bus | |
289 | */ | |
290 | static int | |
291 | orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
292 | { | |
293 | struct orion_spi *orion_spi; | |
294 | unsigned int speed = spi->max_speed_hz; | |
295 | unsigned int bits_per_word = spi->bits_per_word; | |
296 | int rc; | |
297 | ||
298 | orion_spi = spi_master_get_devdata(spi->master); | |
299 | ||
300 | if ((t != NULL) && t->speed_hz) | |
301 | speed = t->speed_hz; | |
302 | ||
303 | if ((t != NULL) && t->bits_per_word) | |
304 | bits_per_word = t->bits_per_word; | |
305 | ||
b15d5d70 JG |
306 | orion_spi_mode_set(spi); |
307 | ||
38d6211e NH |
308 | if (orion_spi->devdata->is_errata_50mhz_ac) |
309 | orion_spi_50mhz_ac_timing_erratum(spi, speed); | |
310 | ||
60cadec9 SA |
311 | rc = orion_spi_baudrate_set(spi, speed); |
312 | if (rc) | |
313 | return rc; | |
314 | ||
495b3358 AL |
315 | if (bits_per_word == 16) |
316 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
317 | ORION_SPI_IF_8_16_BIT_MODE); | |
318 | else | |
319 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
320 | ORION_SPI_IF_8_16_BIT_MODE); | |
321 | ||
322 | return 0; | |
60cadec9 SA |
323 | } |
324 | ||
75872ebe | 325 | static void orion_spi_set_cs(struct spi_device *spi, bool enable) |
60cadec9 | 326 | { |
75872ebe | 327 | struct orion_spi *orion_spi; |
b28b9149 CP |
328 | int cs; |
329 | ||
54424862 JK |
330 | orion_spi = spi_master_get_devdata(spi->master); |
331 | ||
b28b9149 | 332 | if (gpio_is_valid(spi->cs_gpio)) |
54424862 | 333 | cs = orion_spi->unused_hw_gpio; |
b28b9149 CP |
334 | else |
335 | cs = spi->chip_select; | |
75872ebe | 336 | |
23244404 KW |
337 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); |
338 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, | |
b28b9149 | 339 | ORION_SPI_CS(cs)); |
23244404 | 340 | |
75872ebe KW |
341 | /* Chip select logic is inverted from spi_set_cs */ |
342 | if (!enable) | |
60cadec9 SA |
343 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
344 | else | |
345 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); | |
346 | } | |
347 | ||
348 | static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) | |
349 | { | |
350 | int i; | |
351 | ||
352 | for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { | |
353 | if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) | |
354 | return 1; | |
b8434048 JH |
355 | |
356 | udelay(1); | |
60cadec9 SA |
357 | } |
358 | ||
359 | return -1; | |
360 | } | |
361 | ||
362 | static inline int | |
363 | orion_spi_write_read_8bit(struct spi_device *spi, | |
364 | const u8 **tx_buf, u8 **rx_buf) | |
365 | { | |
366 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
367 | struct orion_spi *orion_spi; | |
368 | ||
369 | orion_spi = spi_master_get_devdata(spi->master); | |
370 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
371 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
372 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
373 | ||
374 | /* clear the interrupt cause register */ | |
375 | writel(0x0, int_reg); | |
376 | ||
377 | if (tx_buf && *tx_buf) | |
378 | writel(*(*tx_buf)++, tx_reg); | |
379 | else | |
380 | writel(0, tx_reg); | |
381 | ||
382 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
383 | dev_err(&spi->dev, "TXS timed out\n"); | |
384 | return -1; | |
385 | } | |
386 | ||
387 | if (rx_buf && *rx_buf) | |
388 | *(*rx_buf)++ = readl(rx_reg); | |
389 | ||
390 | return 1; | |
391 | } | |
392 | ||
393 | static inline int | |
394 | orion_spi_write_read_16bit(struct spi_device *spi, | |
395 | const u16 **tx_buf, u16 **rx_buf) | |
396 | { | |
397 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
398 | struct orion_spi *orion_spi; | |
399 | ||
400 | orion_spi = spi_master_get_devdata(spi->master); | |
401 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
402 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
403 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
404 | ||
405 | /* clear the interrupt cause register */ | |
406 | writel(0x0, int_reg); | |
407 | ||
408 | if (tx_buf && *tx_buf) | |
409 | writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); | |
410 | else | |
411 | writel(0, tx_reg); | |
412 | ||
413 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
414 | dev_err(&spi->dev, "TXS timed out\n"); | |
415 | return -1; | |
416 | } | |
417 | ||
418 | if (rx_buf && *rx_buf) | |
419 | put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); | |
420 | ||
421 | return 1; | |
422 | } | |
423 | ||
424 | static unsigned int | |
425 | orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) | |
426 | { | |
60cadec9 SA |
427 | unsigned int count; |
428 | int word_len; | |
b3c195b3 SR |
429 | struct orion_spi *orion_spi; |
430 | int cs = spi->chip_select; | |
c7ba4736 | 431 | void __iomem *vaddr; |
60cadec9 | 432 | |
60cadec9 SA |
433 | word_len = spi->bits_per_word; |
434 | count = xfer->len; | |
435 | ||
b3c195b3 SR |
436 | orion_spi = spi_master_get_devdata(spi->master); |
437 | ||
438 | /* | |
439 | * Use SPI direct write mode if base address is available. Otherwise | |
440 | * fall back to PIO mode for this transfer. | |
441 | */ | |
c7ba4736 KZ |
442 | vaddr = orion_spi->child[cs].direct_access.vaddr; |
443 | ||
444 | if (vaddr && xfer->tx_buf && word_len == 8) { | |
b3c195b3 SR |
445 | unsigned int cnt = count / 4; |
446 | unsigned int rem = count % 4; | |
447 | ||
448 | /* | |
449 | * Send the TX-data to the SPI device via the direct | |
450 | * mapped address window | |
451 | */ | |
c7ba4736 | 452 | iowrite32_rep(vaddr, xfer->tx_buf, cnt); |
b3c195b3 SR |
453 | if (rem) { |
454 | u32 *buf = (u32 *)xfer->tx_buf; | |
455 | ||
c7ba4736 | 456 | iowrite8_rep(vaddr, &buf[cnt], rem); |
b3c195b3 SR |
457 | } |
458 | ||
459 | return count; | |
460 | } | |
461 | ||
60cadec9 SA |
462 | if (word_len == 8) { |
463 | const u8 *tx = xfer->tx_buf; | |
464 | u8 *rx = xfer->rx_buf; | |
465 | ||
466 | do { | |
467 | if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) | |
468 | goto out; | |
469 | count--; | |
21e26062 | 470 | spi_delay_exec(&xfer->word_delay, xfer); |
60cadec9 SA |
471 | } while (count); |
472 | } else if (word_len == 16) { | |
473 | const u16 *tx = xfer->tx_buf; | |
474 | u16 *rx = xfer->rx_buf; | |
475 | ||
476 | do { | |
477 | if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) | |
478 | goto out; | |
479 | count -= 2; | |
21e26062 | 480 | spi_delay_exec(&xfer->word_delay, xfer); |
60cadec9 SA |
481 | } while (count); |
482 | } | |
483 | ||
484 | out: | |
485 | return xfer->len - count; | |
486 | } | |
487 | ||
75872ebe KW |
488 | static int orion_spi_transfer_one(struct spi_master *master, |
489 | struct spi_device *spi, | |
490 | struct spi_transfer *t) | |
60cadec9 | 491 | { |
ba59a807 | 492 | int status = 0; |
60cadec9 | 493 | |
75872ebe | 494 | status = orion_spi_setup_transfer(spi, t); |
ba59a807 | 495 | if (status < 0) |
75872ebe | 496 | return status; |
60cadec9 | 497 | |
75872ebe KW |
498 | if (t->len) |
499 | orion_spi_write_read(spi, t); | |
ba59a807 | 500 | |
75872ebe KW |
501 | return status; |
502 | } | |
ba59a807 | 503 | |
75872ebe KW |
504 | static int orion_spi_setup(struct spi_device *spi) |
505 | { | |
54424862 JK |
506 | if (gpio_is_valid(spi->cs_gpio)) { |
507 | gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
508 | } | |
75872ebe | 509 | return orion_spi_setup_transfer(spi, NULL); |
60cadec9 SA |
510 | } |
511 | ||
2deff8d6 | 512 | static int orion_spi_reset(struct orion_spi *orion_spi) |
60cadec9 SA |
513 | { |
514 | /* Verify that the CS is deasserted */ | |
75872ebe | 515 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
b3c195b3 SR |
516 | |
517 | /* Don't deassert CS between the direct mapped SPI transfers */ | |
518 | writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); | |
519 | ||
60cadec9 SA |
520 | return 0; |
521 | } | |
522 | ||
df59fa7f GU |
523 | static const struct orion_spi_dev orion_spi_dev_data = { |
524 | .typ = ORION_SPI, | |
525 | .min_divisor = 4, | |
526 | .max_divisor = 30, | |
527 | .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, | |
528 | }; | |
529 | ||
4dacccfa | 530 | static const struct orion_spi_dev armada_370_spi_dev_data = { |
df59fa7f | 531 | .typ = ARMADA_SPI, |
ce2f6ea1 | 532 | .min_divisor = 4, |
df59fa7f | 533 | .max_divisor = 1920, |
ce2f6ea1 | 534 | .max_hz = 50000000, |
df59fa7f GU |
535 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
536 | }; | |
537 | ||
4dacccfa GC |
538 | static const struct orion_spi_dev armada_xp_spi_dev_data = { |
539 | .typ = ARMADA_SPI, | |
540 | .max_hz = 50000000, | |
541 | .max_divisor = 1920, | |
542 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
543 | }; | |
544 | ||
545 | static const struct orion_spi_dev armada_375_spi_dev_data = { | |
546 | .typ = ARMADA_SPI, | |
547 | .min_divisor = 15, | |
548 | .max_divisor = 1920, | |
549 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
550 | }; | |
551 | ||
38d6211e NH |
552 | static const struct orion_spi_dev armada_380_spi_dev_data = { |
553 | .typ = ARMADA_SPI, | |
554 | .max_hz = 50000000, | |
555 | .max_divisor = 1920, | |
556 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
557 | .is_errata_50mhz_ac = true, | |
558 | }; | |
559 | ||
df59fa7f | 560 | static const struct of_device_id orion_spi_of_match_table[] = { |
4dacccfa GC |
561 | { |
562 | .compatible = "marvell,orion-spi", | |
563 | .data = &orion_spi_dev_data, | |
564 | }, | |
565 | { | |
566 | .compatible = "marvell,armada-370-spi", | |
567 | .data = &armada_370_spi_dev_data, | |
568 | }, | |
569 | { | |
570 | .compatible = "marvell,armada-375-spi", | |
571 | .data = &armada_375_spi_dev_data, | |
572 | }, | |
573 | { | |
574 | .compatible = "marvell,armada-380-spi", | |
38d6211e | 575 | .data = &armada_380_spi_dev_data, |
4dacccfa GC |
576 | }, |
577 | { | |
578 | .compatible = "marvell,armada-390-spi", | |
579 | .data = &armada_xp_spi_dev_data, | |
580 | }, | |
581 | { | |
582 | .compatible = "marvell,armada-xp-spi", | |
583 | .data = &armada_xp_spi_dev_data, | |
584 | }, | |
585 | ||
df59fa7f GU |
586 | {} |
587 | }; | |
588 | MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); | |
589 | ||
2deff8d6 | 590 | static int orion_spi_probe(struct platform_device *pdev) |
60cadec9 | 591 | { |
df59fa7f GU |
592 | const struct of_device_id *of_id; |
593 | const struct orion_spi_dev *devdata; | |
60cadec9 SA |
594 | struct spi_master *master; |
595 | struct orion_spi *spi; | |
596 | struct resource *r; | |
4574b886 | 597 | unsigned long tclk_hz; |
60cadec9 | 598 | int status = 0; |
b3c195b3 | 599 | struct device_node *np; |
60cadec9 | 600 | |
3fed8068 | 601 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); |
60cadec9 SA |
602 | if (master == NULL) { |
603 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
604 | return -ENOMEM; | |
605 | } | |
606 | ||
607 | if (pdev->id != -1) | |
608 | master->bus_num = pdev->id; | |
f814f9ac | 609 | if (pdev->dev.of_node) { |
e06871cd | 610 | u32 cell_index; |
b8434048 | 611 | |
e06871cd TP |
612 | if (!of_property_read_u32(pdev->dev.of_node, "cell-index", |
613 | &cell_index)) | |
614 | master->bus_num = cell_index; | |
f814f9ac | 615 | } |
60cadec9 | 616 | |
1017f424 BS |
617 | /* we support all 4 SPI modes and LSB first option */ |
618 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; | |
75872ebe KW |
619 | master->set_cs = orion_spi_set_cs; |
620 | master->transfer_one = orion_spi_transfer_one; | |
60cadec9 | 621 | master->num_chipselect = ORION_NUM_CHIPSELECTS; |
75872ebe | 622 | master->setup = orion_spi_setup; |
495b3358 | 623 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
5c678694 | 624 | master->auto_runtime_pm = true; |
b28b9149 | 625 | master->flags = SPI_MASTER_GPIO_SS; |
60cadec9 | 626 | |
24b5a82c | 627 | platform_set_drvdata(pdev, master); |
60cadec9 SA |
628 | |
629 | spi = spi_master_get_devdata(master); | |
630 | spi->master = master; | |
54424862 | 631 | spi->unused_hw_gpio = -1; |
60cadec9 | 632 | |
df59fa7f | 633 | of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); |
9a2d3635 | 634 | devdata = (of_id) ? of_id->data : &orion_spi_dev_data; |
df59fa7f GU |
635 | spi->devdata = devdata; |
636 | ||
bb489841 | 637 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
4574b886 AL |
638 | if (IS_ERR(spi->clk)) { |
639 | status = PTR_ERR(spi->clk); | |
640 | goto out; | |
641 | } | |
642 | ||
c85012ad RK |
643 | status = clk_prepare_enable(spi->clk); |
644 | if (status) | |
645 | goto out; | |
646 | ||
92ae112e GC |
647 | /* The following clock is only used by some SoCs */ |
648 | spi->axi_clk = devm_clk_get(&pdev->dev, "axi"); | |
45586c70 | 649 | if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) { |
479c03a7 CJ |
650 | status = -EPROBE_DEFER; |
651 | goto out_rel_clk; | |
652 | } | |
92ae112e GC |
653 | if (!IS_ERR(spi->axi_clk)) |
654 | clk_prepare_enable(spi->axi_clk); | |
655 | ||
4574b886 | 656 | tclk_hz = clk_get_rate(spi->clk); |
ce2f6ea1 GC |
657 | |
658 | /* | |
659 | * With old device tree, armada-370-spi could be used with | |
660 | * Armada XP, however for this SoC the maximum frequency is | |
661 | * 50MHz instead of tclk/4. On Armada 370, tclk cannot be | |
662 | * higher than 200MHz. So, in order to be able to handle both | |
663 | * SoCs, we can take the minimum of 50MHz and tclk/4. | |
664 | */ | |
665 | if (of_device_is_compatible(pdev->dev.of_node, | |
666 | "marvell,armada-370-spi")) | |
667 | master->max_speed_hz = min(devdata->max_hz, | |
668 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); | |
4dacccfa | 669 | else if (devdata->min_divisor) |
ce2f6ea1 GC |
670 | master->max_speed_hz = |
671 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor); | |
4dacccfa GC |
672 | else |
673 | master->max_speed_hz = devdata->max_hz; | |
df59fa7f | 674 | master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); |
60cadec9 SA |
675 | |
676 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1729ce34 MB |
677 | spi->base = devm_ioremap_resource(&pdev->dev, r); |
678 | if (IS_ERR(spi->base)) { | |
679 | status = PTR_ERR(spi->base); | |
479c03a7 | 680 | goto out_rel_axi_clk; |
60cadec9 SA |
681 | } |
682 | ||
b3c195b3 | 683 | for_each_available_child_of_node(pdev->dev.of_node, np) { |
c7ba4736 | 684 | struct orion_direct_acc *dir_acc; |
b3c195b3 | 685 | u32 cs; |
fb9acf5f | 686 | int cs_gpio; |
b3c195b3 SR |
687 | |
688 | /* Get chip-select number from the "reg" property */ | |
689 | status = of_property_read_u32(np, "reg", &cs); | |
690 | if (status) { | |
691 | dev_err(&pdev->dev, | |
25c56c88 RH |
692 | "%pOF has no valid 'reg' property (%d)\n", |
693 | np, status); | |
b3c195b3 SR |
694 | continue; |
695 | } | |
696 | ||
fb9acf5f JK |
697 | /* |
698 | * Initialize the CS GPIO: | |
699 | * - properly request the actual GPIO signal | |
700 | * - de-assert the logical signal so that all GPIO CS lines | |
701 | * are inactive when probing for slaves | |
702 | * - find an unused physical CS which will be driven for any | |
703 | * slave which uses a CS GPIO | |
704 | */ | |
705 | cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", cs); | |
706 | if (cs_gpio > 0) { | |
707 | char *gpio_name; | |
708 | int cs_flags; | |
709 | ||
710 | if (spi->unused_hw_gpio == -1) { | |
711 | dev_info(&pdev->dev, | |
712 | "Selected unused HW CS#%d for any GPIO CSes\n", | |
713 | cs); | |
714 | spi->unused_hw_gpio = cs; | |
715 | } | |
716 | ||
717 | gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, | |
718 | "%s-CS%d", dev_name(&pdev->dev), cs); | |
719 | if (!gpio_name) { | |
720 | status = -ENOMEM; | |
721 | goto out_rel_axi_clk; | |
722 | } | |
723 | ||
724 | cs_flags = of_property_read_bool(np, "spi-cs-high") ? | |
725 | GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH; | |
726 | status = devm_gpio_request_one(&pdev->dev, cs_gpio, | |
727 | cs_flags, gpio_name); | |
728 | if (status) { | |
729 | dev_err(&pdev->dev, | |
730 | "Can't request GPIO for CS %d\n", cs); | |
731 | goto out_rel_axi_clk; | |
732 | } | |
733 | } | |
734 | ||
b3c195b3 SR |
735 | /* |
736 | * Check if an address is configured for this SPI device. If | |
737 | * not, the MBus mapping via the 'ranges' property in the 'soc' | |
738 | * node is not configured and this device should not use the | |
739 | * direct mode. In this case, just continue with the next | |
740 | * device. | |
741 | */ | |
742 | status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); | |
743 | if (status) | |
744 | continue; | |
745 | ||
746 | /* | |
747 | * Only map one page for direct access. This is enough for the | |
748 | * simple TX transfer which only writes to the first word. | |
749 | * This needs to get extended for the direct SPI-NOR / SPI-NAND | |
750 | * support, once this gets implemented. | |
751 | */ | |
c7ba4736 KZ |
752 | dir_acc = &spi->child[cs].direct_access; |
753 | dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); | |
754 | if (!dir_acc->vaddr) { | |
57c624ae | 755 | status = -ENOMEM; |
479c03a7 | 756 | goto out_rel_axi_clk; |
b3c195b3 | 757 | } |
c7ba4736 | 758 | dir_acc->size = PAGE_SIZE; |
b3c195b3 SR |
759 | |
760 | dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); | |
761 | } | |
762 | ||
5c678694 RK |
763 | pm_runtime_set_active(&pdev->dev); |
764 | pm_runtime_use_autosuspend(&pdev->dev); | |
765 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
766 | pm_runtime_enable(&pdev->dev); | |
767 | ||
14033816 WY |
768 | status = orion_spi_reset(spi); |
769 | if (status < 0) | |
5c678694 RK |
770 | goto out_rel_pm; |
771 | ||
f814f9ac | 772 | master->dev.of_node = pdev->dev.of_node; |
5c678694 | 773 | status = spi_register_master(master); |
60cadec9 | 774 | if (status < 0) |
5c678694 | 775 | goto out_rel_pm; |
60cadec9 SA |
776 | |
777 | return status; | |
778 | ||
5c678694 RK |
779 | out_rel_pm: |
780 | pm_runtime_disable(&pdev->dev); | |
479c03a7 | 781 | out_rel_axi_clk: |
92ae112e | 782 | clk_disable_unprepare(spi->axi_clk); |
479c03a7 | 783 | out_rel_clk: |
4574b886 | 784 | clk_disable_unprepare(spi->clk); |
60cadec9 SA |
785 | out: |
786 | spi_master_put(master); | |
787 | return status; | |
788 | } | |
789 | ||
790 | ||
2deff8d6 | 791 | static int orion_spi_remove(struct platform_device *pdev) |
60cadec9 | 792 | { |
5c678694 RK |
793 | struct spi_master *master = platform_get_drvdata(pdev); |
794 | struct orion_spi *spi = spi_master_get_devdata(master); | |
60cadec9 | 795 | |
5c678694 | 796 | pm_runtime_get_sync(&pdev->dev); |
92ae112e | 797 | clk_disable_unprepare(spi->axi_clk); |
4574b886 | 798 | clk_disable_unprepare(spi->clk); |
4574b886 | 799 | |
5c678694 RK |
800 | spi_unregister_master(master); |
801 | pm_runtime_disable(&pdev->dev); | |
802 | ||
60cadec9 SA |
803 | return 0; |
804 | } | |
805 | ||
806 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
807 | ||
ec833050 | 808 | #ifdef CONFIG_PM |
5c678694 RK |
809 | static int orion_spi_runtime_suspend(struct device *dev) |
810 | { | |
811 | struct spi_master *master = dev_get_drvdata(dev); | |
812 | struct orion_spi *spi = spi_master_get_devdata(master); | |
813 | ||
92ae112e | 814 | clk_disable_unprepare(spi->axi_clk); |
5c678694 RK |
815 | clk_disable_unprepare(spi->clk); |
816 | return 0; | |
817 | } | |
818 | ||
819 | static int orion_spi_runtime_resume(struct device *dev) | |
820 | { | |
821 | struct spi_master *master = dev_get_drvdata(dev); | |
822 | struct orion_spi *spi = spi_master_get_devdata(master); | |
823 | ||
92ae112e GC |
824 | if (!IS_ERR(spi->axi_clk)) |
825 | clk_prepare_enable(spi->axi_clk); | |
5c678694 RK |
826 | return clk_prepare_enable(spi->clk); |
827 | } | |
828 | #endif | |
829 | ||
830 | static const struct dev_pm_ops orion_spi_pm_ops = { | |
831 | SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, | |
832 | orion_spi_runtime_resume, | |
833 | NULL) | |
834 | }; | |
835 | ||
60cadec9 SA |
836 | static struct platform_driver orion_spi_driver = { |
837 | .driver = { | |
838 | .name = DRIVER_NAME, | |
5c678694 | 839 | .pm = &orion_spi_pm_ops, |
f814f9ac | 840 | .of_match_table = of_match_ptr(orion_spi_of_match_table), |
60cadec9 | 841 | }, |
41ab724a | 842 | .probe = orion_spi_probe, |
2deff8d6 | 843 | .remove = orion_spi_remove, |
60cadec9 SA |
844 | }; |
845 | ||
41ab724a | 846 | module_platform_driver(orion_spi_driver); |
60cadec9 SA |
847 | |
848 | MODULE_DESCRIPTION("Orion SPI driver"); | |
849 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); | |
850 | MODULE_LICENSE("GPL"); |