Commit | Line | Data |
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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 | 25 | #include <linux/dmaengine.h> |
beca3655 | 26 | #include <linux/pinctrl/consumer.h> |
ccdc7bf9 SO |
27 | #include <linux/platform_device.h> |
28 | #include <linux/err.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
1f1a4384 | 32 | #include <linux/pm_runtime.h> |
d5a80031 BC |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
d33f473d | 35 | #include <linux/gcd.h> |
13d515c7 | 36 | #include <linux/iopoll.h> |
ccdc7bf9 SO |
37 | |
38 | #include <linux/spi/spi.h> | |
bc7f9bbc | 39 | #include <linux/gpio.h> |
ccdc7bf9 | 40 | |
2203747c | 41 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
42 | |
43 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 44 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
45 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
46 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 47 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
48 | |
49 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
54 | #define OMAP2_MCSPI_SYST 0x24 | |
55 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 56 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
57 | |
58 | /* per-channel banks, 0x14 bytes each, first is: */ | |
59 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
60 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
61 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
62 | #define OMAP2_MCSPI_TX0 0x38 | |
63 | #define OMAP2_MCSPI_RX0 0x3c | |
64 | ||
65 | /* per-register bitmasks: */ | |
d33f473d | 66 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 67 | |
7a8fa725 JH |
68 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
69 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
70 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 71 | |
7a8fa725 JH |
72 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
73 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 75 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 76 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
78 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
81 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
83 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
84 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
85 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
86 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
87 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
88 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 89 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 90 | |
7a8fa725 JH |
91 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
92 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
93 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 94 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 95 | |
7a8fa725 | 96 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 97 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 98 | |
7a8fa725 | 99 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
100 | |
101 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
102 | struct omap2_mcspi_dma { | |
53741ed8 RK |
103 | struct dma_chan *dma_tx; |
104 | struct dma_chan *dma_rx; | |
ccdc7bf9 | 105 | |
ccdc7bf9 SO |
106 | struct completion dma_tx_completion; |
107 | struct completion dma_rx_completion; | |
74f3aaad MP |
108 | |
109 | char dma_rx_ch_name[14]; | |
110 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
111 | }; |
112 | ||
113 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
114 | * cache operations; better heuristics consider wordsize and bitrate. | |
115 | */ | |
8b66c134 | 116 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
117 | |
118 | ||
1bd897f8 BC |
119 | /* |
120 | * Used for context save and restore, structure members to be updated whenever | |
121 | * corresponding registers are modified. | |
122 | */ | |
123 | struct omap2_mcspi_regs { | |
124 | u32 modulctrl; | |
125 | u32 wakeupenable; | |
126 | struct list_head cs; | |
127 | }; | |
128 | ||
ccdc7bf9 | 129 | struct omap2_mcspi { |
ccdc7bf9 | 130 | struct spi_master *master; |
ccdc7bf9 SO |
131 | /* Virtual base address of the controller */ |
132 | void __iomem *base; | |
e5480b73 | 133 | unsigned long phys; |
ccdc7bf9 SO |
134 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
135 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 136 | struct device *dev; |
1bd897f8 | 137 | struct omap2_mcspi_regs ctx; |
d33f473d | 138 | int fifo_depth; |
0384e90b | 139 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
140 | }; |
141 | ||
142 | struct omap2_mcspi_cs { | |
143 | void __iomem *base; | |
e5480b73 | 144 | unsigned long phys; |
ccdc7bf9 | 145 | int word_len; |
97ca0d6c | 146 | u16 mode; |
89c05372 | 147 | struct list_head node; |
a41ae1ad | 148 | /* Context save and restore shadow register */ |
faee9b05 | 149 | u32 chconf0, chctrl0; |
a41ae1ad H |
150 | }; |
151 | ||
ccdc7bf9 SO |
152 | static inline void mcspi_write_reg(struct spi_master *master, |
153 | int idx, u32 val) | |
154 | { | |
155 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
156 | ||
21b2ce5e | 157 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
158 | } |
159 | ||
160 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
161 | { | |
162 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
163 | ||
21b2ce5e | 164 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
165 | } |
166 | ||
167 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
168 | int idx, u32 val) | |
169 | { | |
170 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
171 | ||
21b2ce5e | 172 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
173 | } |
174 | ||
175 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
176 | { | |
177 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
178 | ||
21b2ce5e | 179 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
180 | } |
181 | ||
a41ae1ad H |
182 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
183 | { | |
184 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
185 | ||
186 | return cs->chconf0; | |
187 | } | |
188 | ||
189 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
190 | { | |
191 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
192 | ||
193 | cs->chconf0 = val; | |
194 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 195 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
196 | } |
197 | ||
56cd5c15 IS |
198 | static inline int mcspi_bytes_per_word(int word_len) |
199 | { | |
200 | if (word_len <= 8) | |
201 | return 1; | |
202 | else if (word_len <= 16) | |
203 | return 2; | |
204 | else /* word_len <= 32 */ | |
205 | return 4; | |
206 | } | |
207 | ||
ccdc7bf9 SO |
208 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
209 | int is_read, int enable) | |
210 | { | |
211 | u32 l, rw; | |
212 | ||
a41ae1ad | 213 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
214 | |
215 | if (is_read) /* 1 is read, 0 write */ | |
216 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
217 | else | |
218 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
219 | ||
af4e944d S |
220 | if (enable) |
221 | l |= rw; | |
222 | else | |
223 | l &= ~rw; | |
224 | ||
a41ae1ad | 225 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
226 | } |
227 | ||
228 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
229 | { | |
faee9b05 | 230 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
231 | u32 l; |
232 | ||
faee9b05 SS |
233 | l = cs->chctrl0; |
234 | if (enable) | |
235 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
236 | else | |
237 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
238 | cs->chctrl0 = l; | |
239 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
240 | /* Flash post-writes */ |
241 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
242 | } |
243 | ||
ddcad7e9 | 244 | static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) |
ccdc7bf9 | 245 | { |
5f74db10 | 246 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
ccdc7bf9 SO |
247 | u32 l; |
248 | ||
4373f8b6 MW |
249 | /* The controller handles the inverted chip selects |
250 | * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert | |
251 | * the inversion from the core spi_set_cs function. | |
252 | */ | |
253 | if (spi->mode & SPI_CS_HIGH) | |
254 | enable = !enable; | |
255 | ||
ddcad7e9 | 256 | if (spi->controller_state) { |
5f74db10 SR |
257 | int err = pm_runtime_get_sync(mcspi->dev); |
258 | if (err < 0) { | |
5a686b2c | 259 | pm_runtime_put_noidle(mcspi->dev); |
5f74db10 SR |
260 | dev_err(mcspi->dev, "failed to get sync: %d\n", err); |
261 | return; | |
262 | } | |
263 | ||
ddcad7e9 | 264 | l = mcspi_cached_chconf0(spi); |
af4e944d | 265 | |
ddcad7e9 MW |
266 | if (enable) |
267 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
268 | else | |
269 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
270 | ||
271 | mcspi_write_chconf0(spi, l); | |
5f74db10 SR |
272 | |
273 | pm_runtime_mark_last_busy(mcspi->dev); | |
274 | pm_runtime_put_autosuspend(mcspi->dev); | |
ddcad7e9 | 275 | } |
ccdc7bf9 SO |
276 | } |
277 | ||
278 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
279 | { | |
1bd897f8 BC |
280 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
281 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
282 | u32 l; |
283 | ||
1bd897f8 BC |
284 | /* |
285 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
286 | * to single-channel master mode |
287 | */ | |
288 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
289 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
290 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 291 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 292 | |
1bd897f8 | 293 | ctx->modulctrl = l; |
a41ae1ad H |
294 | } |
295 | ||
d33f473d IS |
296 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
297 | struct spi_transfer *t, int enable) | |
298 | { | |
299 | struct spi_master *master = spi->master; | |
300 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
301 | struct omap2_mcspi *mcspi; | |
302 | unsigned int wcnt; | |
b682cffa | 303 | int max_fifo_depth, bytes_per_word; |
d33f473d IS |
304 | u32 chconf, xferlevel; |
305 | ||
306 | mcspi = spi_master_get_devdata(master); | |
307 | ||
308 | chconf = mcspi_cached_chconf0(spi); | |
309 | if (enable) { | |
310 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
311 | if (t->len % bytes_per_word != 0) | |
312 | goto disable_fifo; | |
313 | ||
5db542ed IS |
314 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
315 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
316 | else | |
317 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
318 | ||
d33f473d IS |
319 | wcnt = t->len / bytes_per_word; |
320 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
321 | goto disable_fifo; | |
322 | ||
323 | xferlevel = wcnt << 16; | |
324 | if (t->rx_buf != NULL) { | |
325 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
b682cffa | 326 | xferlevel |= (bytes_per_word - 1) << 8; |
5db542ed | 327 | } |
b682cffa | 328 | |
5db542ed | 329 | if (t->tx_buf != NULL) { |
d33f473d | 330 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
b682cffa | 331 | xferlevel |= bytes_per_word - 1; |
d33f473d IS |
332 | } |
333 | ||
334 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
335 | mcspi_write_chconf0(spi, chconf); | |
b682cffa | 336 | mcspi->fifo_depth = max_fifo_depth; |
d33f473d IS |
337 | |
338 | return; | |
339 | } | |
340 | ||
341 | disable_fifo: | |
342 | if (t->rx_buf != NULL) | |
343 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
344 | |
345 | if (t->tx_buf != NULL) | |
d33f473d IS |
346 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
347 | ||
348 | mcspi_write_chconf0(spi, chconf); | |
349 | mcspi->fifo_depth = 0; | |
350 | } | |
351 | ||
2764c500 IK |
352 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
353 | { | |
13d515c7 V |
354 | u32 val; |
355 | ||
356 | return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC); | |
2764c500 IK |
357 | } |
358 | ||
53741ed8 RK |
359 | static void omap2_mcspi_rx_callback(void *data) |
360 | { | |
361 | struct spi_device *spi = data; | |
362 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
363 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
364 | ||
53741ed8 RK |
365 | /* We must disable the DMA RX request */ |
366 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
367 | |
368 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
369 | } |
370 | ||
371 | static void omap2_mcspi_tx_callback(void *data) | |
372 | { | |
373 | struct spi_device *spi = data; | |
374 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
375 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
376 | ||
53741ed8 RK |
377 | /* We must disable the DMA TX request */ |
378 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
379 | |
380 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
381 | } |
382 | ||
d7b4394e S |
383 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
384 | struct spi_transfer *xfer, | |
385 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
386 | { |
387 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 388 | struct omap2_mcspi_dma *mcspi_dma; |
ccdc7bf9 SO |
389 | |
390 | mcspi = spi_master_get_devdata(spi->master); | |
391 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
392 | ||
d7b4394e | 393 | if (mcspi_dma->dma_tx) { |
53741ed8 | 394 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
395 | |
396 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
397 | ||
0ba1870f FCJ |
398 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, |
399 | xfer->tx_sg.nents, | |
400 | DMA_MEM_TO_DEV, | |
401 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
402 | if (tx) { |
403 | tx->callback = omap2_mcspi_tx_callback; | |
404 | tx->callback_param = spi; | |
405 | dmaengine_submit(tx); | |
406 | } else { | |
407 | /* FIXME: fall back to PIO? */ | |
408 | } | |
409 | } | |
d7b4394e S |
410 | dma_async_issue_pending(mcspi_dma->dma_tx); |
411 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
412 | ||
d7b4394e | 413 | } |
53741ed8 | 414 | |
d7b4394e S |
415 | static unsigned |
416 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
417 | struct dma_slave_config cfg, | |
418 | unsigned es) | |
419 | { | |
420 | struct omap2_mcspi *mcspi; | |
421 | struct omap2_mcspi_dma *mcspi_dma; | |
0ba1870f FCJ |
422 | unsigned int count, transfer_reduction = 0; |
423 | struct scatterlist *sg_out[2]; | |
424 | int nb_sizes = 0, out_mapped_nents[2], ret, x; | |
425 | size_t sizes[2]; | |
d7b4394e S |
426 | u32 l; |
427 | int elements = 0; | |
428 | int word_len, element_count; | |
429 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
81261359 AM |
430 | void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
431 | ||
d7b4394e S |
432 | mcspi = spi_master_get_devdata(spi->master); |
433 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
434 | count = xfer->len; | |
d33f473d | 435 | |
4bd00413 FCJ |
436 | /* |
437 | * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM | |
438 | * it mentions reducing DMA transfer length by one element in master | |
439 | * normal mode. | |
440 | */ | |
d33f473d | 441 | if (mcspi->fifo_depth == 0) |
0ba1870f | 442 | transfer_reduction = es; |
d33f473d | 443 | |
d7b4394e S |
444 | word_len = cs->word_len; |
445 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 446 | |
d7b4394e S |
447 | if (word_len <= 8) |
448 | element_count = count; | |
449 | else if (word_len <= 16) | |
450 | element_count = count >> 1; | |
451 | else /* word_len <= 32 */ | |
452 | element_count = count >> 2; | |
453 | ||
454 | if (mcspi_dma->dma_rx) { | |
53741ed8 | 455 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
456 | |
457 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
458 | ||
4bd00413 FCJ |
459 | /* |
460 | * Reduce DMA transfer length by one more if McSPI is | |
461 | * configured in turbo mode. | |
462 | */ | |
d33f473d | 463 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
0ba1870f FCJ |
464 | transfer_reduction += es; |
465 | ||
466 | if (transfer_reduction) { | |
467 | /* Split sgl into two. The second sgl won't be used. */ | |
468 | sizes[0] = count - transfer_reduction; | |
469 | sizes[1] = transfer_reduction; | |
470 | nb_sizes = 2; | |
471 | } else { | |
472 | /* | |
473 | * Don't bother splitting the sgl. This essentially | |
474 | * clones the original sgl. | |
475 | */ | |
476 | sizes[0] = count; | |
477 | nb_sizes = 1; | |
478 | } | |
479 | ||
480 | ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, | |
481 | 0, nb_sizes, | |
482 | sizes, | |
483 | sg_out, out_mapped_nents, | |
484 | GFP_KERNEL); | |
53741ed8 | 485 | |
0ba1870f FCJ |
486 | if (ret < 0) { |
487 | dev_err(&spi->dev, "sg_split failed\n"); | |
488 | return 0; | |
489 | } | |
53741ed8 | 490 | |
0ba1870f FCJ |
491 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, |
492 | sg_out[0], | |
493 | out_mapped_nents[0], | |
494 | DMA_DEV_TO_MEM, | |
495 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
496 | if (tx) { |
497 | tx->callback = omap2_mcspi_rx_callback; | |
498 | tx->callback_param = spi; | |
499 | dmaengine_submit(tx); | |
500 | } else { | |
d7b4394e | 501 | /* FIXME: fall back to PIO? */ |
2764c500 | 502 | } |
ccdc7bf9 SO |
503 | } |
504 | ||
d7b4394e S |
505 | dma_async_issue_pending(mcspi_dma->dma_rx); |
506 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 507 | |
d7b4394e | 508 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
0ba1870f FCJ |
509 | |
510 | for (x = 0; x < nb_sizes; x++) | |
511 | kfree(sg_out[x]); | |
d33f473d IS |
512 | |
513 | if (mcspi->fifo_depth > 0) | |
514 | return count; | |
515 | ||
4bd00413 FCJ |
516 | /* |
517 | * Due to the DMA transfer length reduction the missing bytes must | |
518 | * be read manually to receive all of the expected data. | |
519 | */ | |
d7b4394e | 520 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 521 | |
d7b4394e | 522 | elements = element_count - 1; |
4743a0f8 | 523 | |
d7b4394e S |
524 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
525 | elements--; | |
4743a0f8 | 526 | |
81261359 AM |
527 | if (!mcspi_wait_for_reg_bit(chstat_reg, |
528 | OMAP2_MCSPI_CHSTAT_RXS)) { | |
57c5c28d EN |
529 | u32 w; |
530 | ||
531 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
532 | if (word_len <= 8) | |
d7b4394e | 533 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 534 | else if (word_len <= 16) |
d7b4394e | 535 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 536 | else /* word_len <= 32 */ |
d7b4394e | 537 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 538 | } else { |
56cd5c15 | 539 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 540 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 541 | count -= (bytes_per_word << 1); |
d7b4394e S |
542 | omap2_mcspi_set_enable(spi, 1); |
543 | return count; | |
57c5c28d | 544 | } |
ccdc7bf9 | 545 | } |
81261359 | 546 | if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) { |
d7b4394e S |
547 | u32 w; |
548 | ||
549 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
550 | if (word_len <= 8) | |
551 | ((u8 *)xfer->rx_buf)[elements] = w; | |
552 | else if (word_len <= 16) | |
553 | ((u16 *)xfer->rx_buf)[elements] = w; | |
554 | else /* word_len <= 32 */ | |
555 | ((u32 *)xfer->rx_buf)[elements] = w; | |
556 | } else { | |
a1829d2b | 557 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 558 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
559 | } |
560 | omap2_mcspi_set_enable(spi, 1); | |
561 | return count; | |
562 | } | |
563 | ||
564 | static unsigned | |
565 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
566 | { | |
567 | struct omap2_mcspi *mcspi; | |
568 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
569 | struct omap2_mcspi_dma *mcspi_dma; | |
570 | unsigned int count; | |
d7b4394e S |
571 | u8 *rx; |
572 | const u8 *tx; | |
573 | struct dma_slave_config cfg; | |
574 | enum dma_slave_buswidth width; | |
575 | unsigned es; | |
e47a682a | 576 | void __iomem *chstat_reg; |
d33f473d IS |
577 | void __iomem *irqstat_reg; |
578 | int wait_res; | |
d7b4394e S |
579 | |
580 | mcspi = spi_master_get_devdata(spi->master); | |
581 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e S |
582 | |
583 | if (cs->word_len <= 8) { | |
584 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
585 | es = 1; | |
586 | } else if (cs->word_len <= 16) { | |
587 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
588 | es = 2; | |
589 | } else { | |
590 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
591 | es = 4; | |
592 | } | |
593 | ||
d33f473d | 594 | count = xfer->len; |
d33f473d | 595 | |
d7b4394e S |
596 | memset(&cfg, 0, sizeof(cfg)); |
597 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
598 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
599 | cfg.src_addr_width = width; | |
600 | cfg.dst_addr_width = width; | |
b682cffa V |
601 | cfg.src_maxburst = es; |
602 | cfg.dst_maxburst = es; | |
d7b4394e S |
603 | |
604 | rx = xfer->rx_buf; | |
605 | tx = xfer->tx_buf; | |
606 | ||
d7b4394e S |
607 | if (tx != NULL) |
608 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
609 | ||
610 | if (rx != NULL) | |
e47a682a S |
611 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
612 | ||
613 | if (tx != NULL) { | |
e47a682a | 614 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
e47a682a | 615 | |
d33f473d IS |
616 | if (mcspi->fifo_depth > 0) { |
617 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
618 | ||
619 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
620 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
621 | dev_err(&spi->dev, "EOW timed out\n"); | |
622 | ||
623 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
624 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
625 | } | |
626 | ||
e47a682a S |
627 | /* for TX_ONLY mode, be sure all words have shifted out */ |
628 | if (rx == NULL) { | |
d33f473d IS |
629 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
630 | if (mcspi->fifo_depth > 0) { | |
631 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
632 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
633 | if (wait_res < 0) | |
634 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
635 | } else { | |
636 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
637 | OMAP2_MCSPI_CHSTAT_TXS); | |
638 | if (wait_res < 0) | |
639 | dev_err(&spi->dev, "TXS timed out\n"); | |
640 | } | |
641 | if (wait_res >= 0 && | |
642 | (mcspi_wait_for_reg_bit(chstat_reg, | |
643 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
644 | dev_err(&spi->dev, "EOT timed out\n"); |
645 | } | |
646 | } | |
ccdc7bf9 SO |
647 | return count; |
648 | } | |
649 | ||
ccdc7bf9 SO |
650 | static unsigned |
651 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
652 | { | |
ccdc7bf9 SO |
653 | struct omap2_mcspi_cs *cs = spi->controller_state; |
654 | unsigned int count, c; | |
655 | u32 l; | |
656 | void __iomem *base = cs->base; | |
657 | void __iomem *tx_reg; | |
658 | void __iomem *rx_reg; | |
659 | void __iomem *chstat_reg; | |
660 | int word_len; | |
661 | ||
ccdc7bf9 SO |
662 | count = xfer->len; |
663 | c = count; | |
664 | word_len = cs->word_len; | |
665 | ||
a41ae1ad | 666 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
667 | |
668 | /* We store the pre-calculated register addresses on stack to speed | |
669 | * up the transfer loop. */ | |
670 | tx_reg = base + OMAP2_MCSPI_TX0; | |
671 | rx_reg = base + OMAP2_MCSPI_RX0; | |
672 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
673 | ||
adef658d MJ |
674 | if (c < (word_len>>3)) |
675 | return 0; | |
676 | ||
ccdc7bf9 SO |
677 | if (word_len <= 8) { |
678 | u8 *rx; | |
679 | const u8 *tx; | |
680 | ||
681 | rx = xfer->rx_buf; | |
682 | tx = xfer->tx_buf; | |
683 | ||
684 | do { | |
feed9bab | 685 | c -= 1; |
ccdc7bf9 SO |
686 | if (tx != NULL) { |
687 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
688 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
689 | dev_err(&spi->dev, "TXS timed out\n"); | |
690 | goto out; | |
691 | } | |
079a176d | 692 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 693 | word_len, *tx); |
21b2ce5e | 694 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
695 | } |
696 | if (rx != NULL) { | |
697 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
698 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
699 | dev_err(&spi->dev, "RXS timed out\n"); | |
700 | goto out; | |
701 | } | |
4743a0f8 RT |
702 | |
703 | if (c == 1 && tx == NULL && | |
704 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
705 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 706 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 707 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 708 | word_len, *(rx - 1)); |
4743a0f8 RT |
709 | if (mcspi_wait_for_reg_bit(chstat_reg, |
710 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
711 | dev_err(&spi->dev, | |
712 | "RXS timed out\n"); | |
713 | goto out; | |
714 | } | |
715 | c = 0; | |
716 | } else if (c == 0 && tx == NULL) { | |
717 | omap2_mcspi_set_enable(spi, 0); | |
718 | } | |
719 | ||
21b2ce5e | 720 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 721 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 722 | word_len, *(rx - 1)); |
ccdc7bf9 | 723 | } |
95c5c3ab | 724 | } while (c); |
ccdc7bf9 SO |
725 | } else if (word_len <= 16) { |
726 | u16 *rx; | |
727 | const u16 *tx; | |
728 | ||
729 | rx = xfer->rx_buf; | |
730 | tx = xfer->tx_buf; | |
731 | do { | |
feed9bab | 732 | c -= 2; |
ccdc7bf9 SO |
733 | if (tx != NULL) { |
734 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
735 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
736 | dev_err(&spi->dev, "TXS timed out\n"); | |
737 | goto out; | |
738 | } | |
079a176d | 739 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 740 | word_len, *tx); |
21b2ce5e | 741 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
742 | } |
743 | if (rx != NULL) { | |
744 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
745 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
746 | dev_err(&spi->dev, "RXS timed out\n"); | |
747 | goto out; | |
748 | } | |
4743a0f8 RT |
749 | |
750 | if (c == 2 && tx == NULL && | |
751 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
752 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 753 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 754 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 755 | word_len, *(rx - 1)); |
4743a0f8 RT |
756 | if (mcspi_wait_for_reg_bit(chstat_reg, |
757 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
758 | dev_err(&spi->dev, | |
759 | "RXS timed out\n"); | |
760 | goto out; | |
761 | } | |
762 | c = 0; | |
763 | } else if (c == 0 && tx == NULL) { | |
764 | omap2_mcspi_set_enable(spi, 0); | |
765 | } | |
766 | ||
21b2ce5e | 767 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 768 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 769 | word_len, *(rx - 1)); |
ccdc7bf9 | 770 | } |
95c5c3ab | 771 | } while (c >= 2); |
ccdc7bf9 SO |
772 | } else if (word_len <= 32) { |
773 | u32 *rx; | |
774 | const u32 *tx; | |
775 | ||
776 | rx = xfer->rx_buf; | |
777 | tx = xfer->tx_buf; | |
778 | do { | |
feed9bab | 779 | c -= 4; |
ccdc7bf9 SO |
780 | if (tx != NULL) { |
781 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
782 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
783 | dev_err(&spi->dev, "TXS timed out\n"); | |
784 | goto out; | |
785 | } | |
079a176d | 786 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 787 | word_len, *tx); |
21b2ce5e | 788 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
789 | } |
790 | if (rx != NULL) { | |
791 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
792 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
793 | dev_err(&spi->dev, "RXS timed out\n"); | |
794 | goto out; | |
795 | } | |
4743a0f8 RT |
796 | |
797 | if (c == 4 && tx == NULL && | |
798 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
799 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 800 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 801 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 802 | word_len, *(rx - 1)); |
4743a0f8 RT |
803 | if (mcspi_wait_for_reg_bit(chstat_reg, |
804 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
805 | dev_err(&spi->dev, | |
806 | "RXS timed out\n"); | |
807 | goto out; | |
808 | } | |
809 | c = 0; | |
810 | } else if (c == 0 && tx == NULL) { | |
811 | omap2_mcspi_set_enable(spi, 0); | |
812 | } | |
813 | ||
21b2ce5e | 814 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 815 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 816 | word_len, *(rx - 1)); |
ccdc7bf9 | 817 | } |
95c5c3ab | 818 | } while (c >= 4); |
ccdc7bf9 SO |
819 | } |
820 | ||
821 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
822 | if (xfer->rx_buf == NULL) { | |
823 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
824 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
825 | dev_err(&spi->dev, "TXS timed out\n"); | |
826 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
827 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
828 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
829 | |
830 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
831 | * otherwise these rx datas will affect the direct following | |
832 | * RX_ONLY transfer. | |
833 | */ | |
834 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
835 | } |
836 | out: | |
4743a0f8 | 837 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
838 | return count - c; |
839 | } | |
840 | ||
57d9c10d HH |
841 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
842 | { | |
843 | u32 div; | |
844 | ||
845 | for (div = 0; div < 15; div++) | |
846 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
847 | return div; | |
848 | ||
849 | return 15; | |
850 | } | |
851 | ||
ccdc7bf9 SO |
852 | /* called only when no transfer is active to this device */ |
853 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
854 | struct spi_transfer *t) | |
855 | { | |
856 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
857 | struct omap2_mcspi *mcspi; | |
faee9b05 | 858 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 859 | u8 word_len = spi->bits_per_word; |
9bd4517d | 860 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
861 | |
862 | mcspi = spi_master_get_devdata(spi->master); | |
863 | ||
864 | if (t != NULL && t->bits_per_word) | |
865 | word_len = t->bits_per_word; | |
866 | ||
867 | cs->word_len = word_len; | |
868 | ||
9bd4517d SE |
869 | if (t && t->speed_hz) |
870 | speed_hz = t->speed_hz; | |
871 | ||
57d9c10d | 872 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
873 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
874 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
875 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
876 | clkg = 0; | |
877 | } else { | |
878 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
879 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
880 | clkd = (div - 1) & 0xf; | |
881 | extclk = (div - 1) >> 4; | |
882 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
883 | } | |
ccdc7bf9 | 884 | |
a41ae1ad | 885 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
886 | |
887 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
888 | * REVISIT: this controller could support SPI_3WIRE mode. | |
889 | */ | |
2cd45179 | 890 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
891 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
892 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
893 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
894 | } else { | |
895 | l |= OMAP2_MCSPI_CHCONF_IS; | |
896 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
897 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
898 | } | |
ccdc7bf9 SO |
899 | |
900 | /* wordlength */ | |
901 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
902 | l |= (word_len - 1) << 7; | |
903 | ||
904 | /* set chipselect polarity; manage with FORCE */ | |
905 | if (!(spi->mode & SPI_CS_HIGH)) | |
906 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
907 | else | |
908 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
909 | ||
910 | /* set clock divisor */ | |
911 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
912 | l |= clkd << 2; |
913 | ||
914 | /* set clock granularity */ | |
915 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
916 | l |= clkg; | |
917 | if (clkg) { | |
918 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
919 | cs->chctrl0 |= extclk << 8; | |
920 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
921 | } | |
ccdc7bf9 SO |
922 | |
923 | /* set SPI mode 0..3 */ | |
924 | if (spi->mode & SPI_CPOL) | |
925 | l |= OMAP2_MCSPI_CHCONF_POL; | |
926 | else | |
927 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
928 | if (spi->mode & SPI_CPHA) | |
929 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
930 | else | |
931 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
932 | ||
a41ae1ad | 933 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 934 | |
97ca0d6c MG |
935 | cs->mode = spi->mode; |
936 | ||
ccdc7bf9 | 937 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 938 | speed_hz, |
ccdc7bf9 SO |
939 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
940 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
ddc5cdf1 TL |
945 | /* |
946 | * Note that we currently allow DMA only if we get a channel | |
947 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
948 | */ | |
ccdc7bf9 SO |
949 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
950 | { | |
951 | struct spi_master *master = spi->master; | |
952 | struct omap2_mcspi *mcspi; | |
953 | struct omap2_mcspi_dma *mcspi_dma; | |
b085c612 | 954 | int ret = 0; |
ccdc7bf9 SO |
955 | |
956 | mcspi = spi_master_get_devdata(master); | |
957 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
958 | ||
53741ed8 RK |
959 | init_completion(&mcspi_dma->dma_rx_completion); |
960 | init_completion(&mcspi_dma->dma_tx_completion); | |
961 | ||
b085c612 PU |
962 | mcspi_dma->dma_rx = dma_request_chan(&master->dev, |
963 | mcspi_dma->dma_rx_ch_name); | |
964 | if (IS_ERR(mcspi_dma->dma_rx)) { | |
965 | ret = PTR_ERR(mcspi_dma->dma_rx); | |
966 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 967 | goto no_dma; |
b085c612 | 968 | } |
ccdc7bf9 | 969 | |
b085c612 PU |
970 | mcspi_dma->dma_tx = dma_request_chan(&master->dev, |
971 | mcspi_dma->dma_tx_ch_name); | |
972 | if (IS_ERR(mcspi_dma->dma_tx)) { | |
973 | ret = PTR_ERR(mcspi_dma->dma_tx); | |
974 | mcspi_dma->dma_tx = NULL; | |
53741ed8 RK |
975 | dma_release_channel(mcspi_dma->dma_rx); |
976 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
977 | } |
978 | ||
ddc5cdf1 | 979 | no_dma: |
b085c612 | 980 | return ret; |
ccdc7bf9 SO |
981 | } |
982 | ||
ccdc7bf9 SO |
983 | static int omap2_mcspi_setup(struct spi_device *spi) |
984 | { | |
985 | int ret; | |
1bd897f8 BC |
986 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
987 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
988 | struct omap2_mcspi_dma *mcspi_dma; |
989 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
990 | ||
ccdc7bf9 SO |
991 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
992 | ||
993 | if (!cs) { | |
10aa5a35 | 994 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
995 | if (!cs) |
996 | return -ENOMEM; | |
997 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 998 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 999 | cs->mode = 0; |
a41ae1ad | 1000 | cs->chconf0 = 0; |
faee9b05 | 1001 | cs->chctrl0 = 0; |
ccdc7bf9 | 1002 | spi->controller_state = cs; |
89c05372 | 1003 | /* Link this to context save list */ |
1bd897f8 | 1004 | list_add_tail(&cs->node, &ctx->cs); |
2f538c01 MW |
1005 | |
1006 | if (gpio_is_valid(spi->cs_gpio)) { | |
1007 | ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); | |
1008 | if (ret) { | |
1009 | dev_err(&spi->dev, "failed to request gpio\n"); | |
1010 | return ret; | |
1011 | } | |
1012 | gpio_direction_output(spi->cs_gpio, | |
1013 | !(spi->mode & SPI_CS_HIGH)); | |
1014 | } | |
ccdc7bf9 SO |
1015 | } |
1016 | ||
8c7494a5 | 1017 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1018 | ret = omap2_mcspi_request_dma(spi); |
b085c612 PU |
1019 | if (ret) |
1020 | dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", | |
1021 | ret); | |
ccdc7bf9 SO |
1022 | } |
1023 | ||
034d3dc9 | 1024 | ret = pm_runtime_get_sync(mcspi->dev); |
5a686b2c TL |
1025 | if (ret < 0) { |
1026 | pm_runtime_put_noidle(mcspi->dev); | |
1027 | ||
1f1a4384 | 1028 | return ret; |
5a686b2c | 1029 | } |
a41ae1ad | 1030 | |
86eeb6fe | 1031 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1032 | pm_runtime_mark_last_busy(mcspi->dev); |
1033 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1034 | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1039 | { | |
1040 | struct omap2_mcspi *mcspi; | |
1041 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1042 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1043 | |
1044 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1045 | |
5e774943 SE |
1046 | if (spi->controller_state) { |
1047 | /* Unlink controller state from context save list */ | |
1048 | cs = spi->controller_state; | |
1049 | list_del(&cs->node); | |
89c05372 | 1050 | |
10aa5a35 | 1051 | kfree(cs); |
5e774943 | 1052 | } |
ccdc7bf9 | 1053 | |
99f1a43f SE |
1054 | if (spi->chip_select < spi->master->num_chipselect) { |
1055 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1056 | ||
53741ed8 RK |
1057 | if (mcspi_dma->dma_rx) { |
1058 | dma_release_channel(mcspi_dma->dma_rx); | |
1059 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1060 | } |
53741ed8 RK |
1061 | if (mcspi_dma->dma_tx) { |
1062 | dma_release_channel(mcspi_dma->dma_tx); | |
1063 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1064 | } |
ccdc7bf9 | 1065 | } |
bc7f9bbc MW |
1066 | |
1067 | if (gpio_is_valid(spi->cs_gpio)) | |
1068 | gpio_free(spi->cs_gpio); | |
ccdc7bf9 SO |
1069 | } |
1070 | ||
0ba1870f FCJ |
1071 | static int omap2_mcspi_transfer_one(struct spi_master *master, |
1072 | struct spi_device *spi, | |
1073 | struct spi_transfer *t) | |
ccdc7bf9 | 1074 | { |
ccdc7bf9 SO |
1075 | |
1076 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1077 | * -- although this controller would gladly |
ccdc7bf9 SO |
1078 | * arbitrate among multiple channels. This corresponds to "single |
1079 | * channel" master mode. As a side effect, we need to manage the | |
1080 | * chipselect with the FORCE bit ... CS != channel enable. | |
1081 | */ | |
ccdc7bf9 | 1082 | |
0ba1870f | 1083 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1084 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1085 | struct omap2_mcspi_cs *cs; |
1086 | struct omap2_mcspi_device_config *cd; | |
1087 | int par_override = 0; | |
1088 | int status = 0; | |
1089 | u32 chconf; | |
ccdc7bf9 | 1090 | |
0ba1870f | 1091 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1092 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1093 | cs = spi->controller_state; |
1094 | cd = spi->controller_data; | |
ccdc7bf9 | 1095 | |
97ca0d6c MG |
1096 | /* |
1097 | * The slave driver could have changed spi->mode in which case | |
1098 | * it will be different from cs->mode (the current hardware setup). | |
1099 | * If so, set par_override (even though its not a parity issue) so | |
1100 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1101 | * with the correct mode on the first iteration of the loop below. | |
1102 | */ | |
1103 | if (spi->mode != cs->mode) | |
1104 | par_override = 1; | |
1105 | ||
d33f473d | 1106 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 1107 | |
a06b430f MW |
1108 | if (gpio_is_valid(spi->cs_gpio)) |
1109 | omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); | |
1110 | ||
b28cb941 MW |
1111 | if (par_override || |
1112 | (t->speed_hz != spi->max_speed_hz) || | |
1113 | (t->bits_per_word != spi->bits_per_word)) { | |
1114 | par_override = 1; | |
1115 | status = omap2_mcspi_setup_transfer(spi, t); | |
1116 | if (status < 0) | |
1117 | goto out; | |
1118 | if (t->speed_hz == spi->max_speed_hz && | |
1119 | t->bits_per_word == spi->bits_per_word) | |
1120 | par_override = 0; | |
1121 | } | |
1122 | if (cd && cd->cs_per_word) { | |
1123 | chconf = mcspi->ctx.modulctrl; | |
1124 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1125 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1126 | mcspi->ctx.modulctrl = | |
1127 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1128 | } | |
4743a0f8 | 1129 | |
b28cb941 MW |
1130 | chconf = mcspi_cached_chconf0(spi); |
1131 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1132 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
1133 | ||
1134 | if (t->tx_buf == NULL) | |
1135 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1136 | else if (t->rx_buf == NULL) | |
1137 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
1138 | ||
1139 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
1140 | /* Turbo mode is for more than one word */ | |
1141 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1142 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1143 | } | |
ccdc7bf9 | 1144 | |
b28cb941 | 1145 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1146 | |
b28cb941 MW |
1147 | if (t->len) { |
1148 | unsigned count; | |
5fda88f5 | 1149 | |
b28cb941 | 1150 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
0ba1870f FCJ |
1151 | master->cur_msg_mapped && |
1152 | master->can_dma(master, spi, t)) | |
b28cb941 | 1153 | omap2_mcspi_set_fifo(spi, t, 1); |
d33f473d | 1154 | |
b28cb941 | 1155 | omap2_mcspi_set_enable(spi, 1); |
d33f473d | 1156 | |
b28cb941 MW |
1157 | /* RX_ONLY mode needs dummy data in TX reg */ |
1158 | if (t->tx_buf == NULL) | |
1159 | writel_relaxed(0, cs->base | |
1160 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1161 | |
b28cb941 | 1162 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
0ba1870f FCJ |
1163 | master->cur_msg_mapped && |
1164 | master->can_dma(master, spi, t)) | |
b28cb941 MW |
1165 | count = omap2_mcspi_txrx_dma(spi, t); |
1166 | else | |
1167 | count = omap2_mcspi_txrx_pio(spi, t); | |
ccdc7bf9 | 1168 | |
b28cb941 MW |
1169 | if (count != t->len) { |
1170 | status = -EIO; | |
1171 | goto out; | |
ccdc7bf9 | 1172 | } |
b28cb941 | 1173 | } |
ccdc7bf9 | 1174 | |
b28cb941 | 1175 | omap2_mcspi_set_enable(spi, 0); |
d33f473d | 1176 | |
b28cb941 MW |
1177 | if (mcspi->fifo_depth > 0) |
1178 | omap2_mcspi_set_fifo(spi, t, 0); | |
1179 | ||
1180 | out: | |
5fda88f5 S |
1181 | /* Restore defaults if they were overriden */ |
1182 | if (par_override) { | |
1183 | par_override = 0; | |
1184 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1185 | } | |
ccdc7bf9 | 1186 | |
5cbc7ca9 MB |
1187 | if (cd && cd->cs_per_word) { |
1188 | chconf = mcspi->ctx.modulctrl; | |
1189 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1190 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1191 | mcspi->ctx.modulctrl = | |
1192 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1193 | } | |
1194 | ||
5fda88f5 | 1195 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1196 | |
a06b430f MW |
1197 | if (gpio_is_valid(spi->cs_gpio)) |
1198 | omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); | |
1199 | ||
d33f473d IS |
1200 | if (mcspi->fifo_depth > 0 && t) |
1201 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1202 | |
b28cb941 | 1203 | return status; |
ccdc7bf9 SO |
1204 | } |
1205 | ||
468a3208 NA |
1206 | static int omap2_mcspi_prepare_message(struct spi_master *master, |
1207 | struct spi_message *msg) | |
1208 | { | |
1209 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1210 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
1211 | struct omap2_mcspi_cs *cs; | |
1212 | ||
1213 | /* Only a single channel can have the FORCE bit enabled | |
1214 | * in its chconf0 register. | |
1215 | * Scan all channels and disable them except the current one. | |
1216 | * A FORCE can remain from a last transfer having cs_change enabled | |
1217 | */ | |
1218 | list_for_each_entry(cs, &ctx->cs, node) { | |
1219 | if (msg->spi->controller_state == cs) | |
1220 | continue; | |
1221 | ||
1222 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { | |
1223 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
1224 | writel_relaxed(cs->chconf0, | |
1225 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1226 | readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
0ba1870f FCJ |
1233 | static bool omap2_mcspi_can_dma(struct spi_master *master, |
1234 | struct spi_device *spi, | |
1235 | struct spi_transfer *xfer) | |
ccdc7bf9 | 1236 | { |
0ba1870f | 1237 | return (xfer->len >= DMA_MIN_BYTES); |
ccdc7bf9 SO |
1238 | } |
1239 | ||
fd4a319b | 1240 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1241 | { |
1242 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1243 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1244 | int ret = 0; |
ccdc7bf9 | 1245 | |
034d3dc9 | 1246 | ret = pm_runtime_get_sync(mcspi->dev); |
5a686b2c TL |
1247 | if (ret < 0) { |
1248 | pm_runtime_put_noidle(mcspi->dev); | |
1249 | ||
1f1a4384 | 1250 | return ret; |
5a686b2c | 1251 | } |
ddb22195 | 1252 | |
39f8052d | 1253 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1254 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1255 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1256 | |
1257 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1258 | pm_runtime_mark_last_busy(mcspi->dev); |
1259 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1260 | return 0; |
1261 | } | |
1262 | ||
52e9a5bb TL |
1263 | /* |
1264 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1265 | * inactive state when driver was suspend, then force it to inactive state at | |
1266 | * wake up. | |
1267 | */ | |
1f1a4384 G |
1268 | static int omap_mcspi_runtime_resume(struct device *dev) |
1269 | { | |
52e9a5bb TL |
1270 | struct spi_master *master = dev_get_drvdata(dev); |
1271 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1272 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
1273 | struct omap2_mcspi_cs *cs; | |
1f1a4384 | 1274 | |
52e9a5bb TL |
1275 | /* McSPI: context restore */ |
1276 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); | |
1277 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
1278 | ||
1279 | list_for_each_entry(cs, &ctx->cs, node) { | |
1280 | /* | |
1281 | * We need to toggle CS state for OMAP take this | |
1282 | * change in account. | |
1283 | */ | |
1284 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { | |
1285 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; | |
1286 | writel_relaxed(cs->chconf0, | |
1287 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1288 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
1289 | writel_relaxed(cs->chconf0, | |
1290 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1291 | } else { | |
1292 | writel_relaxed(cs->chconf0, | |
1293 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1294 | } | |
1295 | } | |
1f1a4384 G |
1296 | |
1297 | return 0; | |
1298 | } | |
1299 | ||
d5a80031 BC |
1300 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1301 | .regs_offset = 0, | |
1302 | }; | |
1303 | ||
1304 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1305 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1306 | }; | |
1307 | ||
1308 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1309 | { | |
1310 | .compatible = "ti,omap2-mcspi", | |
1311 | .data = &omap2_pdata, | |
1312 | }, | |
1313 | { | |
1314 | .compatible = "ti,omap4-mcspi", | |
1315 | .data = &omap4_pdata, | |
1316 | }, | |
1317 | { }, | |
1318 | }; | |
1319 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1320 | |
fd4a319b | 1321 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1322 | { |
1323 | struct spi_master *master; | |
83a01e72 | 1324 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1325 | struct omap2_mcspi *mcspi; |
1326 | struct resource *r; | |
1327 | int status = 0, i; | |
d5a80031 | 1328 | u32 regs_offset = 0; |
d5a80031 BC |
1329 | struct device_node *node = pdev->dev.of_node; |
1330 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1331 | |
1332 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1333 | if (master == NULL) { | |
1334 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1335 | return -ENOMEM; | |
1336 | } | |
1337 | ||
e7db06b5 DB |
1338 | /* the spi->mode bits understood by this driver: */ |
1339 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1340 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1341 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1342 | master->auto_runtime_pm = true; |
468a3208 | 1343 | master->prepare_message = omap2_mcspi_prepare_message; |
0ba1870f | 1344 | master->can_dma = omap2_mcspi_can_dma; |
b28cb941 | 1345 | master->transfer_one = omap2_mcspi_transfer_one; |
ddcad7e9 | 1346 | master->set_cs = omap2_mcspi_set_cs; |
ccdc7bf9 | 1347 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1348 | master->dev.of_node = node; |
aca0924b AL |
1349 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1350 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1351 | |
24b5a82c | 1352 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1353 | |
1354 | mcspi = spi_master_get_devdata(master); | |
1355 | mcspi->master = master; | |
1356 | ||
d5a80031 BC |
1357 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1358 | if (match) { | |
1359 | u32 num_cs = 1; /* default number of chipselect */ | |
1360 | pdata = match->data; | |
1361 | ||
1362 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1363 | master->num_chipselect = num_cs; | |
2cd45179 DM |
1364 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1365 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1366 | } else { |
8074cf06 | 1367 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 | 1368 | master->num_chipselect = pdata->num_cs; |
0384e90b | 1369 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1370 | } |
1371 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1372 | |
ccdc7bf9 | 1373 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b0ee5605 TR |
1374 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1375 | if (IS_ERR(mcspi->base)) { | |
1376 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1377 | goto free_master; |
55c381e4 | 1378 | } |
af9e53fe V |
1379 | mcspi->phys = r->start + regs_offset; |
1380 | mcspi->base += regs_offset; | |
ccdc7bf9 | 1381 | |
1f1a4384 | 1382 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1383 | |
1bd897f8 | 1384 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1385 | |
a6f936db AL |
1386 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1387 | sizeof(struct omap2_mcspi_dma), | |
1388 | GFP_KERNEL); | |
1389 | if (mcspi->dma_channels == NULL) { | |
1390 | status = -ENOMEM; | |
1a77b127 | 1391 | goto free_master; |
a6f936db | 1392 | } |
ccdc7bf9 | 1393 | |
1a5d8190 | 1394 | for (i = 0; i < master->num_chipselect; i++) { |
b085c612 PU |
1395 | sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); |
1396 | sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); | |
ccdc7bf9 SO |
1397 | } |
1398 | ||
27b5284c S |
1399 | pm_runtime_use_autosuspend(&pdev->dev); |
1400 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1401 | pm_runtime_enable(&pdev->dev); |
1402 | ||
142e07be WY |
1403 | status = omap2_mcspi_master_setup(mcspi); |
1404 | if (status < 0) | |
39f1b565 | 1405 | goto disable_pm; |
ccdc7bf9 | 1406 | |
b95e02b7 | 1407 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1408 | if (status < 0) |
37a2d84a | 1409 | goto disable_pm; |
ccdc7bf9 SO |
1410 | |
1411 | return status; | |
1412 | ||
39f1b565 | 1413 | disable_pm: |
0e6f357a TL |
1414 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1415 | pm_runtime_put_sync(&pdev->dev); | |
751c925c | 1416 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1417 | free_master: |
37a2d84a | 1418 | spi_master_put(master); |
ccdc7bf9 SO |
1419 | return status; |
1420 | } | |
1421 | ||
fd4a319b | 1422 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1423 | { |
a6f936db AL |
1424 | struct spi_master *master = platform_get_drvdata(pdev); |
1425 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1426 | |
0e6f357a | 1427 | pm_runtime_dont_use_autosuspend(mcspi->dev); |
a93a2029 | 1428 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1429 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1430 | |
ccdc7bf9 SO |
1431 | return 0; |
1432 | } | |
1433 | ||
7e38c3c4 KS |
1434 | /* work with hotplug and coldplug */ |
1435 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1436 | ||
42ce7fd6 | 1437 | #ifdef CONFIG_SUSPEND |
5a686b2c | 1438 | static int omap2_mcspi_suspend_noirq(struct device *dev) |
42ce7fd6 | 1439 | { |
5a686b2c | 1440 | return pinctrl_pm_select_sleep_state(dev); |
beca3655 PH |
1441 | } |
1442 | ||
5a686b2c | 1443 | static int omap2_mcspi_resume_noirq(struct device *dev) |
beca3655 | 1444 | { |
5a686b2c TL |
1445 | struct spi_master *master = dev_get_drvdata(dev); |
1446 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1447 | int error; | |
1448 | ||
1449 | error = pinctrl_pm_select_default_state(dev); | |
1450 | if (error) | |
1451 | dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", | |
1452 | __func__, error); | |
1453 | ||
5a686b2c | 1454 | return 0; |
42ce7fd6 | 1455 | } |
beca3655 | 1456 | |
42ce7fd6 | 1457 | #else |
5a686b2c TL |
1458 | #define omap2_mcspi_suspend_noirq NULL |
1459 | #define omap2_mcspi_resume_noirq NULL | |
42ce7fd6 GC |
1460 | #endif |
1461 | ||
1462 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
5a686b2c TL |
1463 | .suspend_noirq = omap2_mcspi_suspend_noirq, |
1464 | .resume_noirq = omap2_mcspi_resume_noirq, | |
1f1a4384 | 1465 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1466 | }; |
1467 | ||
ccdc7bf9 SO |
1468 | static struct platform_driver omap2_mcspi_driver = { |
1469 | .driver = { | |
1470 | .name = "omap2_mcspi", | |
d5a80031 BC |
1471 | .pm = &omap2_mcspi_pm_ops, |
1472 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1473 | }, |
7d6b6d83 | 1474 | .probe = omap2_mcspi_probe, |
fd4a319b | 1475 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1476 | }; |
1477 | ||
9fdca9df | 1478 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1479 | MODULE_LICENSE("GPL"); |