[linux-2.6-block.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t hz = 0;

	hz = dev->max_speed_hz;
	if (t && t->speed_hz)
		hz = min(hz, t->speed_hz);
	if (hz == 0) {
		dev_err(&dev->dev, "Cannot continue with zero clock\n");
		return -EINVAL;
	}

	mxs_ssp_set_clk_rate(ssp, hz);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
		     BF_SSP_CTRL1_WORD_LENGTH
		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
		     ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static int mxs_spi_setup(struct spi_device *dev)
{
	int err = 0;

	if (!dev->bits_per_word)
		dev->bits_per_word = 8;

	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
		return -EINVAL;

	err = mxs_spi_setup_transfer(dev, NULL);
	if (err) {
		dev_err(&dev->dev,
			"Failed to setup transfer, error = %d\n", err);
	}

	return err;
}

static uint32_t mxs_spi_cs_to_reg(unsigned cs)
{
	uint32_t select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
{
	const uint32_t mask =
		BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
	uint32_t select;
	struct mxs_ssp *ssp = &spi->ssp;

	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	select = mxs_spi_cs_to_reg(cs);
	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static inline void mxs_spi_enable(struct mxs_spi *spi)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	writel(BM_SSP_CTRL0_IGNORE_CRC,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
}

static inline void mxs_spi_disable(struct mxs_spi *spi)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(BM_SSP_CTRL0_IGNORE_CRC,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;
	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;
	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	uint32_t ctrl0;
	struct page *vm_page;
	void *sg_buf;
	struct {
		uint32_t		pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	INIT_COMPLETION(spi->c);

	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);

	if (*first)
		ctrl0 |= BM_SSP_CTRL0_LOCK_CS;
	if (!write)
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		min = min(len, desc_len);

		/* Prepare the transfer descriptor. */
		if ((sg_count + 1 == sgs) && *last)
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}
			sg_buf = page_address(vm_page) +
				((size_t)buf & ~PAGE_MASK);
		} else {
			sg_buf = buf;
		}

		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	ret = wait_for_completion_timeout(&spi->c,
				msecs_to_jiffies(SSP_TIMEOUT));
	if (!ret) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;

	if (*first)
		mxs_spi_enable(spi);

	mxs_spi_set_cs(spi, cs);

	while (len--) {
		if (*last && len == 0)
			mxs_spi_disable(spi);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (write)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (write)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!write) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int first, last;
	struct spi_transfer *t, *tmp_t;
	int status = 0;
	int cs;

	first = last = 0;

	cs = m->spi->chip_select;

	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		if (&t->transfer_list == m->transfers.next)
			first = 1;
		if (&t->transfer_list == m->transfers.prev)
			last = 1;
		if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
			dev_err(ssp->dev,
				"Cannot send and receive simultaneously\n");
			status = -EINVAL;
			break;
		}

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						(void *)t->tx_buf,
						t->len, &first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						(void *)t->tx_buf, t->len,
						&first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
		first = last = 0;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return -EINVAL;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->setup = mxs_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       DRIVER_NAME, ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		goto out_dma_release;

	clk_set_rate(ssp->clk, clk_freq);
	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_disable_clk;

	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_disable_clk;
	}

	return 0;

out_disable_clk:
	clk_disable_unprepare(ssp->clk);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = spi_master_get(platform_get_drvdata(pdev));
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	spi_unregister_master(master);
	clk_disable_unprepare(ssp->clk);
	dma_release_channel(ssp->dmach);
	spi_master_put(master);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/of.h>
	35	#include <linux/of_device.h>
	36	#include <linux/of_gpio.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/dmaengine.h>
	42	#include <linux/highmem.h>
	43	#include <linux/clk.h>
	44	#include <linux/err.h>
	45	#include <linux/completion.h>
	46	#include <linux/gpio.h>
	47	#include <linux/regulator/consumer.h>
	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
646781d3 MV	60	struct mxs_spi {
646781d3 MV	61	struct mxs_ssp ssp;
474afc04	62	struct completion c;
646781d3 MV	63	};
	64
	65	static int mxs_spi_setup_transfer(struct spi_device *dev,
	66	struct spi_transfer *t)
	67	{
	68	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	69	struct mxs_ssp *ssp = &spi->ssp;
646781d3 MV	70	uint32_t hz = 0;
646781d3 MV	71
646781d3 MV	72	hz = dev->max_speed_hz;
	73	if (t && t->speed_hz)
	74	hz = min(hz, t->speed_hz);
	75	if (hz == 0) {
	76	dev_err(&dev->dev, "Cannot continue with zero clock\n");
	77	return -EINVAL;
	78	}
	79
	80	mxs_ssp_set_clk_rate(ssp, hz);
	81
	82	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
	83	BF_SSP_CTRL1_WORD_LENGTH
	84	(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	85	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	86	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	87	ssp->base + HW_SSP_CTRL1(ssp));
	88
	89	writel(0x0, ssp->base + HW_SSP_CMD0);
	90	writel(0x0, ssp->base + HW_SSP_CMD1);
	91
	92	return 0;
	93	}
	94
	95	static int mxs_spi_setup(struct spi_device *dev)
	96	{
	97	int err = 0;
	98
	99	if (!dev->bits_per_word)
	100	dev->bits_per_word = 8;
	101
	102	if (dev->mode & ~(SPI_CPOL \| SPI_CPHA))
	103	return -EINVAL;
	104
	105	err = mxs_spi_setup_transfer(dev, NULL);
	106	if (err) {
	107	dev_err(&dev->dev,
	108	"Failed to setup transfer, error = %d\n", err);
	109	}
	110
	111	return err;
	112	}
	113
	114	static uint32_t mxs_spi_cs_to_reg(unsigned cs)
	115	{
	116	uint32_t select = 0;
	117
	118	/*
	119	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	120	*
	121	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	122	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	123	* the datasheet for further details. In SPI mode, they are used to
	124	* toggle the chip-select lines (nCS pins).
	125	*/
	126	if (cs & 1)
	127	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	128	if (cs & 2)
	129	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	130
	131	return select;
	132	}
	133
	134	static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
	135	{
136	const uint32_t mask =
137	BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ;
138	uint32_t select;
139	struct mxs_ssp *ssp = &spi->ssp;
140
141	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
142	select = mxs_spi_cs_to_reg(cs);
143	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
144	}
145
146	static inline void mxs_spi_enable(struct mxs_spi *spi)
147	{
148	struct mxs_ssp *ssp = &spi->ssp;
149
150	writel(BM_SSP_CTRL0_LOCK_CS,
151	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
152	writel(BM_SSP_CTRL0_IGNORE_CRC,
153	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
154	}
155
156	static inline void mxs_spi_disable(struct mxs_spi *spi)
157	{
158	struct mxs_ssp *ssp = &spi->ssp;
159
160	writel(BM_SSP_CTRL0_LOCK_CS,
161	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
162	writel(BM_SSP_CTRL0_IGNORE_CRC,
163	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
164	}
165
166	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
167	{
f13639dc	168	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3 MV	169	struct mxs_ssp *ssp = &spi->ssp;
	170	uint32_t reg;
	171
f13639dc	172	do {
646781d3 MV	173	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	174
f13639dc MV	175	if (!set)
f13639dc MV	176	reg = ~reg;
646781d3	177
f13639dc	178	reg &= mask;
646781d3	179
f13639dc MV	180	if (reg == mask)
	181	return 0;
	182	} while (time_before(jiffies, timeout));
646781d3	183
f13639dc	184	return -ETIMEDOUT;
646781d3 MV	185	}
646781d3 MV	186
474afc04 MV	187	static void mxs_ssp_dma_irq_callback(void *param)
	188	{
	189	struct mxs_spi *spi = param;
	190	complete(&spi->c);
	191	}
	192
	193	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	194	{
	195	struct mxs_ssp *ssp = dev_id;
	196	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	197	__func__, __LINE__,
	198	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	199	readl(ssp->base + HW_SSP_STATUS(ssp)));
	200	return IRQ_HANDLED;
	201	}
	202
	203	static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
	204	unsigned char *buf, int len,
	205	int first, int last, int write)
	206	{
	207	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	208	struct dma_async_tx_descriptor *desc = NULL;
	209	const bool vmalloced_buf = is_vmalloc_addr(buf);
	210	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	211	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	212	int sg_count;
010b4818 MV	213	int min, ret;
	214	uint32_t ctrl0;
	215	struct page *vm_page;
	216	void *sg_buf;
	217	struct {
	218	uint32_t pio[4];
	219	struct scatterlist sg;
	220	} *dma_xfer;
	221
	222	if (!len)
474afc04	223	return -EINVAL;
010b4818 MV	224
	225	dma_xfer = kzalloc(sizeof(dma_xfer) sgs, GFP_KERNEL);
	226	if (!dma_xfer)
	227	return -ENOMEM;
474afc04	228
41682e03	229	INIT_COMPLETION(spi->c);
474afc04	230
010b4818	231	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
ba486a2a	232	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818 MV	233	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER \| mxs_spi_cs_to_reg(cs);
010b4818 MV	234
474afc04	235	if (*first)
010b4818	236	ctrl0 \|= BM_SSP_CTRL0_LOCK_CS;
474afc04	237	if (!write)
010b4818	238	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	239
474afc04 MV	240	/* Queue the DMA data transfer. */
010b4818 MV	241	for (sg_count = 0; sg_count < sgs; sg_count++) {
	242	min = min(len, desc_len);
	243
	244	/* Prepare the transfer descriptor. */
	245	if ((sg_count + 1 == sgs) && *last)
	246	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
	247
ba486a2a JL	248	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	249	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	250	ctrl0 \|= min;
ba486a2a	251	}
010b4818 MV	252
	253	dma_xfer[sg_count].pio[0] = ctrl0;
	254	dma_xfer[sg_count].pio[3] = min;
	255
	256	if (vmalloced_buf) {
	257	vm_page = vmalloc_to_page(buf);
	258	if (!vm_page) {
	259	ret = -ENOMEM;
	260	goto err_vmalloc;
	261	}
	262	sg_buf = page_address(vm_page) +
	263	((size_t)buf & ~PAGE_MASK);
	264	} else {
	265	sg_buf = buf;
	266	}
	267
	268	sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
	269	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
	270	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	271
	272	len -= min;
	273	buf += min;
	274
	275	/* Queue the PIO register write transfer. */
	276	desc = dmaengine_prep_slave_sg(ssp->dmach,
	277	(struct scatterlist *)dma_xfer[sg_count].pio,
	278	(ssp->devid == IMX23_SSP) ? 1 : 4,
	279	DMA_TRANS_NONE,
	280	sg_count ? DMA_PREP_INTERRUPT : 0);
	281	if (!desc) {
	282	dev_err(ssp->dev,
	283	"Failed to get PIO reg. write descriptor.\n");
	284	ret = -EINVAL;
	285	goto err_mapped;
	286	}
	287
	288	desc = dmaengine_prep_slave_sg(ssp->dmach,
	289	&dma_xfer[sg_count].sg, 1,
	290	write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
	291	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	292
	293	if (!desc) {
	294	dev_err(ssp->dev,
	295	"Failed to get DMA data write descriptor.\n");
	296	ret = -EINVAL;
	297	goto err_mapped;
	298	}
474afc04 MV	299	}
	300
	301	/*
	302	* The last descriptor must have this callback,
	303	* to finish the DMA transaction.
	304	*/
	305	desc->callback = mxs_ssp_dma_irq_callback;
	306	desc->callback_param = spi;
	307
	308	/* Start the transfer. */
	309	dmaengine_submit(desc);
	310	dma_async_issue_pending(ssp->dmach);
	311
	312	ret = wait_for_completion_timeout(&spi->c,
	313	msecs_to_jiffies(SSP_TIMEOUT));
474afc04 MV	314	if (!ret) {
	315	dev_err(ssp->dev, "DMA transfer timeout\n");
	316	ret = -ETIMEDOUT;
44968466	317	dmaengine_terminate_all(ssp->dmach);
010b4818	318	goto err_vmalloc;
474afc04 MV	319	}
	320
	321	ret = 0;
	322
010b4818 MV	323	err_vmalloc:
	324	while (--sg_count >= 0) {
	325	err_mapped:
	326	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
474afc04 MV	327	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	328	}
	329
010b4818 MV	330	kfree(dma_xfer);
010b4818 MV	331
474afc04 MV	332	return ret;
	333	}
	334
646781d3 MV	335	static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
	336	unsigned char *buf, int len,
	337	int first, int last, int write)
	338	{
	339	struct mxs_ssp *ssp = &spi->ssp;
	340
	341	if (*first)
	342	mxs_spi_enable(spi);
	343
	344	mxs_spi_set_cs(spi, cs);
	345
	346	while (len--) {
	347	if (*last && len == 0)
	348	mxs_spi_disable(spi);
	349
	350	if (ssp->devid == IMX23_SSP) {
	351	writel(BM_SSP_CTRL0_XFER_COUNT,
	352	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	353	writel(1,
	354	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	355	} else {
	356	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	357	}
	358
	359	if (write)
	360	writel(BM_SSP_CTRL0_READ,
	361	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	362	else
	363	writel(BM_SSP_CTRL0_READ,
	364	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	365
	366	writel(BM_SSP_CTRL0_RUN,
	367	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	368
	369	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	370	return -ETIMEDOUT;
	371
	372	if (write)
	373	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	374
	375	writel(BM_SSP_CTRL0_DATA_XFER,
	376	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	377
	378	if (!write) {
	379	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	380	BM_SSP_STATUS_FIFO_EMPTY, 0))
	381	return -ETIMEDOUT;
	382
	383	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	384	}
	385
	386	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	387	return -ETIMEDOUT;
	388
	389	buf++;
	390	}
	391
	392	if (len <= 0)
	393	return 0;
	394
	395	return -ETIMEDOUT;
	396	}
	397
	398	static int mxs_spi_transfer_one(struct spi_master *master,
399	struct spi_message *m)
400	{
401	struct mxs_spi *spi = spi_master_get_devdata(master);
402	struct mxs_ssp *ssp = &spi->ssp;
403	int first, last;
404	struct spi_transfer t, tmp_t;
405	int status = 0;
406	int cs;
407
408	first = last = 0;
409
410	cs = m->spi->chip_select;
411
412	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
413
414	status = mxs_spi_setup_transfer(m->spi, t);
415	if (status)
416	break;
417
418	if (&t->transfer_list == m->transfers.next)
419	first = 1;
420	if (&t->transfer_list == m->transfers.prev)
421	last = 1;
474afc04	422	if ((t->rx_buf && t->tx_buf) \|\| (t->rx_dma && t->tx_dma)) {
646781d3 MV	423	dev_err(ssp->dev,
	424	"Cannot send and receive simultaneously\n");
	425	status = -EINVAL;
	426	break;
	427	}
	428
474afc04 MV	429	/*
	430	* Small blocks can be transfered via PIO.
	431	* Measured by empiric means:
	432	*
	433	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	434	*
	435	* DMA only: 2.164808 seconds, 473.0KB/s
	436	* Combined: 1.676276 seconds, 610.9KB/s
	437	*/
727c10e3	438	if (t->len < 32) {
474afc04 MV	439	writel(BM_SSP_CTRL1_DMA_ENABLE,
	440	ssp->base + HW_SSP_CTRL1(ssp) +
	441	STMP_OFFSET_REG_CLR);
	442
	443	if (t->tx_buf)
	444	status = mxs_spi_txrx_pio(spi, cs,
	445	(void *)t->tx_buf,
	446	t->len, &first, &last, 1);
	447	if (t->rx_buf)
	448	status = mxs_spi_txrx_pio(spi, cs,
	449	t->rx_buf, t->len,
	450	&first, &last, 0);
	451	} else {
	452	writel(BM_SSP_CTRL1_DMA_ENABLE,
	453	ssp->base + HW_SSP_CTRL1(ssp) +
	454	STMP_OFFSET_REG_SET);
	455
	456	if (t->tx_buf)
	457	status = mxs_spi_txrx_dma(spi, cs,
	458	(void *)t->tx_buf, t->len,
	459	&first, &last, 1);
	460	if (t->rx_buf)
	461	status = mxs_spi_txrx_dma(spi, cs,
	462	t->rx_buf, t->len,
	463	&first, &last, 0);
	464	}
646781d3	465
c895db0f MV	466	if (status) {
c895db0f MV	467	stmp_reset_block(ssp->base);
646781d3	468	break;
c895db0f	469	}
646781d3	470
204e706f	471	m->actual_length += t->len;
646781d3 MV	472	first = last = 0;
	473	}
	474
d856f1eb	475	m->status = status;
646781d3 MV	476	spi_finalize_current_message(master);
	477
	478	return status;
	479	}
	480
	481	static const struct of_device_id mxs_spi_dt_ids[] = {
	482	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	483	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	484	{ /* sentinel */ }
	485	};
	486	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	487
fd4a319b	488	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	489	{
	490	const struct of_device_id *of_id =
	491	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	492	struct device_node *np = pdev->dev.of_node;
	493	struct spi_master *master;
	494	struct mxs_spi *spi;
	495	struct mxs_ssp *ssp;
26aafa77	496	struct resource *iores;
646781d3 MV	497	struct clk *clk;
646781d3 MV	498	void __iomem *base;
26aafa77 SG	499	int devid, clk_freq;
26aafa77 SG	500	int ret = 0, irq_err;
646781d3	501
e64d07a2 MV	502	/*
	503	* Default clock speed for the SPI core. 160MHz seems to
	504	* work reasonably well with most SPI flashes, so use this
	505	* as a default. Override with "clock-frequency" DT prop.
	506	*/
	507	const int clk_freq_default = 160000000;
	508
646781d3	509	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	510	irq_err = platform_get_irq(pdev, 0);
796305a2	511	if (irq_err < 0)
646781d3 MV	512	return -EINVAL;
646781d3 MV	513
b0ee5605 TR	514	base = devm_ioremap_resource(&pdev->dev, iores);
	515	if (IS_ERR(base))
	516	return PTR_ERR(base);
646781d3	517
646781d3 MV	518	clk = devm_clk_get(&pdev->dev, NULL);
	519	if (IS_ERR(clk))
	520	return PTR_ERR(clk);
	521
26aafa77 SG	522	devid = (enum mxs_ssp_id) of_id->data;
	523	ret = of_property_read_u32(np, "clock-frequency",
	524	&clk_freq);
	525	if (ret)
e64d07a2	526	clk_freq = clk_freq_default;
646781d3 MV	527
	528	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	529	if (!master)
	530	return -ENOMEM;
	531
	532	master->transfer_one_message = mxs_spi_transfer_one;
	533	master->setup = mxs_spi_setup;
24778be2	534	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	535	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	536	master->num_chipselect = 3;
	537	master->dev.of_node = np;
	538	master->flags = SPI_MASTER_HALF_DUPLEX;
	539
	540	spi = spi_master_get_devdata(master);
	541	ssp = &spi->ssp;
	542	ssp->dev = &pdev->dev;
	543	ssp->clk = clk;
	544	ssp->base = base;
	545	ssp->devid = devid;
474afc04	546
41682e03 MV	547	init_completion(&spi->c);
41682e03 MV	548
474afc04 MV	549	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
	550	DRIVER_NAME, ssp);
	551	if (ret)
	552	goto out_master_free;
	553
26aafa77	554	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	555	if (!ssp->dmach) {
474afc04 MV	556	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	557	ret = -ENODEV;
474afc04 MV	558	goto out_master_free;
474afc04 MV	559	}
646781d3	560
9c4a39af FE	561	ret = clk_prepare_enable(ssp->clk);
	562	if (ret)
	563	goto out_dma_release;
	564
e64d07a2	565	clk_set_rate(ssp->clk, clk_freq);
646781d3 MV	566	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
646781d3 MV	567
8498bce9 FE	568	ret = stmp_reset_block(ssp->base);
	569	if (ret)
	570	goto out_disable_clk;
646781d3 MV	571
	572	platform_set_drvdata(pdev, master);
	573
	574	ret = spi_register_master(master);
	575	if (ret) {
	576	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
9c4a39af	577	goto out_disable_clk;
646781d3 MV	578	}
	579
	580	return 0;
	581
9c4a39af	582	out_disable_clk:
646781d3	583	clk_disable_unprepare(ssp->clk);
9c4a39af	584	out_dma_release:
e11933f6	585	dma_release_channel(ssp->dmach);
474afc04	586	out_master_free:
646781d3 MV	587	spi_master_put(master);
	588	return ret;
	589	}
	590
fd4a319b	591	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	592	{
	593	struct spi_master *master;
	594	struct mxs_spi *spi;
	595	struct mxs_ssp *ssp;
	596
7d520d28	597	master = spi_master_get(platform_get_drvdata(pdev));
646781d3 MV	598	spi = spi_master_get_devdata(master);
	599	ssp = &spi->ssp;
	600
	601	spi_unregister_master(master);
646781d3	602	clk_disable_unprepare(ssp->clk);
e11933f6	603	dma_release_channel(ssp->dmach);
646781d3 MV	604	spi_master_put(master);
	605
	606	return 0;
	607	}
	608
	609	static struct platform_driver mxs_spi_driver = {
	610	.probe = mxs_spi_probe,
fd4a319b	611	.remove = mxs_spi_remove,
646781d3 MV	612	.driver = {
	613	.name = DRIVER_NAME,
	614	.owner = THIS_MODULE,
	615	.of_match_table = mxs_spi_dt_ids,
	616	},
	617	};
	618
	619	module_platform_driver(mxs_spi_driver);
	620
	621	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	622	MODULE_DESCRIPTION("MXS SPI master driver");
	623	MODULE_LICENSE("GPL");
	624	MODULE_ALIAS("platform:mxs-spi");