[linux-2.6-block.git] / drivers / spi / spi-mxs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Freescale MXS SPI master driver
//
// Copyright 2012 DENX Software Engineering, GmbH.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
//
// Rework and transition to new API by:
// Marek Vasut <marex@denx.de>
//
// Based on previous attempt by:
// Fabio Estevam <fabio.estevam@freescale.com>
//
// Based on code from U-Boot bootloader by:
// Marek Vasut <marex@denx.de>
//
// Based on spi-stmp.c, which is:
// Author: Dmitry Pervushin <dimka@embeddedalley.com>

#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>
#include <trace/events/spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
	unsigned int		sck;	/* Rate requested (vs actual) */
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				  const struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);

	if (hz == 0) {
		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
		return -EINVAL;
	}

	if (hz != spi->sck) {
		mxs_ssp_set_clk_rate(ssp, hz);
		/*
		 * Save requested rate, hz, rather than the actual rate,
		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
		 * when the actual rate is not quite the same as requested rate.
		 */
		spi->sck = hz;
		/*
		 * Perhaps we should return an error if the actual clock is
		 * nowhere close to what was requested?
		 */
	}

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	       ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static u32 mxs_spi_cs_to_reg(unsigned cs)
{
	u32 select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	u32 reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;

	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;

	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	u32 ctrl0;
	struct page *vm_page;
	struct {
		u32			pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	reinit_completion(&spi->c);

	/* Chip select was already programmed into CTRL0 */
	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}

			sg_init_table(&dma_xfer[sg_count].sg, 1);
			sg_set_page(&dma_xfer[sg_count].sg, vm_page,
				    min, offset_in_page(buf));
		} else {
			sg_init_one(&dma_xfer[sg_count].sg, buf, min);
		}

		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	if (!wait_for_completion_timeout(&spi->c,
					 msecs_to_jiffies(SSP_TIMEOUT))) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t;
	unsigned int flag;
	int status = 0;

	/* Program CS register bits here, it will be used for all transfers. */
	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	list_for_each_entry(t, &m->transfers, transfer_list) {

		trace_spi_transfer_start(m, t);

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi,
						t->rx_buf, t->len,
						flag);
		}

		trace_spi_transfer_stop(m, t);

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int mxs_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	clk_disable_unprepare(ssp->clk);

	ret = pinctrl_pm_select_idle_state(dev);
	if (ret) {
		int ret2 = clk_prepare_enable(ssp->clk);

		if (ret2)
			dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
				 ret, ret2);
	}

	return ret;
}

static int mxs_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	ret = pinctrl_pm_select_default_state(dev);
	if (ret)
		return ret;

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		pinctrl_pm_select_idle_state(dev);

	return ret;
}

static int __maybe_unused mxs_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	ret = spi_master_suspend(master);
	if (ret)
		return ret;

	if (!pm_runtime_suspended(dev))
		return mxs_spi_runtime_suspend(dev);
	else
		return 0;
}

static int __maybe_unused mxs_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	if (!pm_runtime_suspended(dev))
		ret = mxs_spi_runtime_resume(dev);
	else
		ret = 0;
	if (ret)
		return ret;

	ret = spi_master_resume(master);
	if (ret < 0 && !pm_runtime_suspended(dev))
		mxs_spi_runtime_suspend(dev);

	return ret;
}

static const struct dev_pm_ops mxs_spi_pm = {
	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
			   mxs_spi_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
};

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return irq_err;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	master->transfer_one_message = mxs_spi_transfer_one;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->auto_runtime_pm = true;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       dev_name(&pdev->dev), ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	pm_runtime_enable(ssp->dev);
	if (!pm_runtime_enabled(ssp->dev)) {
		ret = mxs_spi_runtime_resume(ssp->dev);
		if (ret < 0) {
			dev_err(ssp->dev, "runtime resume failed\n");
			goto out_dma_release;
		}
	}

	ret = pm_runtime_get_sync(ssp->dev);
	if (ret < 0) {
		dev_err(ssp->dev, "runtime_get_sync failed\n");
		goto out_pm_runtime_disable;
	}

	clk_set_rate(ssp->clk, clk_freq);

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_pm_runtime_put;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_pm_runtime_put;
	}

	pm_runtime_put(ssp->dev);

	return 0;

out_pm_runtime_put:
	pm_runtime_put(ssp->dev);
out_pm_runtime_disable:
	pm_runtime_disable(ssp->dev);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		mxs_spi_runtime_suspend(&pdev->dev);

	dma_release_channel(ssp->dmach);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.of_match_table = mxs_spi_dt_ids,
		.pm = &mxs_spi_pm,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
4c23e486 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Freescale MXS SPI master driver
	4	//
	5	// Copyright 2012 DENX Software Engineering, GmbH.
	6	// Copyright 2012 Freescale Semiconductor, Inc.
	7	// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	8	//
	9	// Rework and transition to new API by:
	10	// Marek Vasut <marex@denx.de>
	11	//
	12	// Based on previous attempt by:
	13	// Fabio Estevam <fabio.estevam@freescale.com>
	14	//
	15	// Based on code from U-Boot bootloader by:
	16	// Marek Vasut <marex@denx.de>
	17	//
	18	// Based on spi-stmp.c, which is:
	19	// Author: Dmitry Pervushin <dimka@embeddedalley.com>
646781d3 MV	20
646781d3 MV	21	#include <linux/kernel.h>
646781d3 MV	22	#include <linux/ioport.h>
	23	#include <linux/of.h>
	24	#include <linux/of_device.h>
	25	#include <linux/of_gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/delay.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/dma-mapping.h>
	30	#include <linux/dmaengine.h>
	31	#include <linux/highmem.h>
	32	#include <linux/clk.h>
	33	#include <linux/err.h>
	34	#include <linux/completion.h>
	35	#include <linux/gpio.h>
	36	#include <linux/regulator/consumer.h>
b7969caf	37	#include <linux/pm_runtime.h>
646781d3	38	#include <linux/module.h>
646781d3 MV	39	#include <linux/stmp_device.h>
	40	#include <linux/spi/spi.h>
	41	#include <linux/spi/mxs-spi.h>
f3fdea3a	42	#include <trace/events/spi.h>
646781d3 MV	43
	44	#define DRIVER_NAME "mxs-spi"
	45
010b4818 MV	46	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	47	#define SSP_TIMEOUT 10000
646781d3	48
474afc04 MV	49	#define SG_MAXLEN 0xff00
474afc04 MV	50
28cad125 TP	51	/*
	52	* Flags for txrx functions. More efficient that using an argument register for
	53	* each one.
	54	*/
	55	#define TXRX_WRITE (1<<0) /* This is a write */
	56	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	57
646781d3 MV	58	struct mxs_spi {
646781d3 MV	59	struct mxs_ssp ssp;
474afc04	60	struct completion c;
a560943e	61	unsigned int sck; /* Rate requested (vs actual) */
646781d3 MV	62	};
	63
	64	static int mxs_spi_setup_transfer(struct spi_device *dev,
aa9e0c6f	65	const struct spi_transfer *t)
646781d3 MV	66	{
	67	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	68	struct mxs_ssp *ssp = &spi->ssp;
aa9e0c6f	69	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
646781d3	70
646781d3	71	if (hz == 0) {
aa9e0c6f	72	dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
646781d3 MV	73	return -EINVAL;
	74	}
	75
a560943e TP	76	if (hz != spi->sck) {
	77	mxs_ssp_set_clk_rate(ssp, hz);
	78	/*
	79	* Save requested rate, hz, rather than the actual rate,
a44619c3	80	* ssp->clk_rate. Otherwise we would set the rate every transfer
a560943e TP	81	* when the actual rate is not quite the same as requested rate.
	82	*/
	83	spi->sck = hz;
	84	/*
	85	* Perhaps we should return an error if the actual clock is
	86	* nowhere close to what was requested?
	87	*/
	88	}
646781d3	89
58f46e41 TP	90	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	91	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	92
646781d3 MV	93	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
aa9e0c6f TP	94	BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	95	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	96	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	97	ssp->base + HW_SSP_CTRL1(ssp));
646781d3 MV	98
	99	writel(0x0, ssp->base + HW_SSP_CMD0);
	100	writel(0x0, ssp->base + HW_SSP_CMD1);
	101
	102	return 0;
	103	}
	104
42e182f8	105	static u32 mxs_spi_cs_to_reg(unsigned cs)
646781d3	106	{
42e182f8	107	u32 select = 0;
646781d3 MV	108
	109	/*
	110	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	111	*
	112	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	113	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	114	* the datasheet for further details. In SPI mode, they are used to
	115	* toggle the chip-select lines (nCS pins).
	116	*/
	117	if (cs & 1)
	118	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	119	if (cs & 2)
	120	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	121
	122	return select;
	123	}
	124
646781d3 MV	125	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	126	{
f13639dc	127	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3	128	struct mxs_ssp *ssp = &spi->ssp;
42e182f8	129	u32 reg;
646781d3	130
f13639dc	131	do {
646781d3 MV	132	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	133
f13639dc MV	134	if (!set)
f13639dc MV	135	reg = ~reg;
646781d3	136
f13639dc	137	reg &= mask;
646781d3	138
f13639dc MV	139	if (reg == mask)
	140	return 0;
	141	} while (time_before(jiffies, timeout));
646781d3	142
f13639dc	143	return -ETIMEDOUT;
646781d3 MV	144	}
646781d3 MV	145
474afc04 MV	146	static void mxs_ssp_dma_irq_callback(void *param)
	147	{
	148	struct mxs_spi *spi = param;
a7fa3219	149
474afc04 MV	150	complete(&spi->c);
	151	}
	152
	153	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	154	{
	155	struct mxs_ssp *ssp = dev_id;
a7fa3219	156
474afc04 MV	157	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	158	__func__, __LINE__,
	159	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	160	readl(ssp->base + HW_SSP_STATUS(ssp)));
	161	return IRQ_HANDLED;
	162	}
	163
0b782f70	164	static int mxs_spi_txrx_dma(struct mxs_spi *spi,
474afc04	165	unsigned char *buf, int len,
28cad125	166	unsigned int flags)
474afc04 MV	167	{
474afc04 MV	168	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	169	struct dma_async_tx_descriptor *desc = NULL;
	170	const bool vmalloced_buf = is_vmalloc_addr(buf);
	171	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	172	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	173	int sg_count;
010b4818	174	int min, ret;
42e182f8	175	u32 ctrl0;
010b4818	176	struct page *vm_page;
010b4818	177	struct {
42e182f8	178	u32 pio[4];
010b4818 MV	179	struct scatterlist sg;
	180	} *dma_xfer;
	181
	182	if (!len)
474afc04	183	return -EINVAL;
010b4818	184
a7fa3219	185	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
010b4818 MV	186	if (!dma_xfer)
010b4818 MV	187	return -ENOMEM;
474afc04	188
16735d02	189	reinit_completion(&spi->c);
474afc04	190
0b782f70	191	/* Chip select was already programmed into CTRL0 */
010b4818	192	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	193	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	194	BM_SSP_CTRL0_READ);
0b782f70	195	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER;
010b4818	196
28cad125	197	if (!(flags & TXRX_WRITE))
010b4818	198	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	199
474afc04 MV	200	/* Queue the DMA data transfer. */
010b4818	201	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	202	/* Prepare the transfer descriptor. */
010b4818 MV	203	min = min(len, desc_len);
010b4818 MV	204
28cad125 TP	205	/*
	206	* De-assert CS on last segment if flag is set (i.e., no more
	207	* transfers will follow)
	208	*/
	209	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	210	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	211
ba486a2a JL	212	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	213	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	214	ctrl0 \|= min;
ba486a2a	215	}
010b4818 MV	216
	217	dma_xfer[sg_count].pio[0] = ctrl0;
	218	dma_xfer[sg_count].pio[3] = min;
	219
	220	if (vmalloced_buf) {
	221	vm_page = vmalloc_to_page(buf);
	222	if (!vm_page) {
	223	ret = -ENOMEM;
	224	goto err_vmalloc;
	225	}
9e8987ac CK	226
	227	sg_init_table(&dma_xfer[sg_count].sg, 1);
	228	sg_set_page(&dma_xfer[sg_count].sg, vm_page,
	229	min, offset_in_page(buf));
010b4818	230	} else {
9e8987ac	231	sg_init_one(&dma_xfer[sg_count].sg, buf, min);
010b4818 MV	232	}
010b4818 MV	233
010b4818	234	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	235	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	236
	237	len -= min;
	238	buf += min;
	239
	240	/* Queue the PIO register write transfer. */
	241	desc = dmaengine_prep_slave_sg(ssp->dmach,
	242	(struct scatterlist *)dma_xfer[sg_count].pio,
	243	(ssp->devid == IMX23_SSP) ? 1 : 4,
	244	DMA_TRANS_NONE,
	245	sg_count ? DMA_PREP_INTERRUPT : 0);
	246	if (!desc) {
	247	dev_err(ssp->dev,
	248	"Failed to get PIO reg. write descriptor.\n");
	249	ret = -EINVAL;
	250	goto err_mapped;
	251	}
	252
	253	desc = dmaengine_prep_slave_sg(ssp->dmach,
	254	&dma_xfer[sg_count].sg, 1,
28cad125	255	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	256	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	257
	258	if (!desc) {
	259	dev_err(ssp->dev,
	260	"Failed to get DMA data write descriptor.\n");
	261	ret = -EINVAL;
	262	goto err_mapped;
	263	}
474afc04 MV	264	}
	265
	266	/*
	267	* The last descriptor must have this callback,
	268	* to finish the DMA transaction.
	269	*/
	270	desc->callback = mxs_ssp_dma_irq_callback;
	271	desc->callback_param = spi;
	272
	273	/* Start the transfer. */
	274	dmaengine_submit(desc);
	275	dma_async_issue_pending(ssp->dmach);
	276
f2234691 NMG	277	if (!wait_for_completion_timeout(&spi->c,
f2234691 NMG	278	msecs_to_jiffies(SSP_TIMEOUT))) {
474afc04 MV	279	dev_err(ssp->dev, "DMA transfer timeout\n");
474afc04 MV	280	ret = -ETIMEDOUT;
44968466	281	dmaengine_terminate_all(ssp->dmach);
010b4818	282	goto err_vmalloc;
474afc04 MV	283	}
	284
	285	ret = 0;
	286
010b4818 MV	287	err_vmalloc:
	288	while (--sg_count >= 0) {
	289	err_mapped:
	290	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	291	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	292	}
474afc04 MV	293
010b4818 MV	294	kfree(dma_xfer);
010b4818 MV	295
474afc04 MV	296	return ret;
	297	}
	298
0b782f70	299	static int mxs_spi_txrx_pio(struct mxs_spi *spi,
646781d3	300	unsigned char *buf, int len,
28cad125	301	unsigned int flags)
646781d3 MV	302	{
	303	struct mxs_ssp *ssp = &spi->ssp;
	304
75e73fa2 TP	305	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	306	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	307
646781d3 MV	308	while (len--) {
28cad125	309	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	310	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	311	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	312
	313	if (ssp->devid == IMX23_SSP) {
	314	writel(BM_SSP_CTRL0_XFER_COUNT,
	315	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	316	writel(1,
	317	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	318	} else {
	319	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	320	}
	321
28cad125	322	if (flags & TXRX_WRITE)
646781d3 MV	323	writel(BM_SSP_CTRL0_READ,
	324	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	325	else
	326	writel(BM_SSP_CTRL0_READ,
	327	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	328
	329	writel(BM_SSP_CTRL0_RUN,
	330	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	331
	332	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	333	return -ETIMEDOUT;
	334
28cad125	335	if (flags & TXRX_WRITE)
646781d3 MV	336	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	337
	338	writel(BM_SSP_CTRL0_DATA_XFER,
	339	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	340
28cad125	341	if (!(flags & TXRX_WRITE)) {
646781d3 MV	342	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	343	BM_SSP_STATUS_FIFO_EMPTY, 0))
	344	return -ETIMEDOUT;
	345
	346	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	347	}
	348
	349	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	350	return -ETIMEDOUT;
	351
	352	buf++;
	353	}
	354
	355	if (len <= 0)
	356	return 0;
	357
	358	return -ETIMEDOUT;
	359	}
	360
	361	static int mxs_spi_transfer_one(struct spi_master *master,
	362	struct spi_message *m)
	363	{
	364	struct mxs_spi *spi = spi_master_get_devdata(master);
	365	struct mxs_ssp *ssp = &spi->ssp;
9a7da6cc	366	struct spi_transfer *t;
28cad125	367	unsigned int flag;
646781d3	368	int status = 0;
646781d3	369
0b782f70 TP	370	/* Program CS register bits here, it will be used for all transfers. */
	371	writel(BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ,
	372	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	373	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	374	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3	375
9a7da6cc	376	list_for_each_entry(t, &m->transfers, transfer_list) {
646781d3	377
f3fdea3a UKK	378	trace_spi_transfer_start(m, t);
f3fdea3a UKK	379
646781d3 MV	380	status = mxs_spi_setup_transfer(m->spi, t);
	381	if (status)
	382	break;
	383
28cad125 TP	384	/* De-assert on last transfer, inverted by cs_change flag */
	385	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	386	TXRX_DEASSERT_CS : 0;
646781d3	387
474afc04 MV	388	/*
	389	* Small blocks can be transfered via PIO.
	390	* Measured by empiric means:
	391	*
	392	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	393	*
	394	* DMA only: 2.164808 seconds, 473.0KB/s
	395	* Combined: 1.676276 seconds, 610.9KB/s
	396	*/
727c10e3	397	if (t->len < 32) {
474afc04 MV	398	writel(BM_SSP_CTRL1_DMA_ENABLE,
	399	ssp->base + HW_SSP_CTRL1(ssp) +
	400	STMP_OFFSET_REG_CLR);
	401
	402	if (t->tx_buf)
0b782f70	403	status = mxs_spi_txrx_pio(spi,
474afc04	404	(void *)t->tx_buf,
28cad125	405	t->len, flag \| TXRX_WRITE);
474afc04	406	if (t->rx_buf)
0b782f70	407	status = mxs_spi_txrx_pio(spi,
474afc04	408	t->rx_buf, t->len,
28cad125	409	flag);
474afc04 MV	410	} else {
	411	writel(BM_SSP_CTRL1_DMA_ENABLE,
	412	ssp->base + HW_SSP_CTRL1(ssp) +
	413	STMP_OFFSET_REG_SET);
	414
	415	if (t->tx_buf)
0b782f70	416	status = mxs_spi_txrx_dma(spi,
474afc04	417	(void *)t->tx_buf, t->len,
28cad125	418	flag \| TXRX_WRITE);
474afc04	419	if (t->rx_buf)
0b782f70	420	status = mxs_spi_txrx_dma(spi,
474afc04	421	t->rx_buf, t->len,
28cad125	422	flag);
474afc04	423	}
646781d3	424
f3fdea3a UKK	425	trace_spi_transfer_stop(m, t);
f3fdea3a UKK	426
c895db0f MV	427	if (status) {
c895db0f MV	428	stmp_reset_block(ssp->base);
646781d3	429	break;
c895db0f	430	}
646781d3	431
204e706f	432	m->actual_length += t->len;
646781d3 MV	433	}
646781d3 MV	434
d856f1eb	435	m->status = status;
646781d3 MV	436	spi_finalize_current_message(master);
	437
	438	return status;
	439	}
	440
b7969caf UKK	441	static int mxs_spi_runtime_suspend(struct device *dev)
	442	{
	443	struct spi_master *master = dev_get_drvdata(dev);
	444	struct mxs_spi *spi = spi_master_get_devdata(master);
	445	struct mxs_ssp *ssp = &spi->ssp;
	446	int ret;
	447
	448	clk_disable_unprepare(ssp->clk);
	449
	450	ret = pinctrl_pm_select_idle_state(dev);
	451	if (ret) {
	452	int ret2 = clk_prepare_enable(ssp->clk);
	453
	454	if (ret2)
	455	dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
	456	ret, ret2);
	457	}
	458
	459	return ret;
	460	}
	461
	462	static int mxs_spi_runtime_resume(struct device *dev)
	463	{
	464	struct spi_master *master = dev_get_drvdata(dev);
	465	struct mxs_spi *spi = spi_master_get_devdata(master);
	466	struct mxs_ssp *ssp = &spi->ssp;
	467	int ret;
	468
	469	ret = pinctrl_pm_select_default_state(dev);
	470	if (ret)
	471	return ret;
	472
	473	ret = clk_prepare_enable(ssp->clk);
	474	if (ret)
	475	pinctrl_pm_select_idle_state(dev);
	476
	477	return ret;
	478	}
	479
	480	static int __maybe_unused mxs_spi_suspend(struct device *dev)
	481	{
	482	struct spi_master *master = dev_get_drvdata(dev);
	483	int ret;
	484
	485	ret = spi_master_suspend(master);
	486	if (ret)
	487	return ret;
	488
	489	if (!pm_runtime_suspended(dev))
	490	return mxs_spi_runtime_suspend(dev);
	491	else
	492	return 0;
	493	}
	494
	495	static int __maybe_unused mxs_spi_resume(struct device *dev)
	496	{
	497	struct spi_master *master = dev_get_drvdata(dev);
	498	int ret;
	499
	500	if (!pm_runtime_suspended(dev))
	501	ret = mxs_spi_runtime_resume(dev);
	502	else
	503	ret = 0;
	504	if (ret)
505	return ret;
506
507	ret = spi_master_resume(master);
508	if (ret < 0 && !pm_runtime_suspended(dev))
509	mxs_spi_runtime_suspend(dev);
510
511	return ret;
512	}
513
514	static const struct dev_pm_ops mxs_spi_pm = {
515	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
516	mxs_spi_runtime_resume, NULL)
517	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
518	};
519
646781d3 MV	520	static const struct of_device_id mxs_spi_dt_ids[] = {
	521	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	522	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	523	{ /* sentinel */ }
	524	};
	525	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	526
fd4a319b	527	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	528	{
	529	const struct of_device_id *of_id =
	530	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	531	struct device_node *np = pdev->dev.of_node;
	532	struct spi_master *master;
	533	struct mxs_spi *spi;
	534	struct mxs_ssp *ssp;
646781d3 MV	535	struct clk *clk;
646781d3 MV	536	void __iomem *base;
26aafa77 SG	537	int devid, clk_freq;
26aafa77 SG	538	int ret = 0, irq_err;
646781d3	539
e64d07a2 MV	540	/*
	541	* Default clock speed for the SPI core. 160MHz seems to
	542	* work reasonably well with most SPI flashes, so use this
	543	* as a default. Override with "clock-frequency" DT prop.
	544	*/
	545	const int clk_freq_default = 160000000;
	546
474afc04	547	irq_err = platform_get_irq(pdev, 0);
796305a2	548	if (irq_err < 0)
cdd1945b	549	return irq_err;
646781d3	550
d4225b36	551	base = devm_platform_ioremap_resource(pdev, 0);
b0ee5605 TR	552	if (IS_ERR(base))
b0ee5605 TR	553	return PTR_ERR(base);
646781d3	554
646781d3 MV	555	clk = devm_clk_get(&pdev->dev, NULL);
	556	if (IS_ERR(clk))
	557	return PTR_ERR(clk);
	558
26aafa77 SG	559	devid = (enum mxs_ssp_id) of_id->data;
	560	ret = of_property_read_u32(np, "clock-frequency",
	561	&clk_freq);
	562	if (ret)
e64d07a2	563	clk_freq = clk_freq_default;
646781d3 MV	564
	565	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	566	if (!master)
	567	return -ENOMEM;
	568
b7969caf UKK	569	platform_set_drvdata(pdev, master);
b7969caf UKK	570
646781d3	571	master->transfer_one_message = mxs_spi_transfer_one;
24778be2	572	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	573	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	574	master->num_chipselect = 3;
	575	master->dev.of_node = np;
	576	master->flags = SPI_MASTER_HALF_DUPLEX;
b7969caf	577	master->auto_runtime_pm = true;
646781d3 MV	578
	579	spi = spi_master_get_devdata(master);
	580	ssp = &spi->ssp;
	581	ssp->dev = &pdev->dev;
	582	ssp->clk = clk;
	583	ssp->base = base;
	584	ssp->devid = devid;
474afc04	585
41682e03 MV	586	init_completion(&spi->c);
41682e03 MV	587
474afc04	588	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
617100c2	589	dev_name(&pdev->dev), ssp);
474afc04 MV	590	if (ret)
	591	goto out_master_free;
	592
26aafa77	593	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	594	if (!ssp->dmach) {
474afc04 MV	595	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	596	ret = -ENODEV;
474afc04 MV	597	goto out_master_free;
474afc04 MV	598	}
646781d3	599
b7969caf UKK	600	pm_runtime_enable(ssp->dev);
	601	if (!pm_runtime_enabled(ssp->dev)) {
	602	ret = mxs_spi_runtime_resume(ssp->dev);
	603	if (ret < 0) {
	604	dev_err(ssp->dev, "runtime resume failed\n");
	605	goto out_dma_release;
	606	}
	607	}
	608
	609	ret = pm_runtime_get_sync(ssp->dev);
	610	if (ret < 0) {
	611	dev_err(ssp->dev, "runtime_get_sync failed\n");
	612	goto out_pm_runtime_disable;
	613	}
9c4a39af	614
e64d07a2	615	clk_set_rate(ssp->clk, clk_freq);
646781d3	616
8498bce9 FE	617	ret = stmp_reset_block(ssp->base);
8498bce9 FE	618	if (ret)
b7969caf	619	goto out_pm_runtime_put;
646781d3	620
33e195ac	621	ret = devm_spi_register_master(&pdev->dev, master);
646781d3 MV	622	if (ret) {
646781d3 MV	623	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
b7969caf	624	goto out_pm_runtime_put;
646781d3 MV	625	}
646781d3 MV	626
b7969caf UKK	627	pm_runtime_put(ssp->dev);
b7969caf UKK	628
646781d3 MV	629	return 0;
646781d3 MV	630
b7969caf UKK	631	out_pm_runtime_put:
	632	pm_runtime_put(ssp->dev);
	633	out_pm_runtime_disable:
	634	pm_runtime_disable(ssp->dev);
9c4a39af	635	out_dma_release:
e11933f6	636	dma_release_channel(ssp->dmach);
474afc04	637	out_master_free:
646781d3 MV	638	spi_master_put(master);
	639	return ret;
	640	}
	641
fd4a319b	642	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	643	{
	644	struct spi_master *master;
	645	struct mxs_spi *spi;
	646	struct mxs_ssp *ssp;
	647
e322ce93	648	master = platform_get_drvdata(pdev);
646781d3 MV	649	spi = spi_master_get_devdata(master);
	650	ssp = &spi->ssp;
	651
b7969caf UKK	652	pm_runtime_disable(&pdev->dev);
	653	if (!pm_runtime_status_suspended(&pdev->dev))
	654	mxs_spi_runtime_suspend(&pdev->dev);
	655
e11933f6	656	dma_release_channel(ssp->dmach);
646781d3 MV	657
	658	return 0;
	659	}
	660
	661	static struct platform_driver mxs_spi_driver = {
	662	.probe = mxs_spi_probe,
fd4a319b	663	.remove = mxs_spi_remove,
646781d3 MV	664	.driver = {
646781d3 MV	665	.name = DRIVER_NAME,
646781d3	666	.of_match_table = mxs_spi_dt_ids,
b7969caf	667	.pm = &mxs_spi_pm,
646781d3 MV	668	},
	669	};
	670
	671	module_platform_driver(mxs_spi_driver);
	672
	673	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	674	MODULE_DESCRIPTION("MXS SPI master driver");
	675	MODULE_LICENSE("GPL");
	676	MODULE_ALIAS("platform:mxs-spi");