[linux-block.git] / drivers / spi / spi-mxs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Freescale MXS SPI master driver
//
// Copyright 2012 DENX Software Engineering, GmbH.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
//
// Rework and transition to new API by:
// Marek Vasut <marex@denx.de>
//
// Based on previous attempt by:
// Fabio Estevam <fabio.estevam@freescale.com>
//
// Based on code from U-Boot bootloader by:
// Marek Vasut <marex@denx.de>
//
// Based on spi-stmp.c, which is:
// Author: Dmitry Pervushin <dimka@embeddedalley.com>

#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>
#include <trace/events/spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
	unsigned int		sck;	/* Rate requested (vs actual) */
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				  const struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);

	if (hz == 0) {
		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
		return -EINVAL;
	}

	if (hz != spi->sck) {
		mxs_ssp_set_clk_rate(ssp, hz);
		/*
		 * Save requested rate, hz, rather than the actual rate,
		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
		 * when the actual rate is not quite the same as requested rate.
		 */
		spi->sck = hz;
		/*
		 * Perhaps we should return an error if the actual clock is
		 * nowhere close to what was requested?
		 */
	}

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	       ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static u32 mxs_spi_cs_to_reg(unsigned cs)
{
	u32 select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	u32 reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;

	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;

	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	u32 ctrl0;
	struct page *vm_page;
	struct {
		u32			pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	reinit_completion(&spi->c);

	/* Chip select was already programmed into CTRL0 */
	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}

			sg_init_table(&dma_xfer[sg_count].sg, 1);
			sg_set_page(&dma_xfer[sg_count].sg, vm_page,
				    min, offset_in_page(buf));
		} else {
			sg_init_one(&dma_xfer[sg_count].sg, buf, min);
		}

		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	if (!wait_for_completion_timeout(&spi->c,
					 msecs_to_jiffies(SSP_TIMEOUT))) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t;
	unsigned int flag;
	int status = 0;

	/* Program CS register bits here, it will be used for all transfers. */
	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	list_for_each_entry(t, &m->transfers, transfer_list) {

		trace_spi_transfer_start(m, t);

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi,
						t->rx_buf, t->len,
						flag);
		}

		trace_spi_transfer_stop(m, t);

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int mxs_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	clk_disable_unprepare(ssp->clk);

	ret = pinctrl_pm_select_idle_state(dev);
	if (ret) {
		int ret2 = clk_prepare_enable(ssp->clk);

		if (ret2)
			dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
				 ret, ret2);
	}

	return ret;
}

static int mxs_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	ret = pinctrl_pm_select_default_state(dev);
	if (ret)
		return ret;

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		pinctrl_pm_select_idle_state(dev);

	return ret;
}

static int __maybe_unused mxs_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	ret = spi_master_suspend(master);
	if (ret)
		return ret;

	if (!pm_runtime_suspended(dev))
		return mxs_spi_runtime_suspend(dev);
	else
		return 0;
}

static int __maybe_unused mxs_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	if (!pm_runtime_suspended(dev))
		ret = mxs_spi_runtime_resume(dev);
	else
		ret = 0;
	if (ret)
		return ret;

	ret = spi_master_resume(master);
	if (ret < 0 && !pm_runtime_suspended(dev))
		mxs_spi_runtime_suspend(dev);

	return ret;
}

static const struct dev_pm_ops mxs_spi_pm = {
	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
			   mxs_spi_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
};

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return irq_err;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	master->transfer_one_message = mxs_spi_transfer_one;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->auto_runtime_pm = true;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       dev_name(&pdev->dev), ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
	if (IS_ERR(ssp->dmach)) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = PTR_ERR(ssp->dmach);
		goto out_master_free;
	}

	pm_runtime_enable(ssp->dev);
	if (!pm_runtime_enabled(ssp->dev)) {
		ret = mxs_spi_runtime_resume(ssp->dev);
		if (ret < 0) {
			dev_err(ssp->dev, "runtime resume failed\n");
			goto out_dma_release;
		}
	}

	ret = pm_runtime_resume_and_get(ssp->dev);
	if (ret < 0) {
		dev_err(ssp->dev, "runtime_get_sync failed\n");
		goto out_pm_runtime_disable;
	}

	clk_set_rate(ssp->clk, clk_freq);

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_pm_runtime_put;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_pm_runtime_put;
	}

	pm_runtime_put(ssp->dev);

	return 0;

out_pm_runtime_put:
	pm_runtime_put(ssp->dev);
out_pm_runtime_disable:
	pm_runtime_disable(ssp->dev);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static void mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		mxs_spi_runtime_suspend(&pdev->dev);

	dma_release_channel(ssp->dmach);
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove_new = mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.of_match_table = mxs_spi_dt_ids,
		.pm = &mxs_spi_pm,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
4c23e486 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Freescale MXS SPI master driver
	4	//
	5	// Copyright 2012 DENX Software Engineering, GmbH.
	6	// Copyright 2012 Freescale Semiconductor, Inc.
	7	// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	8	//
	9	// Rework and transition to new API by:
	10	// Marek Vasut <marex@denx.de>
	11	//
	12	// Based on previous attempt by:
	13	// Fabio Estevam <fabio.estevam@freescale.com>
	14	//
	15	// Based on code from U-Boot bootloader by:
	16	// Marek Vasut <marex@denx.de>
	17	//
	18	// Based on spi-stmp.c, which is:
	19	// Author: Dmitry Pervushin <dimka@embeddedalley.com>
646781d3 MV	20
646781d3 MV	21	#include <linux/kernel.h>
646781d3 MV	22	#include <linux/ioport.h>
	23	#include <linux/of.h>
	24	#include <linux/of_device.h>
646781d3 MV	25	#include <linux/platform_device.h>
	26	#include <linux/delay.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/dma-mapping.h>
	29	#include <linux/dmaengine.h>
	30	#include <linux/highmem.h>
	31	#include <linux/clk.h>
	32	#include <linux/err.h>
	33	#include <linux/completion.h>
85dadb71	34	#include <linux/pinctrl/consumer.h>
646781d3	35	#include <linux/regulator/consumer.h>
b7969caf	36	#include <linux/pm_runtime.h>
646781d3	37	#include <linux/module.h>
646781d3 MV	38	#include <linux/stmp_device.h>
	39	#include <linux/spi/spi.h>
	40	#include <linux/spi/mxs-spi.h>
f3fdea3a	41	#include <trace/events/spi.h>
646781d3 MV	42
	43	#define DRIVER_NAME "mxs-spi"
	44
010b4818 MV	45	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	46	#define SSP_TIMEOUT 10000
646781d3	47
474afc04 MV	48	#define SG_MAXLEN 0xff00
474afc04 MV	49
28cad125 TP	50	/*
	51	* Flags for txrx functions. More efficient that using an argument register for
	52	* each one.
	53	*/
	54	#define TXRX_WRITE (1<<0) /* This is a write */
	55	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	56
646781d3 MV	57	struct mxs_spi {
646781d3 MV	58	struct mxs_ssp ssp;
474afc04	59	struct completion c;
a560943e	60	unsigned int sck; /* Rate requested (vs actual) */
646781d3 MV	61	};
	62
	63	static int mxs_spi_setup_transfer(struct spi_device *dev,
aa9e0c6f	64	const struct spi_transfer *t)
646781d3 MV	65	{
	66	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	67	struct mxs_ssp *ssp = &spi->ssp;
aa9e0c6f	68	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
646781d3	69
646781d3	70	if (hz == 0) {
aa9e0c6f	71	dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
646781d3 MV	72	return -EINVAL;
	73	}
	74
a560943e TP	75	if (hz != spi->sck) {
	76	mxs_ssp_set_clk_rate(ssp, hz);
	77	/*
	78	* Save requested rate, hz, rather than the actual rate,
a44619c3	79	* ssp->clk_rate. Otherwise we would set the rate every transfer
a560943e TP	80	* when the actual rate is not quite the same as requested rate.
	81	*/
	82	spi->sck = hz;
	83	/*
	84	* Perhaps we should return an error if the actual clock is
	85	* nowhere close to what was requested?
	86	*/
	87	}
646781d3	88
58f46e41 TP	89	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	90	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	91
646781d3 MV	92	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
aa9e0c6f TP	93	BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	94	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	95	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	96	ssp->base + HW_SSP_CTRL1(ssp));
646781d3 MV	97
	98	writel(0x0, ssp->base + HW_SSP_CMD0);
	99	writel(0x0, ssp->base + HW_SSP_CMD1);
	100
	101	return 0;
	102	}
	103
42e182f8	104	static u32 mxs_spi_cs_to_reg(unsigned cs)
646781d3	105	{
42e182f8	106	u32 select = 0;
646781d3 MV	107
	108	/*
	109	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	110	*
	111	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	112	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	113	* the datasheet for further details. In SPI mode, they are used to
	114	* toggle the chip-select lines (nCS pins).
	115	*/
	116	if (cs & 1)
	117	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	118	if (cs & 2)
	119	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	120
	121	return select;
	122	}
	123
646781d3 MV	124	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	125	{
f13639dc	126	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3	127	struct mxs_ssp *ssp = &spi->ssp;
42e182f8	128	u32 reg;
646781d3	129
f13639dc	130	do {
646781d3 MV	131	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	132
f13639dc MV	133	if (!set)
f13639dc MV	134	reg = ~reg;
646781d3	135
f13639dc	136	reg &= mask;
646781d3	137
f13639dc MV	138	if (reg == mask)
	139	return 0;
	140	} while (time_before(jiffies, timeout));
646781d3	141
f13639dc	142	return -ETIMEDOUT;
646781d3 MV	143	}
646781d3 MV	144
474afc04 MV	145	static void mxs_ssp_dma_irq_callback(void *param)
	146	{
	147	struct mxs_spi *spi = param;
a7fa3219	148
474afc04 MV	149	complete(&spi->c);
	150	}
	151
	152	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	153	{
	154	struct mxs_ssp *ssp = dev_id;
a7fa3219	155
474afc04 MV	156	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	157	__func__, __LINE__,
	158	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	159	readl(ssp->base + HW_SSP_STATUS(ssp)));
	160	return IRQ_HANDLED;
	161	}
	162
0b782f70	163	static int mxs_spi_txrx_dma(struct mxs_spi *spi,
474afc04	164	unsigned char *buf, int len,
28cad125	165	unsigned int flags)
474afc04 MV	166	{
474afc04 MV	167	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	168	struct dma_async_tx_descriptor *desc = NULL;
	169	const bool vmalloced_buf = is_vmalloc_addr(buf);
	170	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	171	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	172	int sg_count;
010b4818	173	int min, ret;
42e182f8	174	u32 ctrl0;
010b4818	175	struct page *vm_page;
010b4818	176	struct {
42e182f8	177	u32 pio[4];
010b4818 MV	178	struct scatterlist sg;
	179	} *dma_xfer;
	180
	181	if (!len)
474afc04	182	return -EINVAL;
010b4818	183
a7fa3219	184	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
010b4818 MV	185	if (!dma_xfer)
010b4818 MV	186	return -ENOMEM;
474afc04	187
16735d02	188	reinit_completion(&spi->c);
474afc04	189
0b782f70	190	/* Chip select was already programmed into CTRL0 */
010b4818	191	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	192	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	193	BM_SSP_CTRL0_READ);
0b782f70	194	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER;
010b4818	195
28cad125	196	if (!(flags & TXRX_WRITE))
010b4818	197	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	198
474afc04 MV	199	/* Queue the DMA data transfer. */
010b4818	200	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	201	/* Prepare the transfer descriptor. */
010b4818 MV	202	min = min(len, desc_len);
010b4818 MV	203
28cad125 TP	204	/*
	205	* De-assert CS on last segment if flag is set (i.e., no more
	206	* transfers will follow)
	207	*/
	208	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	209	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	210
ba486a2a JL	211	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	212	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	213	ctrl0 \|= min;
ba486a2a	214	}
010b4818 MV	215
	216	dma_xfer[sg_count].pio[0] = ctrl0;
	217	dma_xfer[sg_count].pio[3] = min;
	218
	219	if (vmalloced_buf) {
	220	vm_page = vmalloc_to_page(buf);
	221	if (!vm_page) {
	222	ret = -ENOMEM;
	223	goto err_vmalloc;
	224	}
9e8987ac CK	225
	226	sg_init_table(&dma_xfer[sg_count].sg, 1);
	227	sg_set_page(&dma_xfer[sg_count].sg, vm_page,
	228	min, offset_in_page(buf));
010b4818	229	} else {
9e8987ac	230	sg_init_one(&dma_xfer[sg_count].sg, buf, min);
010b4818 MV	231	}
010b4818 MV	232
010b4818	233	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	234	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	235
	236	len -= min;
	237	buf += min;
	238
	239	/* Queue the PIO register write transfer. */
	240	desc = dmaengine_prep_slave_sg(ssp->dmach,
	241	(struct scatterlist *)dma_xfer[sg_count].pio,
	242	(ssp->devid == IMX23_SSP) ? 1 : 4,
	243	DMA_TRANS_NONE,
	244	sg_count ? DMA_PREP_INTERRUPT : 0);
	245	if (!desc) {
	246	dev_err(ssp->dev,
	247	"Failed to get PIO reg. write descriptor.\n");
	248	ret = -EINVAL;
	249	goto err_mapped;
	250	}
	251
	252	desc = dmaengine_prep_slave_sg(ssp->dmach,
	253	&dma_xfer[sg_count].sg, 1,
28cad125	254	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	255	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	256
	257	if (!desc) {
	258	dev_err(ssp->dev,
	259	"Failed to get DMA data write descriptor.\n");
	260	ret = -EINVAL;
	261	goto err_mapped;
	262	}
474afc04 MV	263	}
	264
	265	/*
	266	* The last descriptor must have this callback,
	267	* to finish the DMA transaction.
	268	*/
	269	desc->callback = mxs_ssp_dma_irq_callback;
	270	desc->callback_param = spi;
	271
	272	/* Start the transfer. */
	273	dmaengine_submit(desc);
	274	dma_async_issue_pending(ssp->dmach);
	275
f2234691 NMG	276	if (!wait_for_completion_timeout(&spi->c,
f2234691 NMG	277	msecs_to_jiffies(SSP_TIMEOUT))) {
474afc04 MV	278	dev_err(ssp->dev, "DMA transfer timeout\n");
474afc04 MV	279	ret = -ETIMEDOUT;
44968466	280	dmaengine_terminate_all(ssp->dmach);
010b4818	281	goto err_vmalloc;
474afc04 MV	282	}
	283
	284	ret = 0;
	285
010b4818 MV	286	err_vmalloc:
	287	while (--sg_count >= 0) {
	288	err_mapped:
	289	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	290	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	291	}
474afc04 MV	292
010b4818 MV	293	kfree(dma_xfer);
010b4818 MV	294
474afc04 MV	295	return ret;
	296	}
	297
0b782f70	298	static int mxs_spi_txrx_pio(struct mxs_spi *spi,
646781d3	299	unsigned char *buf, int len,
28cad125	300	unsigned int flags)
646781d3 MV	301	{
	302	struct mxs_ssp *ssp = &spi->ssp;
	303
75e73fa2 TP	304	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	305	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	306
646781d3 MV	307	while (len--) {
28cad125	308	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	309	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	310	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	311
	312	if (ssp->devid == IMX23_SSP) {
	313	writel(BM_SSP_CTRL0_XFER_COUNT,
	314	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	315	writel(1,
	316	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	317	} else {
	318	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	319	}
	320
28cad125	321	if (flags & TXRX_WRITE)
646781d3 MV	322	writel(BM_SSP_CTRL0_READ,
	323	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	324	else
	325	writel(BM_SSP_CTRL0_READ,
	326	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	327
	328	writel(BM_SSP_CTRL0_RUN,
	329	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	330
	331	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	332	return -ETIMEDOUT;
	333
28cad125	334	if (flags & TXRX_WRITE)
646781d3 MV	335	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	336
	337	writel(BM_SSP_CTRL0_DATA_XFER,
	338	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	339
28cad125	340	if (!(flags & TXRX_WRITE)) {
646781d3 MV	341	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	342	BM_SSP_STATUS_FIFO_EMPTY, 0))
	343	return -ETIMEDOUT;
	344
	345	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	346	}
	347
	348	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	349	return -ETIMEDOUT;
	350
	351	buf++;
	352	}
	353
	354	if (len <= 0)
	355	return 0;
	356
	357	return -ETIMEDOUT;
	358	}
	359
	360	static int mxs_spi_transfer_one(struct spi_master *master,
	361	struct spi_message *m)
	362	{
	363	struct mxs_spi *spi = spi_master_get_devdata(master);
	364	struct mxs_ssp *ssp = &spi->ssp;
9a7da6cc	365	struct spi_transfer *t;
28cad125	366	unsigned int flag;
646781d3	367	int status = 0;
646781d3	368
0b782f70 TP	369	/* Program CS register bits here, it will be used for all transfers. */
	370	writel(BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ,
	371	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
9e264f3f	372	writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
0b782f70	373	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3	374
9a7da6cc	375	list_for_each_entry(t, &m->transfers, transfer_list) {
646781d3	376
f3fdea3a UKK	377	trace_spi_transfer_start(m, t);
f3fdea3a UKK	378
646781d3 MV	379	status = mxs_spi_setup_transfer(m->spi, t);
	380	if (status)
	381	break;
	382
28cad125 TP	383	/* De-assert on last transfer, inverted by cs_change flag */
	384	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	385	TXRX_DEASSERT_CS : 0;
646781d3	386
474afc04 MV	387	/*
	388	* Small blocks can be transfered via PIO.
	389	* Measured by empiric means:
	390	*
	391	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	392	*
	393	* DMA only: 2.164808 seconds, 473.0KB/s
	394	* Combined: 1.676276 seconds, 610.9KB/s
	395	*/
727c10e3	396	if (t->len < 32) {
474afc04 MV	397	writel(BM_SSP_CTRL1_DMA_ENABLE,
	398	ssp->base + HW_SSP_CTRL1(ssp) +
	399	STMP_OFFSET_REG_CLR);
	400
	401	if (t->tx_buf)
0b782f70	402	status = mxs_spi_txrx_pio(spi,
474afc04	403	(void *)t->tx_buf,
28cad125	404	t->len, flag \| TXRX_WRITE);
474afc04	405	if (t->rx_buf)
0b782f70	406	status = mxs_spi_txrx_pio(spi,
474afc04	407	t->rx_buf, t->len,
28cad125	408	flag);
474afc04 MV	409	} else {
	410	writel(BM_SSP_CTRL1_DMA_ENABLE,
	411	ssp->base + HW_SSP_CTRL1(ssp) +
	412	STMP_OFFSET_REG_SET);
	413
	414	if (t->tx_buf)
0b782f70	415	status = mxs_spi_txrx_dma(spi,
474afc04	416	(void *)t->tx_buf, t->len,
28cad125	417	flag \| TXRX_WRITE);
474afc04	418	if (t->rx_buf)
0b782f70	419	status = mxs_spi_txrx_dma(spi,
474afc04	420	t->rx_buf, t->len,
28cad125	421	flag);
474afc04	422	}
646781d3	423
f3fdea3a UKK	424	trace_spi_transfer_stop(m, t);
f3fdea3a UKK	425
c895db0f MV	426	if (status) {
c895db0f MV	427	stmp_reset_block(ssp->base);
646781d3	428	break;
c895db0f	429	}
646781d3	430
204e706f	431	m->actual_length += t->len;
646781d3 MV	432	}
646781d3 MV	433
d856f1eb	434	m->status = status;
646781d3 MV	435	spi_finalize_current_message(master);
	436
	437	return status;
	438	}
	439
b7969caf UKK	440	static int mxs_spi_runtime_suspend(struct device *dev)
	441	{
	442	struct spi_master *master = dev_get_drvdata(dev);
	443	struct mxs_spi *spi = spi_master_get_devdata(master);
	444	struct mxs_ssp *ssp = &spi->ssp;
	445	int ret;
	446
	447	clk_disable_unprepare(ssp->clk);
	448
	449	ret = pinctrl_pm_select_idle_state(dev);
	450	if (ret) {
	451	int ret2 = clk_prepare_enable(ssp->clk);
	452
	453	if (ret2)
	454	dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
	455	ret, ret2);
	456	}
	457
	458	return ret;
	459	}
	460
	461	static int mxs_spi_runtime_resume(struct device *dev)
	462	{
	463	struct spi_master *master = dev_get_drvdata(dev);
	464	struct mxs_spi *spi = spi_master_get_devdata(master);
	465	struct mxs_ssp *ssp = &spi->ssp;
	466	int ret;
	467
	468	ret = pinctrl_pm_select_default_state(dev);
	469	if (ret)
	470	return ret;
	471
	472	ret = clk_prepare_enable(ssp->clk);
	473	if (ret)
	474	pinctrl_pm_select_idle_state(dev);
	475
	476	return ret;
	477	}
	478
	479	static int __maybe_unused mxs_spi_suspend(struct device *dev)
	480	{
	481	struct spi_master *master = dev_get_drvdata(dev);
	482	int ret;
	483
	484	ret = spi_master_suspend(master);
	485	if (ret)
	486	return ret;
	487
	488	if (!pm_runtime_suspended(dev))
	489	return mxs_spi_runtime_suspend(dev);
	490	else
	491	return 0;
	492	}
	493
	494	static int __maybe_unused mxs_spi_resume(struct device *dev)
	495	{
	496	struct spi_master *master = dev_get_drvdata(dev);
	497	int ret;
	498
	499	if (!pm_runtime_suspended(dev))
	500	ret = mxs_spi_runtime_resume(dev);
	501	else
	502	ret = 0;
	503	if (ret)
504	return ret;
505
506	ret = spi_master_resume(master);
507	if (ret < 0 && !pm_runtime_suspended(dev))
508	mxs_spi_runtime_suspend(dev);
509
510	return ret;
511	}
512
513	static const struct dev_pm_ops mxs_spi_pm = {
514	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
515	mxs_spi_runtime_resume, NULL)
516	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
517	};
518
646781d3 MV	519	static const struct of_device_id mxs_spi_dt_ids[] = {
	520	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	521	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	522	{ /* sentinel */ }
	523	};
	524	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	525
fd4a319b	526	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	527	{
	528	const struct of_device_id *of_id =
	529	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	530	struct device_node *np = pdev->dev.of_node;
	531	struct spi_master *master;
	532	struct mxs_spi *spi;
	533	struct mxs_ssp *ssp;
646781d3 MV	534	struct clk *clk;
646781d3 MV	535	void __iomem *base;
26aafa77 SG	536	int devid, clk_freq;
26aafa77 SG	537	int ret = 0, irq_err;
646781d3	538
e64d07a2 MV	539	/*
	540	* Default clock speed for the SPI core. 160MHz seems to
	541	* work reasonably well with most SPI flashes, so use this
	542	* as a default. Override with "clock-frequency" DT prop.
	543	*/
	544	const int clk_freq_default = 160000000;
	545
474afc04	546	irq_err = platform_get_irq(pdev, 0);
796305a2	547	if (irq_err < 0)
cdd1945b	548	return irq_err;
646781d3	549
d4225b36	550	base = devm_platform_ioremap_resource(pdev, 0);
b0ee5605 TR	551	if (IS_ERR(base))
b0ee5605 TR	552	return PTR_ERR(base);
646781d3	553
646781d3 MV	554	clk = devm_clk_get(&pdev->dev, NULL);
	555	if (IS_ERR(clk))
	556	return PTR_ERR(clk);
	557
26aafa77 SG	558	devid = (enum mxs_ssp_id) of_id->data;
	559	ret = of_property_read_u32(np, "clock-frequency",
	560	&clk_freq);
	561	if (ret)
e64d07a2	562	clk_freq = clk_freq_default;
646781d3 MV	563
	564	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	565	if (!master)
	566	return -ENOMEM;
	567
b7969caf UKK	568	platform_set_drvdata(pdev, master);
b7969caf UKK	569
646781d3	570	master->transfer_one_message = mxs_spi_transfer_one;
24778be2	571	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	572	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	573	master->num_chipselect = 3;
	574	master->dev.of_node = np;
	575	master->flags = SPI_MASTER_HALF_DUPLEX;
b7969caf	576	master->auto_runtime_pm = true;
646781d3 MV	577
	578	spi = spi_master_get_devdata(master);
	579	ssp = &spi->ssp;
	580	ssp->dev = &pdev->dev;
	581	ssp->clk = clk;
	582	ssp->base = base;
	583	ssp->devid = devid;
474afc04	584
41682e03 MV	585	init_completion(&spi->c);
41682e03 MV	586
474afc04	587	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
617100c2	588	dev_name(&pdev->dev), ssp);
474afc04 MV	589	if (ret)
	590	goto out_master_free;
	591
7ccffd41 PU	592	ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
7ccffd41 PU	593	if (IS_ERR(ssp->dmach)) {
474afc04	594	dev_err(ssp->dev, "Failed to request DMA\n");
7ccffd41	595	ret = PTR_ERR(ssp->dmach);
474afc04 MV	596	goto out_master_free;
474afc04 MV	597	}
646781d3	598
b7969caf UKK	599	pm_runtime_enable(ssp->dev);
	600	if (!pm_runtime_enabled(ssp->dev)) {
	601	ret = mxs_spi_runtime_resume(ssp->dev);
	602	if (ret < 0) {
	603	dev_err(ssp->dev, "runtime resume failed\n");
	604	goto out_dma_release;
	605	}
	606	}
	607
32831bf5	608	ret = pm_runtime_resume_and_get(ssp->dev);
b7969caf UKK	609	if (ret < 0) {
	610	dev_err(ssp->dev, "runtime_get_sync failed\n");
	611	goto out_pm_runtime_disable;
	612	}
9c4a39af	613
e64d07a2	614	clk_set_rate(ssp->clk, clk_freq);
646781d3	615
8498bce9 FE	616	ret = stmp_reset_block(ssp->base);
8498bce9 FE	617	if (ret)
b7969caf	618	goto out_pm_runtime_put;
646781d3	619
33e195ac	620	ret = devm_spi_register_master(&pdev->dev, master);
646781d3 MV	621	if (ret) {
646781d3 MV	622	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
b7969caf	623	goto out_pm_runtime_put;
646781d3 MV	624	}
646781d3 MV	625
b7969caf UKK	626	pm_runtime_put(ssp->dev);
b7969caf UKK	627
646781d3 MV	628	return 0;
646781d3 MV	629
b7969caf UKK	630	out_pm_runtime_put:
	631	pm_runtime_put(ssp->dev);
	632	out_pm_runtime_disable:
	633	pm_runtime_disable(ssp->dev);
9c4a39af	634	out_dma_release:
e11933f6	635	dma_release_channel(ssp->dmach);
474afc04	636	out_master_free:
646781d3 MV	637	spi_master_put(master);
	638	return ret;
	639	}
	640
a760db09	641	static void mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	642	{
	643	struct spi_master *master;
	644	struct mxs_spi *spi;
	645	struct mxs_ssp *ssp;
	646
e322ce93	647	master = platform_get_drvdata(pdev);
646781d3 MV	648	spi = spi_master_get_devdata(master);
	649	ssp = &spi->ssp;
	650
b7969caf UKK	651	pm_runtime_disable(&pdev->dev);
	652	if (!pm_runtime_status_suspended(&pdev->dev))
	653	mxs_spi_runtime_suspend(&pdev->dev);
	654
e11933f6	655	dma_release_channel(ssp->dmach);
646781d3 MV	656	}
	657
	658	static struct platform_driver mxs_spi_driver = {
	659	.probe = mxs_spi_probe,
a760db09	660	.remove_new = mxs_spi_remove,
646781d3 MV	661	.driver = {
646781d3 MV	662	.name = DRIVER_NAME,
646781d3	663	.of_match_table = mxs_spi_dt_ids,
b7969caf	664	.pm = &mxs_spi_pm,
646781d3 MV	665	},
	666	};
	667
	668	module_platform_driver(mxs_spi_driver);
	669
	670	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	671	MODULE_DESCRIPTION("MXS SPI master driver");
	672	MODULE_LICENSE("GPL");
	673	MODULE_ALIAS("platform:mxs-spi");