[linux-2.6-block.git] / drivers / spi / spi-mxic.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2018 Macronix International Co., Ltd.
//
// Authors:
//	Mason Yang <masonccyang@mxic.com.tw>
//	zhengxunli <zhengxunli@mxic.com.tw>
//	Boris Brezillon <boris.brezillon@bootlin.com>
//

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>

#define HC_CFG			0x0
#define HC_CFG_IF_CFG(x)	((x) << 27)
#define HC_CFG_DUAL_SLAVE	BIT(31)
#define HC_CFG_INDIVIDUAL	BIT(30)
#define HC_CFG_NIO(x)		(((x) / 4) << 27)
#define HC_CFG_TYPE(s, t)	((t) << (23 + ((s) * 2)))
#define HC_CFG_TYPE_SPI_NOR	0
#define HC_CFG_TYPE_SPI_NAND	1
#define HC_CFG_TYPE_SPI_RAM	2
#define HC_CFG_TYPE_RAW_NAND	3
#define HC_CFG_SLV_ACT(x)	((x) << 21)
#define HC_CFG_CLK_PH_EN	BIT(20)
#define HC_CFG_CLK_POL_INV	BIT(19)
#define HC_CFG_BIG_ENDIAN	BIT(18)
#define HC_CFG_DATA_PASS	BIT(17)
#define HC_CFG_IDLE_SIO_LVL(x)	((x) << 16)
#define HC_CFG_MAN_START_EN	BIT(3)
#define HC_CFG_MAN_START	BIT(2)
#define HC_CFG_MAN_CS_EN	BIT(1)
#define HC_CFG_MAN_CS_ASSERT	BIT(0)

#define INT_STS			0x4
#define INT_STS_EN		0x8
#define INT_SIG_EN		0xc
#define INT_STS_ALL		GENMASK(31, 0)
#define INT_RDY_PIN		BIT(26)
#define INT_RDY_SR		BIT(25)
#define INT_LNR_SUSP		BIT(24)
#define INT_ECC_ERR		BIT(17)
#define INT_CRC_ERR		BIT(16)
#define INT_LWR_DIS		BIT(12)
#define INT_LRD_DIS		BIT(11)
#define INT_SDMA_INT		BIT(10)
#define INT_DMA_FINISH		BIT(9)
#define INT_RX_NOT_FULL		BIT(3)
#define INT_RX_NOT_EMPTY	BIT(2)
#define INT_TX_NOT_FULL		BIT(1)
#define INT_TX_EMPTY		BIT(0)

#define HC_EN			0x10
#define HC_EN_BIT		BIT(0)

#define TXD(x)			(0x14 + ((x) * 4))
#define RXD			0x24

#define SS_CTRL(s)		(0x30 + ((s) * 4))
#define LRD_CFG			0x44
#define LWR_CFG			0x80
#define RWW_CFG			0x70
#define OP_READ			BIT(23)
#define OP_DUMMY_CYC(x)		((x) << 17)
#define OP_ADDR_BYTES(x)	((x) << 14)
#define OP_CMD_BYTES(x)		(((x) - 1) << 13)
#define OP_OCTA_CRC_EN		BIT(12)
#define OP_DQS_EN		BIT(11)
#define OP_ENHC_EN		BIT(10)
#define OP_PREAMBLE_EN		BIT(9)
#define OP_DATA_DDR		BIT(8)
#define OP_DATA_BUSW(x)		((x) << 6)
#define OP_ADDR_DDR		BIT(5)
#define OP_ADDR_BUSW(x)		((x) << 3)
#define OP_CMD_DDR		BIT(2)
#define OP_CMD_BUSW(x)		(x)
#define OP_BUSW_1		0
#define OP_BUSW_2		1
#define OP_BUSW_4		2
#define OP_BUSW_8		3

#define OCTA_CRC		0x38
#define OCTA_CRC_IN_EN(s)	BIT(3 + ((s) * 16))
#define OCTA_CRC_CHUNK(s, x)	((fls((x) / 32)) << (1 + ((s) * 16)))
#define OCTA_CRC_OUT_EN(s)	BIT(0 + ((s) * 16))

#define ONFI_DIN_CNT(s)		(0x3c + (s))

#define LRD_CTRL		0x48
#define RWW_CTRL		0x74
#define LWR_CTRL		0x84
#define LMODE_EN		BIT(31)
#define LMODE_SLV_ACT(x)	((x) << 21)
#define LMODE_CMD1(x)		((x) << 8)
#define LMODE_CMD0(x)		(x)

#define LRD_ADDR		0x4c
#define LWR_ADDR		0x88
#define LRD_RANGE		0x50
#define LWR_RANGE		0x8c

#define AXI_SLV_ADDR		0x54

#define DMAC_RD_CFG		0x58
#define DMAC_WR_CFG		0x94
#define DMAC_CFG_PERIPH_EN	BIT(31)
#define DMAC_CFG_ALLFLUSH_EN	BIT(30)
#define DMAC_CFG_LASTFLUSH_EN	BIT(29)
#define DMAC_CFG_QE(x)		(((x) + 1) << 16)
#define DMAC_CFG_BURST_LEN(x)	(((x) + 1) << 12)
#define DMAC_CFG_BURST_SZ(x)	((x) << 8)
#define DMAC_CFG_DIR_READ	BIT(1)
#define DMAC_CFG_START		BIT(0)

#define DMAC_RD_CNT		0x5c
#define DMAC_WR_CNT		0x98

#define SDMA_ADDR		0x60

#define DMAM_CFG		0x64
#define DMAM_CFG_START		BIT(31)
#define DMAM_CFG_CONT		BIT(30)
#define DMAM_CFG_SDMA_GAP(x)	(fls((x) / 8192) << 2)
#define DMAM_CFG_DIR_READ	BIT(1)
#define DMAM_CFG_EN		BIT(0)

#define DMAM_CNT		0x68

#define LNR_TIMER_TH		0x6c

#define RDM_CFG0		0x78
#define RDM_CFG0_POLY(x)	(x)

#define RDM_CFG1		0x7c
#define RDM_CFG1_RDM_EN		BIT(31)
#define RDM_CFG1_SEED(x)	(x)

#define LWR_SUSP_CTRL		0x90
#define LWR_SUSP_CTRL_EN	BIT(31)

#define DMAS_CTRL		0x9c
#define DMAS_CTRL_EN		BIT(31)
#define DMAS_CTRL_DIR_READ	BIT(30)

#define DATA_STROB		0xa0
#define DATA_STROB_EDO_EN	BIT(2)
#define DATA_STROB_INV_POL	BIT(1)
#define DATA_STROB_DELAY_2CYC	BIT(0)

#define IDLY_CODE(x)		(0xa4 + ((x) * 4))
#define IDLY_CODE_VAL(x, v)	((v) << (((x) % 4) * 8))

#define GPIO			0xc4
#define GPIO_PT(x)		BIT(3 + ((x) * 16))
#define GPIO_RESET(x)		BIT(2 + ((x) * 16))
#define GPIO_HOLDB(x)		BIT(1 + ((x) * 16))
#define GPIO_WPB(x)		BIT((x) * 16)

#define HC_VER			0xd0

#define HW_TEST(x)		(0xe0 + ((x) * 4))

struct mxic_spi {
	struct clk *ps_clk;
	struct clk *send_clk;
	struct clk *send_dly_clk;
	void __iomem *regs;
	u32 cur_speed_hz;
};

static int mxic_spi_clk_enable(struct mxic_spi *mxic)
{
	int ret;

	ret = clk_prepare_enable(mxic->send_clk);
	if (ret)
		return ret;

	ret = clk_prepare_enable(mxic->send_dly_clk);
	if (ret)
		goto err_send_dly_clk;

	return ret;

err_send_dly_clk:
	clk_disable_unprepare(mxic->send_clk);

	return ret;
}

static void mxic_spi_clk_disable(struct mxic_spi *mxic)
{
	clk_disable_unprepare(mxic->send_clk);
	clk_disable_unprepare(mxic->send_dly_clk);
}

static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
{
	writel(IDLY_CODE_VAL(0, idly_code) |
	       IDLY_CODE_VAL(1, idly_code) |
	       IDLY_CODE_VAL(2, idly_code) |
	       IDLY_CODE_VAL(3, idly_code),
	       mxic->regs + IDLY_CODE(0));
	writel(IDLY_CODE_VAL(4, idly_code) |
	       IDLY_CODE_VAL(5, idly_code) |
	       IDLY_CODE_VAL(6, idly_code) |
	       IDLY_CODE_VAL(7, idly_code),
	       mxic->regs + IDLY_CODE(1));
}

static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
{
	int ret;

	ret = clk_set_rate(mxic->send_clk, freq);
	if (ret)
		return ret;

	ret = clk_set_rate(mxic->send_dly_clk, freq);
	if (ret)
		return ret;

	/*
	 * A constant delay range from 0x0 ~ 0x1F for input delay,
	 * the unit is 78 ps, the max input delay is 2.418 ns.
	 */
	mxic_spi_set_input_delay_dqs(mxic, 0xf);

	/*
	 * Phase degree = 360 * freq * output-delay
	 * where output-delay is a constant value 1 ns in FPGA.
	 *
	 * Get Phase degree = 360 * freq * 1 ns
	 *                  = 360 * freq * 1 sec / 1000000000
	 *                  = 9 * freq / 25000000
	 */
	ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
	if (ret)
		return ret;

	return 0;
}

static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
{
	int ret;

	if (mxic->cur_speed_hz == freq)
		return 0;

	mxic_spi_clk_disable(mxic);
	ret = mxic_spi_clk_setup(mxic, freq);
	if (ret)
		return ret;

	ret = mxic_spi_clk_enable(mxic);
	if (ret)
		return ret;

	mxic->cur_speed_hz = freq;

	return 0;
}

static void mxic_spi_hw_init(struct mxic_spi *mxic)
{
	writel(0, mxic->regs + DATA_STROB);
	writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
	writel(0, mxic->regs + HC_EN);
	writel(0, mxic->regs + LRD_CFG);
	writel(0, mxic->regs + LRD_CTRL);
	writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
	       HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
	       mxic->regs + HC_CFG);
}

static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
			      void *rxbuf, unsigned int len)
{
	unsigned int pos = 0;

	while (pos < len) {
		unsigned int nbytes = len - pos;
		u32 data = 0xffffffff;
		u32 sts;
		int ret;

		if (nbytes > 4)
			nbytes = 4;

		if (txbuf)
			memcpy(&data, txbuf + pos, nbytes);

		ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
					 sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
		if (ret)
			return ret;

		writel(data, mxic->regs + TXD(nbytes % 4));

		if (rxbuf) {
			ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
						 sts & INT_TX_EMPTY, 0,
						 USEC_PER_SEC);
			if (ret)
				return ret;

			ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
						 sts & INT_RX_NOT_EMPTY, 0,
						 USEC_PER_SEC);
			if (ret)
				return ret;

			data = readl(mxic->regs + RXD);
			data >>= (8 * (4 - nbytes));
			memcpy(rxbuf + pos, &data, nbytes);
			WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
		} else {
			readl(mxic->regs + RXD);
		}
		WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);

		pos += nbytes;
	}

	return 0;
}

static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
				     const struct spi_mem_op *op)
{
	bool all_false;

	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
		return false;

	if (op->data.nbytes && op->dummy.nbytes &&
	    op->data.buswidth != op->dummy.buswidth)
		return false;

	if (op->addr.nbytes > 7)
		return false;

	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
		    !op->data.dtr;

	if (all_false)
		return spi_mem_default_supports_op(mem, op);
	else
		return spi_mem_dtr_supports_op(mem, op);
}

static int mxic_spi_mem_exec_op(struct spi_mem *mem,
				const struct spi_mem_op *op)
{
	struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
	int nio = 1, i, ret;
	u32 ss_ctrl;
	u8 addr[8], cmd[2];

	ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
	if (ret)
		return ret;

	if (mem->spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
		nio = 8;
	else if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
		nio = 4;
	else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
		nio = 2;

	writel(HC_CFG_NIO(nio) |
	       HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
	       HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
	       HC_CFG_MAN_CS_EN,
	       mxic->regs + HC_CFG);
	writel(HC_EN_BIT, mxic->regs + HC_EN);

	ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) |
		  OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
		  (op->cmd.dtr ? OP_CMD_DDR : 0);

	if (op->addr.nbytes)
		ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
			   OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
			   (op->addr.dtr ? OP_ADDR_DDR : 0);

	if (op->dummy.nbytes)
		ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);

	if (op->data.nbytes) {
		ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
			   (op->data.dtr ? OP_DATA_DDR : 0);
		if (op->data.dir == SPI_MEM_DATA_IN) {
			ss_ctrl |= OP_READ;
			if (op->data.dtr)
				ss_ctrl |= OP_DQS_EN;
		}
	}

	writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));

	writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
	       mxic->regs + HC_CFG);

	for (i = 0; i < op->cmd.nbytes; i++)
		cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1));

	ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
	if (ret)
		goto out;

	for (i = 0; i < op->addr.nbytes; i++)
		addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));

	ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
	if (ret)
		goto out;

	ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
	if (ret)
		goto out;

	ret = mxic_spi_data_xfer(mxic,
				 op->data.dir == SPI_MEM_DATA_OUT ?
				 op->data.buf.out : NULL,
				 op->data.dir == SPI_MEM_DATA_IN ?
				 op->data.buf.in : NULL,
				 op->data.nbytes);

out:
	writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
	       mxic->regs + HC_CFG);
	writel(0, mxic->regs + HC_EN);

	return ret;
}

static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
	.supports_op = mxic_spi_mem_supports_op,
	.exec_op = mxic_spi_mem_exec_op,
};

static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
{
	struct mxic_spi *mxic = spi_master_get_devdata(spi->master);

	if (!lvl) {
		writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
		       mxic->regs + HC_CFG);
		writel(HC_EN_BIT, mxic->regs + HC_EN);
		writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
		       mxic->regs + HC_CFG);
	} else {
		writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
		       mxic->regs + HC_CFG);
		writel(0, mxic->regs + HC_EN);
	}
}

static int mxic_spi_transfer_one(struct spi_master *master,
				 struct spi_device *spi,
				 struct spi_transfer *t)
{
	struct mxic_spi *mxic = spi_master_get_devdata(master);
	unsigned int busw = OP_BUSW_1;
	int ret;

	if (t->rx_buf && t->tx_buf) {
		if (((spi->mode & SPI_TX_QUAD) &&
		     !(spi->mode & SPI_RX_QUAD)) ||
		    ((spi->mode & SPI_TX_DUAL) &&
		     !(spi->mode & SPI_RX_DUAL)))
			return -ENOTSUPP;
	}

	ret = mxic_spi_set_freq(mxic, t->speed_hz);
	if (ret)
		return ret;

	if (t->tx_buf) {
		if (spi->mode & SPI_TX_QUAD)
			busw = OP_BUSW_4;
		else if (spi->mode & SPI_TX_DUAL)
			busw = OP_BUSW_2;
	} else if (t->rx_buf) {
		if (spi->mode & SPI_RX_QUAD)
			busw = OP_BUSW_4;
		else if (spi->mode & SPI_RX_DUAL)
			busw = OP_BUSW_2;
	}

	writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
	       OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),
	       mxic->regs + SS_CTRL(0));

	ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
	if (ret)
		return ret;

	spi_finalize_current_transfer(master);

	return 0;
}

static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxic_spi *mxic = spi_master_get_devdata(master);

	mxic_spi_clk_disable(mxic);
	clk_disable_unprepare(mxic->ps_clk);

	return 0;
}

static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxic_spi *mxic = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(mxic->ps_clk);
	if (ret) {
		dev_err(dev, "Cannot enable ps_clock.\n");
		return ret;
	}

	return mxic_spi_clk_enable(mxic);
}

static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
	SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
			   mxic_spi_runtime_resume, NULL)
};

static int mxic_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct resource *res;
	struct mxic_spi *mxic;
	int ret;

	master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	mxic = spi_master_get_devdata(master);

	master->dev.of_node = pdev->dev.of_node;

	mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
	if (IS_ERR(mxic->ps_clk))
		return PTR_ERR(mxic->ps_clk);

	mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
	if (IS_ERR(mxic->send_clk))
		return PTR_ERR(mxic->send_clk);

	mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
	if (IS_ERR(mxic->send_dly_clk))
		return PTR_ERR(mxic->send_dly_clk);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	mxic->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mxic->regs))
		return PTR_ERR(mxic->regs);

	pm_runtime_enable(&pdev->dev);
	master->auto_runtime_pm = true;

	master->num_chipselect = 1;
	master->mem_ops = &mxic_spi_mem_ops;

	master->set_cs = mxic_spi_set_cs;
	master->transfer_one = mxic_spi_transfer_one;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA |
			SPI_RX_DUAL | SPI_TX_DUAL |
			SPI_RX_QUAD | SPI_TX_QUAD |
			SPI_RX_OCTAL | SPI_TX_OCTAL;

	mxic_spi_hw_init(mxic);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "spi_register_master failed\n");
		pm_runtime_disable(&pdev->dev);
	}

	return ret;
}

static int mxic_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	spi_unregister_master(master);

	return 0;
}

static const struct of_device_id mxic_spi_of_ids[] = {
	{ .compatible = "mxicy,mx25f0a-spi", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);

static struct platform_driver mxic_spi_driver = {
	.probe = mxic_spi_probe,
	.remove = mxic_spi_remove,
	.driver = {
		.name = "mxic-spi",
		.of_match_table = mxic_spi_of_ids,
		.pm = &mxic_spi_dev_pm_ops,
	},
};
module_platform_driver(mxic_spi_driver);

MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
MODULE_DESCRIPTION("MX25F0A SPI controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
b942d80b MY	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (C) 2018 Macronix International Co., Ltd.
	4	//
	5	// Authors:
	6	// Mason Yang <masonccyang@mxic.com.tw>
	7	// zhengxunli <zhengxunli@mxic.com.tw>
	8	// Boris Brezillon <boris.brezillon@bootlin.com>
	9	//
	10
	11	#include <linux/clk.h>
	12	#include <linux/io.h>
	13	#include <linux/iopoll.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pm_runtime.h>
	17	#include <linux/spi/spi.h>
	18	#include <linux/spi/spi-mem.h>
	19
	20	#define HC_CFG 0x0
	21	#define HC_CFG_IF_CFG(x) ((x) << 27)
	22	#define HC_CFG_DUAL_SLAVE BIT(31)
	23	#define HC_CFG_INDIVIDUAL BIT(30)
	24	#define HC_CFG_NIO(x) (((x) / 4) << 27)
	25	#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
	26	#define HC_CFG_TYPE_SPI_NOR 0
	27	#define HC_CFG_TYPE_SPI_NAND 1
	28	#define HC_CFG_TYPE_SPI_RAM 2
	29	#define HC_CFG_TYPE_RAW_NAND 3
	30	#define HC_CFG_SLV_ACT(x) ((x) << 21)
	31	#define HC_CFG_CLK_PH_EN BIT(20)
	32	#define HC_CFG_CLK_POL_INV BIT(19)
	33	#define HC_CFG_BIG_ENDIAN BIT(18)
	34	#define HC_CFG_DATA_PASS BIT(17)
	35	#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
	36	#define HC_CFG_MAN_START_EN BIT(3)
	37	#define HC_CFG_MAN_START BIT(2)
	38	#define HC_CFG_MAN_CS_EN BIT(1)
	39	#define HC_CFG_MAN_CS_ASSERT BIT(0)
	40
	41	#define INT_STS 0x4
	42	#define INT_STS_EN 0x8
	43	#define INT_SIG_EN 0xc
	44	#define INT_STS_ALL GENMASK(31, 0)
	45	#define INT_RDY_PIN BIT(26)
	46	#define INT_RDY_SR BIT(25)
	47	#define INT_LNR_SUSP BIT(24)
	48	#define INT_ECC_ERR BIT(17)
	49	#define INT_CRC_ERR BIT(16)
	50	#define INT_LWR_DIS BIT(12)
	51	#define INT_LRD_DIS BIT(11)
	52	#define INT_SDMA_INT BIT(10)
	53	#define INT_DMA_FINISH BIT(9)
	54	#define INT_RX_NOT_FULL BIT(3)
	55	#define INT_RX_NOT_EMPTY BIT(2)
	56	#define INT_TX_NOT_FULL BIT(1)
	57	#define INT_TX_EMPTY BIT(0)
	58
	59	#define HC_EN 0x10
	60	#define HC_EN_BIT BIT(0)
	61
	62	#define TXD(x) (0x14 + ((x) * 4))
	63	#define RXD 0x24
	64
65	#define SS_CTRL(s) (0x30 + ((s) * 4))
66	#define LRD_CFG 0x44
67	#define LWR_CFG 0x80
68	#define RWW_CFG 0x70
69	#define OP_READ BIT(23)
70	#define OP_DUMMY_CYC(x) ((x) << 17)
71	#define OP_ADDR_BYTES(x) ((x) << 14)
72	#define OP_CMD_BYTES(x) (((x) - 1) << 13)
73	#define OP_OCTA_CRC_EN BIT(12)
74	#define OP_DQS_EN BIT(11)
75	#define OP_ENHC_EN BIT(10)
76	#define OP_PREAMBLE_EN BIT(9)
77	#define OP_DATA_DDR BIT(8)
78	#define OP_DATA_BUSW(x) ((x) << 6)
79	#define OP_ADDR_DDR BIT(5)
80	#define OP_ADDR_BUSW(x) ((x) << 3)
81	#define OP_CMD_DDR BIT(2)
82	#define OP_CMD_BUSW(x) (x)
83	#define OP_BUSW_1 0
84	#define OP_BUSW_2 1
85	#define OP_BUSW_4 2
86	#define OP_BUSW_8 3
87
88	#define OCTA_CRC 0x38
89	#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
90	#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
91	#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
92
93	#define ONFI_DIN_CNT(s) (0x3c + (s))
94
95	#define LRD_CTRL 0x48
96	#define RWW_CTRL 0x74
97	#define LWR_CTRL 0x84
98	#define LMODE_EN BIT(31)
99	#define LMODE_SLV_ACT(x) ((x) << 21)
100	#define LMODE_CMD1(x) ((x) << 8)
101	#define LMODE_CMD0(x) (x)
102
103	#define LRD_ADDR 0x4c
104	#define LWR_ADDR 0x88
105	#define LRD_RANGE 0x50
106	#define LWR_RANGE 0x8c
107
108	#define AXI_SLV_ADDR 0x54
109
110	#define DMAC_RD_CFG 0x58
111	#define DMAC_WR_CFG 0x94
112	#define DMAC_CFG_PERIPH_EN BIT(31)
113	#define DMAC_CFG_ALLFLUSH_EN BIT(30)
114	#define DMAC_CFG_LASTFLUSH_EN BIT(29)
115	#define DMAC_CFG_QE(x) (((x) + 1) << 16)
116	#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
117	#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
118	#define DMAC_CFG_DIR_READ BIT(1)
119	#define DMAC_CFG_START BIT(0)
120
121	#define DMAC_RD_CNT 0x5c
122	#define DMAC_WR_CNT 0x98
123
124	#define SDMA_ADDR 0x60
125
126	#define DMAM_CFG 0x64
127	#define DMAM_CFG_START BIT(31)
128	#define DMAM_CFG_CONT BIT(30)
129	#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
130	#define DMAM_CFG_DIR_READ BIT(1)
131	#define DMAM_CFG_EN BIT(0)
132
133	#define DMAM_CNT 0x68
134
135	#define LNR_TIMER_TH 0x6c
136
137	#define RDM_CFG0 0x78
138	#define RDM_CFG0_POLY(x) (x)
139
140	#define RDM_CFG1 0x7c
141	#define RDM_CFG1_RDM_EN BIT(31)
142	#define RDM_CFG1_SEED(x) (x)
143
144	#define LWR_SUSP_CTRL 0x90
145	#define LWR_SUSP_CTRL_EN BIT(31)
146
147	#define DMAS_CTRL 0x9c
6fe7ab38 MR	148	#define DMAS_CTRL_EN BIT(31)
6fe7ab38 MR	149	#define DMAS_CTRL_DIR_READ BIT(30)
b942d80b MY	150
	151	#define DATA_STROB 0xa0
	152	#define DATA_STROB_EDO_EN BIT(2)
	153	#define DATA_STROB_INV_POL BIT(1)
	154	#define DATA_STROB_DELAY_2CYC BIT(0)
	155
	156	#define IDLY_CODE(x) (0xa4 + ((x) * 4))
	157	#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
	158
	159	#define GPIO 0xc4
	160	#define GPIO_PT(x) BIT(3 + ((x) * 16))
	161	#define GPIO_RESET(x) BIT(2 + ((x) * 16))
	162	#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
	163	#define GPIO_WPB(x) BIT((x) * 16)
	164
	165	#define HC_VER 0xd0
	166
	167	#define HW_TEST(x) (0xe0 + ((x) * 4))
	168
	169	struct mxic_spi {
	170	struct clk *ps_clk;
	171	struct clk *send_clk;
	172	struct clk *send_dly_clk;
	173	void __iomem *regs;
	174	u32 cur_speed_hz;
	175	};
	176
	177	static int mxic_spi_clk_enable(struct mxic_spi *mxic)
	178	{
	179	int ret;
	180
	181	ret = clk_prepare_enable(mxic->send_clk);
	182	if (ret)
	183	return ret;
	184
	185	ret = clk_prepare_enable(mxic->send_dly_clk);
	186	if (ret)
	187	goto err_send_dly_clk;
	188
	189	return ret;
	190
	191	err_send_dly_clk:
	192	clk_disable_unprepare(mxic->send_clk);
	193
	194	return ret;
	195	}
	196
	197	static void mxic_spi_clk_disable(struct mxic_spi *mxic)
	198	{
	199	clk_disable_unprepare(mxic->send_clk);
	200	clk_disable_unprepare(mxic->send_dly_clk);
	201	}
	202
	203	static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
	204	{
	205	writel(IDLY_CODE_VAL(0, idly_code) \|
	206	IDLY_CODE_VAL(1, idly_code) \|
	207	IDLY_CODE_VAL(2, idly_code) \|
	208	IDLY_CODE_VAL(3, idly_code),
	209	mxic->regs + IDLY_CODE(0));
	210	writel(IDLY_CODE_VAL(4, idly_code) \|
	211	IDLY_CODE_VAL(5, idly_code) \|
	212	IDLY_CODE_VAL(6, idly_code) \|
	213	IDLY_CODE_VAL(7, idly_code),
214	mxic->regs + IDLY_CODE(1));
215	}
216
217	static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
218	{
219	int ret;
220
221	ret = clk_set_rate(mxic->send_clk, freq);
222	if (ret)
223	return ret;
224
225	ret = clk_set_rate(mxic->send_dly_clk, freq);
226	if (ret)
227	return ret;
228
229	/*
230	* A constant delay range from 0x0 ~ 0x1F for input delay,
231	* the unit is 78 ps, the max input delay is 2.418 ns.
232	*/
233	mxic_spi_set_input_delay_dqs(mxic, 0xf);
234
235	/*
236	* Phase degree = 360 * freq * output-delay
237	* where output-delay is a constant value 1 ns in FPGA.
238	*
239	* Get Phase degree = 360 * freq * 1 ns
240	* = 360 * freq * 1 sec / 1000000000
241	* = 9 * freq / 25000000
242	*/
243	ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
244	if (ret)
245	return ret;
246
247	return 0;
248	}
249
250	static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
251	{
252	int ret;
253
254	if (mxic->cur_speed_hz == freq)
255	return 0;
256
257	mxic_spi_clk_disable(mxic);
258	ret = mxic_spi_clk_setup(mxic, freq);
259	if (ret)
260	return ret;
261
262	ret = mxic_spi_clk_enable(mxic);
263	if (ret)
264	return ret;
265
266	mxic->cur_speed_hz = freq;
267
268	return 0;
269	}
270
271	static void mxic_spi_hw_init(struct mxic_spi *mxic)
272	{
273	writel(0, mxic->regs + DATA_STROB);
274	writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
275	writel(0, mxic->regs + HC_EN);
276	writel(0, mxic->regs + LRD_CFG);
277	writel(0, mxic->regs + LRD_CTRL);
4a82fe0e	278	writel(HC_CFG_NIO(1) \| HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) \|
b942d80b MY	279	HC_CFG_SLV_ACT(0) \| HC_CFG_MAN_CS_EN \| HC_CFG_IDLE_SIO_LVL(1),
	280	mxic->regs + HC_CFG);
	281	}
	282
	283	static int mxic_spi_data_xfer(struct mxic_spi mxic, const void txbuf,
	284	void *rxbuf, unsigned int len)
	285	{
	286	unsigned int pos = 0;
	287
	288	while (pos < len) {
	289	unsigned int nbytes = len - pos;
	290	u32 data = 0xffffffff;
	291	u32 sts;
	292	int ret;
	293
	294	if (nbytes > 4)
	295	nbytes = 4;
	296
	297	if (txbuf)
	298	memcpy(&data, txbuf + pos, nbytes);
	299
	300	ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
	301	sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
	302	if (ret)
	303	return ret;
	304
	305	writel(data, mxic->regs + TXD(nbytes % 4));
	306
	307	if (rxbuf) {
	308	ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
	309	sts & INT_TX_EMPTY, 0,
	310	USEC_PER_SEC);
	311	if (ret)
	312	return ret;
	313
	314	ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
	315	sts & INT_RX_NOT_EMPTY, 0,
	316	USEC_PER_SEC);
	317	if (ret)
	318	return ret;
	319
	320	data = readl(mxic->regs + RXD);
	321	data >>= (8 * (4 - nbytes));
	322	memcpy(rxbuf + pos, &data, nbytes);
	323	WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
	324	} else {
	325	readl(mxic->regs + RXD);
	326	}
	327	WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
	328
	329	pos += nbytes;
	330	}
	331
	332	return 0;
	333	}
	334
	335	static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
	336	const struct spi_mem_op *op)
	337	{
d05aaa66 ZL	338	bool all_false;
	339
	340	if (op->data.buswidth > 8 \|\| op->addr.buswidth > 8 \|\|
	341	op->dummy.buswidth > 8 \|\| op->cmd.buswidth > 8)
b942d80b MY	342	return false;
	343
	344	if (op->data.nbytes && op->dummy.nbytes &&
	345	op->data.buswidth != op->dummy.buswidth)
	346	return false;
	347
	348	if (op->addr.nbytes > 7)
	349	return false;
	350
d05aaa66 ZL	351	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
	352	!op->data.dtr;
	353
	354	if (all_false)
	355	return spi_mem_default_supports_op(mem, op);
	356	else
	357	return spi_mem_dtr_supports_op(mem, op);
b942d80b MY	358	}
	359
	360	static int mxic_spi_mem_exec_op(struct spi_mem *mem,
	361	const struct spi_mem_op *op)
	362	{
	363	struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
	364	int nio = 1, i, ret;
	365	u32 ss_ctrl;
d05aaa66	366	u8 addr[8], cmd[2];
b942d80b MY	367
	368	ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
	369	if (ret)
	370	return ret;
	371
d05aaa66 ZL	372	if (mem->spi->mode & (SPI_TX_OCTAL \| SPI_RX_OCTAL))
	373	nio = 8;
	374	else if (mem->spi->mode & (SPI_TX_QUAD \| SPI_RX_QUAD))
b942d80b MY	375	nio = 4;
	376	else if (mem->spi->mode & (SPI_TX_DUAL \| SPI_RX_DUAL))
	377	nio = 2;
	378
	379	writel(HC_CFG_NIO(nio) \|
	380	HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) \|
	381	HC_CFG_SLV_ACT(mem->spi->chip_select) \| HC_CFG_IDLE_SIO_LVL(1) \|
	382	HC_CFG_MAN_CS_EN,
	383	mxic->regs + HC_CFG);
	384	writel(HC_EN_BIT, mxic->regs + HC_EN);
	385
d05aaa66 ZL	386	ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) \|
	387	OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) \|
	388	(op->cmd.dtr ? OP_CMD_DDR : 0);
b942d80b MY	389
	390	if (op->addr.nbytes)
	391	ss_ctrl \|= OP_ADDR_BYTES(op->addr.nbytes) \|
d05aaa66 ZL	392	OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) \|
d05aaa66 ZL	393	(op->addr.dtr ? OP_ADDR_DDR : 0);
b942d80b MY	394
	395	if (op->dummy.nbytes)
	396	ss_ctrl \|= OP_DUMMY_CYC(op->dummy.nbytes);
	397
	398	if (op->data.nbytes) {
d05aaa66 ZL	399	ss_ctrl \|= OP_DATA_BUSW(fls(op->data.buswidth) - 1) \|
d05aaa66 ZL	400	(op->data.dtr ? OP_DATA_DDR : 0);
aca19684	401	if (op->data.dir == SPI_MEM_DATA_IN) {
b942d80b	402	ss_ctrl \|= OP_READ;
d05aaa66 ZL	403	if (op->data.dtr)
d05aaa66 ZL	404	ss_ctrl \|= OP_DQS_EN;
aca19684	405	}
b942d80b MY	406	}
	407
	408	writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
	409
	410	writel(readl(mxic->regs + HC_CFG) \| HC_CFG_MAN_CS_ASSERT,
	411	mxic->regs + HC_CFG);
	412
d05aaa66 ZL	413	for (i = 0; i < op->cmd.nbytes; i++)
	414	cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1));
	415
	416	ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
b942d80b MY	417	if (ret)
	418	goto out;
	419
	420	for (i = 0; i < op->addr.nbytes; i++)
	421	addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
	422
	423	ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
	424	if (ret)
	425	goto out;
	426
	427	ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
	428	if (ret)
	429	goto out;
	430
	431	ret = mxic_spi_data_xfer(mxic,
	432	op->data.dir == SPI_MEM_DATA_OUT ?
	433	op->data.buf.out : NULL,
	434	op->data.dir == SPI_MEM_DATA_IN ?
	435	op->data.buf.in : NULL,
	436	op->data.nbytes);
	437
	438	out:
	439	writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
	440	mxic->regs + HC_CFG);
	441	writel(0, mxic->regs + HC_EN);
	442
	443	return ret;
	444	}
	445
	446	static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
	447	.supports_op = mxic_spi_mem_supports_op,
	448	.exec_op = mxic_spi_mem_exec_op,
	449	};
	450
	451	static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
	452	{
	453	struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
	454
	455	if (!lvl) {
	456	writel(readl(mxic->regs + HC_CFG) \| HC_CFG_MAN_CS_EN,
	457	mxic->regs + HC_CFG);
	458	writel(HC_EN_BIT, mxic->regs + HC_EN);
	459	writel(readl(mxic->regs + HC_CFG) \| HC_CFG_MAN_CS_ASSERT,
	460	mxic->regs + HC_CFG);
	461	} else {
	462	writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
	463	mxic->regs + HC_CFG);
	464	writel(0, mxic->regs + HC_EN);
	465	}
	466	}
	467
	468	static int mxic_spi_transfer_one(struct spi_master *master,
	469	struct spi_device *spi,
	470	struct spi_transfer *t)
	471	{
	472	struct mxic_spi *mxic = spi_master_get_devdata(master);
	473	unsigned int busw = OP_BUSW_1;
	474	int ret;
	475
	476	if (t->rx_buf && t->tx_buf) {
	477	if (((spi->mode & SPI_TX_QUAD) &&
	478	!(spi->mode & SPI_RX_QUAD)) \|\|
	479	((spi->mode & SPI_TX_DUAL) &&
	480	!(spi->mode & SPI_RX_DUAL)))
481	return -ENOTSUPP;
482	}
483
484	ret = mxic_spi_set_freq(mxic, t->speed_hz);
485	if (ret)
486	return ret;
487
488	if (t->tx_buf) {
489	if (spi->mode & SPI_TX_QUAD)
490	busw = OP_BUSW_4;
491	else if (spi->mode & SPI_TX_DUAL)
492	busw = OP_BUSW_2;
493	} else if (t->rx_buf) {
494	if (spi->mode & SPI_RX_QUAD)
495	busw = OP_BUSW_4;
496	else if (spi->mode & SPI_RX_DUAL)
497	busw = OP_BUSW_2;
498	}
499
500	writel(OP_CMD_BYTES(1) \| OP_CMD_BUSW(busw) \|
501	OP_DATA_BUSW(busw) \| (t->rx_buf ? OP_READ : 0),
502	mxic->regs + SS_CTRL(0));
503
504	ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
505	if (ret)
506	return ret;
507
508	spi_finalize_current_transfer(master);
509
510	return 0;
511	}
512
513	static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
514	{
f457cb70	515	struct spi_master *master = dev_get_drvdata(dev);
b942d80b MY	516	struct mxic_spi *mxic = spi_master_get_devdata(master);
	517
	518	mxic_spi_clk_disable(mxic);
	519	clk_disable_unprepare(mxic->ps_clk);
	520
	521	return 0;
	522	}
	523
	524	static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
	525	{
f457cb70	526	struct spi_master *master = dev_get_drvdata(dev);
b942d80b MY	527	struct mxic_spi *mxic = spi_master_get_devdata(master);
	528	int ret;
	529
	530	ret = clk_prepare_enable(mxic->ps_clk);
	531	if (ret) {
	532	dev_err(dev, "Cannot enable ps_clock.\n");
	533	return ret;
	534	}
	535
	536	return mxic_spi_clk_enable(mxic);
	537	}
	538
	539	static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
	540	SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
	541	mxic_spi_runtime_resume, NULL)
	542	};
	543
	544	static int mxic_spi_probe(struct platform_device *pdev)
	545	{
	546	struct spi_master *master;
	547	struct resource *res;
	548	struct mxic_spi *mxic;
	549	int ret;
	550
cc53711b	551	master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
b942d80b MY	552	if (!master)
	553	return -ENOMEM;
	554
	555	platform_set_drvdata(pdev, master);
	556
	557	mxic = spi_master_get_devdata(master);
	558
	559	master->dev.of_node = pdev->dev.of_node;
	560
	561	mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
	562	if (IS_ERR(mxic->ps_clk))
	563	return PTR_ERR(mxic->ps_clk);
	564
	565	mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
	566	if (IS_ERR(mxic->send_clk))
	567	return PTR_ERR(mxic->send_clk);
	568
	569	mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
	570	if (IS_ERR(mxic->send_dly_clk))
	571	return PTR_ERR(mxic->send_dly_clk);
	572
	573	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	574	mxic->regs = devm_ioremap_resource(&pdev->dev, res);
	575	if (IS_ERR(mxic->regs))
	576	return PTR_ERR(mxic->regs);
	577
	578	pm_runtime_enable(&pdev->dev);
	579	master->auto_runtime_pm = true;
	580
	581	master->num_chipselect = 1;
	582	master->mem_ops = &mxic_spi_mem_ops;
	583
	584	master->set_cs = mxic_spi_set_cs;
	585	master->transfer_one = mxic_spi_transfer_one;
	586	master->bits_per_word_mask = SPI_BPW_MASK(8);
	587	master->mode_bits = SPI_CPOL \| SPI_CPHA \|
	588	SPI_RX_DUAL \| SPI_TX_DUAL \|
d05aaa66 ZL	589	SPI_RX_QUAD \| SPI_TX_QUAD \|
d05aaa66 ZL	590	SPI_RX_OCTAL \| SPI_TX_OCTAL;
b942d80b MY	591
	592	mxic_spi_hw_init(mxic);
	593
	594	ret = spi_register_master(master);
	595	if (ret) {
	596	dev_err(&pdev->dev, "spi_register_master failed\n");
cc53711b	597	pm_runtime_disable(&pdev->dev);
b942d80b MY	598	}
b942d80b MY	599
b942d80b MY	600	return ret;
	601	}
	602
	603	static int mxic_spi_remove(struct platform_device *pdev)
	604	{
	605	struct spi_master *master = platform_get_drvdata(pdev);
	606
	607	pm_runtime_disable(&pdev->dev);
	608	spi_unregister_master(master);
	609
	610	return 0;
	611	}
	612
	613	static const struct of_device_id mxic_spi_of_ids[] = {
	614	{ .compatible = "mxicy,mx25f0a-spi", },
	615	{ /* sentinel */ }
	616	};
	617	MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);
	618
	619	static struct platform_driver mxic_spi_driver = {
	620	.probe = mxic_spi_probe,
	621	.remove = mxic_spi_remove,
	622	.driver = {
	623	.name = "mxic-spi",
	624	.of_match_table = mxic_spi_of_ids,
	625	.pm = &mxic_spi_dev_pm_ops,
	626	},
	627	};
	628	module_platform_driver(mxic_spi_driver);
	629
	630	MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
	631	MODULE_DESCRIPTION("MX25F0A SPI controller driver");
	632	MODULE_LICENSE("GPL v2");