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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a568231f LL |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
4 | * Author: Leilk Liu <leilk.liu@mediatek.com> | |
a568231f LL |
5 | */ |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/device.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/interrupt.h> | |
dd69a0a6 | 11 | #include <linux/io.h> |
a568231f LL |
12 | #include <linux/ioport.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
1a5a87d5 | 15 | #include <linux/gpio/consumer.h> |
a568231f LL |
16 | #include <linux/platform_device.h> |
17 | #include <linux/platform_data/spi-mt65xx.h> | |
18 | #include <linux/pm_runtime.h> | |
19 | #include <linux/spi/spi.h> | |
9f763fd2 | 20 | #include <linux/spi/spi-mem.h> |
fdeae8f5 | 21 | #include <linux/dma-mapping.h> |
a568231f LL |
22 | |
23 | #define SPI_CFG0_REG 0x0000 | |
24 | #define SPI_CFG1_REG 0x0004 | |
25 | #define SPI_TX_SRC_REG 0x0008 | |
26 | #define SPI_RX_DST_REG 0x000c | |
27 | #define SPI_TX_DATA_REG 0x0010 | |
28 | #define SPI_RX_DATA_REG 0x0014 | |
29 | #define SPI_CMD_REG 0x0018 | |
30 | #define SPI_STATUS0_REG 0x001c | |
31 | #define SPI_PAD_SEL_REG 0x0024 | |
058fe49d | 32 | #define SPI_CFG2_REG 0x0028 |
fdeae8f5 | 33 | #define SPI_TX_SRC_REG_64 0x002c |
34 | #define SPI_RX_DST_REG_64 0x0030 | |
7e963fb2 | 35 | #define SPI_CFG3_IPM_REG 0x0040 |
a568231f LL |
36 | |
37 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 | |
38 | #define SPI_CFG0_SCK_LOW_OFFSET 8 | |
39 | #define SPI_CFG0_CS_HOLD_OFFSET 16 | |
40 | #define SPI_CFG0_CS_SETUP_OFFSET 24 | |
058fe49d LL |
41 | #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 |
42 | #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 | |
a568231f LL |
43 | |
44 | #define SPI_CFG1_CS_IDLE_OFFSET 0 | |
45 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 | |
46 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 | |
f84d866a | 47 | #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 |
03b1be37 | 48 | #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 |
a568231f | 49 | |
f84d866a | 50 | #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 |
03b1be37 LL |
51 | #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 |
52 | ||
a568231f LL |
53 | #define SPI_CFG1_CS_IDLE_MASK 0xff |
54 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 | |
55 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 | |
7e963fb2 | 56 | #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) |
44b37eb7 | 57 | #define SPI_CFG2_SCK_HIGH_OFFSET 0 |
58 | #define SPI_CFG2_SCK_LOW_OFFSET 16 | |
a568231f | 59 | |
a71d6ea6 LL |
60 | #define SPI_CMD_ACT BIT(0) |
61 | #define SPI_CMD_RESUME BIT(1) | |
a568231f LL |
62 | #define SPI_CMD_RST BIT(2) |
63 | #define SPI_CMD_PAUSE_EN BIT(4) | |
64 | #define SPI_CMD_DEASSERT BIT(5) | |
058fe49d LL |
65 | #define SPI_CMD_SAMPLE_SEL BIT(6) |
66 | #define SPI_CMD_CS_POL BIT(7) | |
a568231f LL |
67 | #define SPI_CMD_CPHA BIT(8) |
68 | #define SPI_CMD_CPOL BIT(9) | |
69 | #define SPI_CMD_RX_DMA BIT(10) | |
70 | #define SPI_CMD_TX_DMA BIT(11) | |
71 | #define SPI_CMD_TXMSBF BIT(12) | |
72 | #define SPI_CMD_RXMSBF BIT(13) | |
73 | #define SPI_CMD_RX_ENDIAN BIT(14) | |
74 | #define SPI_CMD_TX_ENDIAN BIT(15) | |
75 | #define SPI_CMD_FINISH_IE BIT(16) | |
76 | #define SPI_CMD_PAUSE_IE BIT(17) | |
7e963fb2 LL |
77 | #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) |
78 | #define SPI_CMD_IPM_SPIM_LOOP BIT(21) | |
79 | #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 | |
a568231f | 80 | |
7e963fb2 | 81 | #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) |
9f763fd2 LL |
82 | |
83 | #define PIN_MODE_CFG(x) ((x) / 2) | |
84 | ||
7e963fb2 LL |
85 | #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) |
86 | #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) | |
9f763fd2 LL |
87 | #define SPI_CFG3_IPM_XMODE_EN BIT(4) |
88 | #define SPI_CFG3_IPM_NODATA_FLAG BIT(5) | |
89 | #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 | |
90 | #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 | |
91 | ||
92 | #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) | |
93 | #define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) | |
94 | #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) | |
95 | ||
a568231f LL |
96 | #define MT8173_SPI_MAX_PAD_SEL 3 |
97 | ||
50f8fec2 LL |
98 | #define MTK_SPI_PAUSE_INT_STATUS 0x2 |
99 | ||
a568231f LL |
100 | #define MTK_SPI_IDLE 0 |
101 | #define MTK_SPI_PAUSED 1 | |
102 | ||
1ce24864 | 103 | #define MTK_SPI_MAX_FIFO_SIZE 32U |
a568231f | 104 | #define MTK_SPI_PACKET_SIZE 1024 |
7e963fb2 | 105 | #define MTK_SPI_IPM_PACKET_SIZE SZ_64K |
9f763fd2 LL |
106 | #define MTK_SPI_IPM_PACKET_LOOP SZ_256 |
107 | ||
fdeae8f5 | 108 | #define MTK_SPI_32BITS_MASK (0xffffffff) |
109 | ||
110 | #define DMA_ADDR_EXT_BITS (36) | |
111 | #define DMA_ADDR_DEF_BITS (32) | |
a568231f LL |
112 | |
113 | struct mtk_spi_compatible { | |
af57937e LL |
114 | bool need_pad_sel; |
115 | /* Must explicitly send dummy Tx bytes to do Rx only transfer */ | |
116 | bool must_tx; | |
058fe49d LL |
117 | /* some IC design adjust cfg register to enhance time accuracy */ |
118 | bool enhance_timing; | |
fdeae8f5 | 119 | /* some IC support DMA addr extension */ |
120 | bool dma_ext; | |
162a31ef MZ |
121 | /* some IC no need unprepare SPI clk */ |
122 | bool no_need_unprepare; | |
7e963fb2 LL |
123 | /* IPM design adjust and extend register to support more features */ |
124 | bool ipm_design; | |
a568231f LL |
125 | }; |
126 | ||
127 | struct mtk_spi { | |
128 | void __iomem *base; | |
129 | u32 state; | |
37457607 LL |
130 | int pad_num; |
131 | u32 *pad_sel; | |
a740f4e6 | 132 | struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; |
a568231f LL |
133 | struct spi_transfer *cur_transfer; |
134 | u32 xfer_len; | |
00bca73b | 135 | u32 num_xfered; |
a568231f LL |
136 | struct scatterlist *tx_sgl, *rx_sgl; |
137 | u32 tx_sgl_len, rx_sgl_len; | |
138 | const struct mtk_spi_compatible *dev_comp; | |
162a31ef | 139 | u32 spi_clk_hz; |
9f763fd2 LL |
140 | struct completion spimem_done; |
141 | bool use_spimem; | |
142 | struct device *dev; | |
143 | dma_addr_t tx_dma; | |
144 | dma_addr_t rx_dma; | |
a568231f LL |
145 | }; |
146 | ||
4eaf6f73 | 147 | static const struct mtk_spi_compatible mtk_common_compat; |
fc4f226f | 148 | |
b6b1f2d9 | 149 | static const struct mtk_spi_compatible mt2712_compat = { |
150 | .must_tx = true, | |
151 | }; | |
152 | ||
7e963fb2 LL |
153 | static const struct mtk_spi_compatible mtk_ipm_compat = { |
154 | .enhance_timing = true, | |
155 | .dma_ext = true, | |
156 | .ipm_design = true, | |
157 | }; | |
158 | ||
2c231e0a | 159 | static const struct mtk_spi_compatible mt6765_compat = { |
160 | .need_pad_sel = true, | |
161 | .must_tx = true, | |
162 | .enhance_timing = true, | |
fdeae8f5 | 163 | .dma_ext = true, |
2c231e0a | 164 | }; |
165 | ||
fc4f226f LL |
166 | static const struct mtk_spi_compatible mt7622_compat = { |
167 | .must_tx = true, | |
168 | .enhance_timing = true, | |
169 | }; | |
170 | ||
a568231f | 171 | static const struct mtk_spi_compatible mt8173_compat = { |
af57937e LL |
172 | .need_pad_sel = true, |
173 | .must_tx = true, | |
a568231f LL |
174 | }; |
175 | ||
b654aa6f LL |
176 | static const struct mtk_spi_compatible mt8183_compat = { |
177 | .need_pad_sel = true, | |
178 | .must_tx = true, | |
179 | .enhance_timing = true, | |
180 | }; | |
181 | ||
162a31ef MZ |
182 | static const struct mtk_spi_compatible mt6893_compat = { |
183 | .need_pad_sel = true, | |
184 | .must_tx = true, | |
185 | .enhance_timing = true, | |
186 | .dma_ext = true, | |
187 | .no_need_unprepare = true, | |
188 | }; | |
189 | ||
a568231f LL |
190 | /* |
191 | * A piece of default chip info unless the platform | |
192 | * supplies it. | |
193 | */ | |
194 | static const struct mtk_chip_config mtk_default_chip_info = { | |
058fe49d | 195 | .sample_sel = 0, |
f84d866a | 196 | .tick_delay = 0, |
a568231f LL |
197 | }; |
198 | ||
199 | static const struct of_device_id mtk_spi_of_match[] = { | |
7e963fb2 LL |
200 | { .compatible = "mediatek,spi-ipm", |
201 | .data = (void *)&mtk_ipm_compat, | |
202 | }, | |
15bcdefd LL |
203 | { .compatible = "mediatek,mt2701-spi", |
204 | .data = (void *)&mtk_common_compat, | |
205 | }, | |
b6b1f2d9 | 206 | { .compatible = "mediatek,mt2712-spi", |
207 | .data = (void *)&mt2712_compat, | |
208 | }, | |
4eaf6f73 LL |
209 | { .compatible = "mediatek,mt6589-spi", |
210 | .data = (void *)&mtk_common_compat, | |
211 | }, | |
2c231e0a | 212 | { .compatible = "mediatek,mt6765-spi", |
213 | .data = (void *)&mt6765_compat, | |
214 | }, | |
fc4f226f LL |
215 | { .compatible = "mediatek,mt7622-spi", |
216 | .data = (void *)&mt7622_compat, | |
217 | }, | |
942779c6 LL |
218 | { .compatible = "mediatek,mt7629-spi", |
219 | .data = (void *)&mt7622_compat, | |
220 | }, | |
4eaf6f73 LL |
221 | { .compatible = "mediatek,mt8135-spi", |
222 | .data = (void *)&mtk_common_compat, | |
223 | }, | |
224 | { .compatible = "mediatek,mt8173-spi", | |
225 | .data = (void *)&mt8173_compat, | |
226 | }, | |
b654aa6f LL |
227 | { .compatible = "mediatek,mt8183-spi", |
228 | .data = (void *)&mt8183_compat, | |
229 | }, | |
8cf125c4 | 230 | { .compatible = "mediatek,mt8192-spi", |
231 | .data = (void *)&mt6765_compat, | |
232 | }, | |
162a31ef MZ |
233 | { .compatible = "mediatek,mt6893-spi", |
234 | .data = (void *)&mt6893_compat, | |
235 | }, | |
a568231f LL |
236 | {} |
237 | }; | |
238 | MODULE_DEVICE_TABLE(of, mtk_spi_of_match); | |
239 | ||
240 | static void mtk_spi_reset(struct mtk_spi *mdata) | |
241 | { | |
242 | u32 reg_val; | |
243 | ||
244 | /* set the software reset bit in SPI_CMD_REG. */ | |
245 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
246 | reg_val |= SPI_CMD_RST; | |
247 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
248 | ||
249 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
250 | reg_val &= ~SPI_CMD_RST; | |
251 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
252 | } | |
253 | ||
04e6bb0d MZ |
254 | static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) |
255 | { | |
256 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
257 | struct spi_delay *cs_setup = &spi->cs_setup; | |
258 | struct spi_delay *cs_hold = &spi->cs_hold; | |
259 | struct spi_delay *cs_inactive = &spi->cs_inactive; | |
5c842e51 | 260 | u32 setup, hold, inactive; |
04e6bb0d MZ |
261 | u32 reg_val; |
262 | int delay; | |
263 | ||
264 | delay = spi_delay_to_ns(cs_setup, NULL); | |
265 | if (delay < 0) | |
266 | return delay; | |
267 | setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
268 | ||
269 | delay = spi_delay_to_ns(cs_hold, NULL); | |
270 | if (delay < 0) | |
271 | return delay; | |
272 | hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
273 | ||
274 | delay = spi_delay_to_ns(cs_inactive, NULL); | |
275 | if (delay < 0) | |
276 | return delay; | |
277 | inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
278 | ||
3672bb82 DH |
279 | if (hold || setup) { |
280 | reg_val = readl(mdata->base + SPI_CFG0_REG); | |
281 | if (mdata->dev_comp->enhance_timing) { | |
282 | if (hold) { | |
283 | hold = min_t(u32, hold, 0x10000); | |
284 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); | |
285 | reg_val |= (((hold - 1) & 0xffff) | |
286 | << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); | |
287 | } | |
288 | if (setup) { | |
289 | setup = min_t(u32, setup, 0x10000); | |
290 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); | |
291 | reg_val |= (((setup - 1) & 0xffff) | |
292 | << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); | |
293 | } | |
294 | } else { | |
295 | if (hold) { | |
296 | hold = min_t(u32, hold, 0x100); | |
297 | reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); | |
298 | reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); | |
299 | } | |
300 | if (setup) { | |
301 | setup = min_t(u32, setup, 0x100); | |
302 | reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); | |
303 | reg_val |= (((setup - 1) & 0xff) | |
304 | << SPI_CFG0_CS_SETUP_OFFSET); | |
305 | } | |
306 | } | |
307 | writel(reg_val, mdata->base + SPI_CFG0_REG); | |
04e6bb0d | 308 | } |
04e6bb0d | 309 | |
3672bb82 DH |
310 | if (inactive) { |
311 | inactive = min_t(u32, inactive, 0x100); | |
312 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
313 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; | |
314 | reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); | |
315 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
316 | } | |
04e6bb0d MZ |
317 | |
318 | return 0; | |
319 | } | |
320 | ||
7e963fb2 LL |
321 | static int mtk_spi_hw_init(struct spi_master *master, |
322 | struct spi_device *spi) | |
a568231f | 323 | { |
79b5d3f2 | 324 | u16 cpha, cpol; |
a568231f | 325 | u32 reg_val; |
58a984c7 | 326 | struct mtk_chip_config *chip_config = spi->controller_data; |
79b5d3f2 LL |
327 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
328 | ||
329 | cpha = spi->mode & SPI_CPHA ? 1 : 0; | |
330 | cpol = spi->mode & SPI_CPOL ? 1 : 0; | |
331 | ||
79b5d3f2 | 332 | reg_val = readl(mdata->base + SPI_CMD_REG); |
7e963fb2 LL |
333 | if (mdata->dev_comp->ipm_design) { |
334 | /* SPI transfer without idle time until packet length done */ | |
335 | reg_val |= SPI_CMD_IPM_NONIDLE_MODE; | |
336 | if (spi->mode & SPI_LOOP) | |
337 | reg_val |= SPI_CMD_IPM_SPIM_LOOP; | |
338 | else | |
339 | reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; | |
340 | } | |
341 | ||
79b5d3f2 LL |
342 | if (cpha) |
343 | reg_val |= SPI_CMD_CPHA; | |
344 | else | |
345 | reg_val &= ~SPI_CMD_CPHA; | |
346 | if (cpol) | |
347 | reg_val |= SPI_CMD_CPOL; | |
348 | else | |
349 | reg_val &= ~SPI_CMD_CPOL; | |
a568231f LL |
350 | |
351 | /* set the mlsbx and mlsbtx */ | |
3e582c6e | 352 | if (spi->mode & SPI_LSB_FIRST) { |
a71d6ea6 | 353 | reg_val &= ~SPI_CMD_TXMSBF; |
a71d6ea6 | 354 | reg_val &= ~SPI_CMD_RXMSBF; |
3e582c6e LL |
355 | } else { |
356 | reg_val |= SPI_CMD_TXMSBF; | |
357 | reg_val |= SPI_CMD_RXMSBF; | |
358 | } | |
a568231f LL |
359 | |
360 | /* set the tx/rx endian */ | |
44f636da LL |
361 | #ifdef __LITTLE_ENDIAN |
362 | reg_val &= ~SPI_CMD_TX_ENDIAN; | |
363 | reg_val &= ~SPI_CMD_RX_ENDIAN; | |
364 | #else | |
365 | reg_val |= SPI_CMD_TX_ENDIAN; | |
366 | reg_val |= SPI_CMD_RX_ENDIAN; | |
367 | #endif | |
a568231f | 368 | |
058fe49d | 369 | if (mdata->dev_comp->enhance_timing) { |
ae7c2d34 LX |
370 | /* set CS polarity */ |
371 | if (spi->mode & SPI_CS_HIGH) | |
058fe49d LL |
372 | reg_val |= SPI_CMD_CS_POL; |
373 | else | |
374 | reg_val &= ~SPI_CMD_CS_POL; | |
ae7c2d34 | 375 | |
058fe49d LL |
376 | if (chip_config->sample_sel) |
377 | reg_val |= SPI_CMD_SAMPLE_SEL; | |
378 | else | |
379 | reg_val &= ~SPI_CMD_SAMPLE_SEL; | |
380 | } | |
381 | ||
a568231f | 382 | /* set finish and pause interrupt always enable */ |
15293324 | 383 | reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; |
a568231f LL |
384 | |
385 | /* disable dma mode */ | |
386 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); | |
387 | ||
388 | /* disable deassert mode */ | |
389 | reg_val &= ~SPI_CMD_DEASSERT; | |
390 | ||
391 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
392 | ||
393 | /* pad select */ | |
394 | if (mdata->dev_comp->need_pad_sel) | |
37457607 LL |
395 | writel(mdata->pad_sel[spi->chip_select], |
396 | mdata->base + SPI_PAD_SEL_REG); | |
a568231f | 397 | |
f84d866a | 398 | /* tick delay */ |
03b1be37 | 399 | if (mdata->dev_comp->enhance_timing) { |
7e963fb2 LL |
400 | if (mdata->dev_comp->ipm_design) { |
401 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
402 | reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; | |
403 | reg_val |= ((chip_config->tick_delay & 0x7) | |
404 | << SPI_CMD_IPM_GET_TICKDLY_OFFSET); | |
405 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
406 | } else { | |
407 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
408 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; | |
409 | reg_val |= ((chip_config->tick_delay & 0x7) | |
410 | << SPI_CFG1_GET_TICK_DLY_OFFSET); | |
411 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
412 | } | |
03b1be37 | 413 | } else { |
7e963fb2 | 414 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
03b1be37 LL |
415 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; |
416 | reg_val |= ((chip_config->tick_delay & 0x3) | |
417 | << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); | |
7e963fb2 | 418 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
03b1be37 | 419 | } |
f84d866a | 420 | |
04e6bb0d MZ |
421 | /* set hw cs timing */ |
422 | mtk_spi_set_hw_cs_timing(spi); | |
a568231f LL |
423 | return 0; |
424 | } | |
425 | ||
7e963fb2 LL |
426 | static int mtk_spi_prepare_message(struct spi_master *master, |
427 | struct spi_message *msg) | |
428 | { | |
429 | return mtk_spi_hw_init(master, msg->spi); | |
430 | } | |
431 | ||
a568231f LL |
432 | static void mtk_spi_set_cs(struct spi_device *spi, bool enable) |
433 | { | |
434 | u32 reg_val; | |
435 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
436 | ||
ae7c2d34 LX |
437 | if (spi->mode & SPI_CS_HIGH) |
438 | enable = !enable; | |
439 | ||
a568231f | 440 | reg_val = readl(mdata->base + SPI_CMD_REG); |
6583d203 | 441 | if (!enable) { |
a568231f | 442 | reg_val |= SPI_CMD_PAUSE_EN; |
6583d203 LL |
443 | writel(reg_val, mdata->base + SPI_CMD_REG); |
444 | } else { | |
a568231f | 445 | reg_val &= ~SPI_CMD_PAUSE_EN; |
6583d203 LL |
446 | writel(reg_val, mdata->base + SPI_CMD_REG); |
447 | mdata->state = MTK_SPI_IDLE; | |
448 | mtk_spi_reset(mdata); | |
449 | } | |
a568231f LL |
450 | } |
451 | ||
452 | static void mtk_spi_prepare_transfer(struct spi_master *master, | |
7e963fb2 | 453 | u32 speed_hz) |
a568231f | 454 | { |
162a31ef | 455 | u32 div, sck_time, reg_val; |
a568231f LL |
456 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
457 | ||
7e963fb2 LL |
458 | if (speed_hz < mdata->spi_clk_hz / 2) |
459 | div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); | |
a568231f LL |
460 | else |
461 | div = 1; | |
462 | ||
2ce0acf5 | 463 | sck_time = (div + 1) / 2; |
a568231f | 464 | |
058fe49d | 465 | if (mdata->dev_comp->enhance_timing) { |
9f6e7e8d | 466 | reg_val = readl(mdata->base + SPI_CFG2_REG); |
467 | reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); | |
468 | reg_val |= (((sck_time - 1) & 0xffff) | |
44b37eb7 | 469 | << SPI_CFG2_SCK_HIGH_OFFSET); |
9f6e7e8d | 470 | reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); |
058fe49d | 471 | reg_val |= (((sck_time - 1) & 0xffff) |
44b37eb7 | 472 | << SPI_CFG2_SCK_LOW_OFFSET); |
058fe49d | 473 | writel(reg_val, mdata->base + SPI_CFG2_REG); |
058fe49d | 474 | } else { |
9f6e7e8d | 475 | reg_val = readl(mdata->base + SPI_CFG0_REG); |
476 | reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); | |
477 | reg_val |= (((sck_time - 1) & 0xff) | |
058fe49d | 478 | << SPI_CFG0_SCK_HIGH_OFFSET); |
9f6e7e8d | 479 | reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); |
058fe49d | 480 | reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); |
058fe49d LL |
481 | writel(reg_val, mdata->base + SPI_CFG0_REG); |
482 | } | |
a568231f LL |
483 | } |
484 | ||
485 | static void mtk_spi_setup_packet(struct spi_master *master) | |
486 | { | |
487 | u32 packet_size, packet_loop, reg_val; | |
488 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
489 | ||
7e963fb2 LL |
490 | if (mdata->dev_comp->ipm_design) |
491 | packet_size = min_t(u32, | |
492 | mdata->xfer_len, | |
493 | MTK_SPI_IPM_PACKET_SIZE); | |
494 | else | |
495 | packet_size = min_t(u32, | |
496 | mdata->xfer_len, | |
497 | MTK_SPI_PACKET_SIZE); | |
498 | ||
a568231f LL |
499 | packet_loop = mdata->xfer_len / packet_size; |
500 | ||
501 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
7e963fb2 LL |
502 | if (mdata->dev_comp->ipm_design) |
503 | reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; | |
504 | else | |
505 | reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; | |
a568231f | 506 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; |
7e963fb2 | 507 | reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; |
a568231f LL |
508 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; |
509 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
510 | } | |
511 | ||
512 | static void mtk_spi_enable_transfer(struct spi_master *master) | |
513 | { | |
50f8fec2 | 514 | u32 cmd; |
a568231f LL |
515 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
516 | ||
517 | cmd = readl(mdata->base + SPI_CMD_REG); | |
518 | if (mdata->state == MTK_SPI_IDLE) | |
a71d6ea6 | 519 | cmd |= SPI_CMD_ACT; |
a568231f | 520 | else |
a71d6ea6 | 521 | cmd |= SPI_CMD_RESUME; |
a568231f LL |
522 | writel(cmd, mdata->base + SPI_CMD_REG); |
523 | } | |
524 | ||
50f8fec2 | 525 | static int mtk_spi_get_mult_delta(u32 xfer_len) |
a568231f | 526 | { |
50f8fec2 | 527 | u32 mult_delta; |
a568231f LL |
528 | |
529 | if (xfer_len > MTK_SPI_PACKET_SIZE) | |
530 | mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; | |
531 | else | |
532 | mult_delta = 0; | |
533 | ||
534 | return mult_delta; | |
535 | } | |
536 | ||
537 | static void mtk_spi_update_mdata_len(struct spi_master *master) | |
538 | { | |
539 | int mult_delta; | |
540 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
541 | ||
542 | if (mdata->tx_sgl_len && mdata->rx_sgl_len) { | |
543 | if (mdata->tx_sgl_len > mdata->rx_sgl_len) { | |
544 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
545 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
546 | mdata->rx_sgl_len = mult_delta; | |
547 | mdata->tx_sgl_len -= mdata->xfer_len; | |
548 | } else { | |
549 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
550 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
551 | mdata->tx_sgl_len = mult_delta; | |
552 | mdata->rx_sgl_len -= mdata->xfer_len; | |
553 | } | |
554 | } else if (mdata->tx_sgl_len) { | |
555 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
556 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
557 | mdata->tx_sgl_len = mult_delta; | |
558 | } else if (mdata->rx_sgl_len) { | |
559 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
560 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
561 | mdata->rx_sgl_len = mult_delta; | |
562 | } | |
563 | } | |
564 | ||
565 | static void mtk_spi_setup_dma_addr(struct spi_master *master, | |
566 | struct spi_transfer *xfer) | |
567 | { | |
568 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
569 | ||
fdeae8f5 | 570 | if (mdata->tx_sgl) { |
571 | writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), | |
572 | mdata->base + SPI_TX_SRC_REG); | |
573 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
574 | if (mdata->dev_comp->dma_ext) | |
575 | writel((u32)(xfer->tx_dma >> 32), | |
576 | mdata->base + SPI_TX_SRC_REG_64); | |
577 | #endif | |
578 | } | |
579 | ||
580 | if (mdata->rx_sgl) { | |
581 | writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), | |
582 | mdata->base + SPI_RX_DST_REG); | |
583 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
584 | if (mdata->dev_comp->dma_ext) | |
585 | writel((u32)(xfer->rx_dma >> 32), | |
586 | mdata->base + SPI_RX_DST_REG_64); | |
587 | #endif | |
588 | } | |
a568231f LL |
589 | } |
590 | ||
591 | static int mtk_spi_fifo_transfer(struct spi_master *master, | |
592 | struct spi_device *spi, | |
593 | struct spi_transfer *xfer) | |
594 | { | |
de327e49 NB |
595 | int cnt, remainder; |
596 | u32 reg_val; | |
a568231f LL |
597 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
598 | ||
599 | mdata->cur_transfer = xfer; | |
1ce24864 | 600 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); |
00bca73b | 601 | mdata->num_xfered = 0; |
7e963fb2 | 602 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
a568231f LL |
603 | mtk_spi_setup_packet(master); |
604 | ||
0d5c3954 GR |
605 | if (xfer->tx_buf) { |
606 | cnt = xfer->len / 4; | |
3a70dd2d | 607 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); |
0d5c3954 GR |
608 | remainder = xfer->len % 4; |
609 | if (remainder > 0) { | |
610 | reg_val = 0; | |
3a70dd2d PH |
611 | memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); |
612 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); | |
613 | } | |
de327e49 NB |
614 | } |
615 | ||
a568231f LL |
616 | mtk_spi_enable_transfer(master); |
617 | ||
618 | return 1; | |
619 | } | |
620 | ||
621 | static int mtk_spi_dma_transfer(struct spi_master *master, | |
622 | struct spi_device *spi, | |
623 | struct spi_transfer *xfer) | |
624 | { | |
625 | int cmd; | |
626 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
627 | ||
628 | mdata->tx_sgl = NULL; | |
629 | mdata->rx_sgl = NULL; | |
630 | mdata->tx_sgl_len = 0; | |
631 | mdata->rx_sgl_len = 0; | |
632 | mdata->cur_transfer = xfer; | |
00bca73b | 633 | mdata->num_xfered = 0; |
a568231f | 634 | |
7e963fb2 | 635 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
a568231f LL |
636 | |
637 | cmd = readl(mdata->base + SPI_CMD_REG); | |
638 | if (xfer->tx_buf) | |
639 | cmd |= SPI_CMD_TX_DMA; | |
640 | if (xfer->rx_buf) | |
641 | cmd |= SPI_CMD_RX_DMA; | |
642 | writel(cmd, mdata->base + SPI_CMD_REG); | |
643 | ||
644 | if (xfer->tx_buf) | |
645 | mdata->tx_sgl = xfer->tx_sg.sgl; | |
646 | if (xfer->rx_buf) | |
647 | mdata->rx_sgl = xfer->rx_sg.sgl; | |
648 | ||
649 | if (mdata->tx_sgl) { | |
650 | xfer->tx_dma = sg_dma_address(mdata->tx_sgl); | |
651 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
652 | } | |
653 | if (mdata->rx_sgl) { | |
654 | xfer->rx_dma = sg_dma_address(mdata->rx_sgl); | |
655 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
656 | } | |
657 | ||
658 | mtk_spi_update_mdata_len(master); | |
659 | mtk_spi_setup_packet(master); | |
660 | mtk_spi_setup_dma_addr(master, xfer); | |
661 | mtk_spi_enable_transfer(master); | |
662 | ||
663 | return 1; | |
664 | } | |
665 | ||
666 | static int mtk_spi_transfer_one(struct spi_master *master, | |
667 | struct spi_device *spi, | |
668 | struct spi_transfer *xfer) | |
669 | { | |
7e963fb2 LL |
670 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
671 | u32 reg_val = 0; | |
672 | ||
673 | /* prepare xfer direction and duplex mode */ | |
674 | if (mdata->dev_comp->ipm_design) { | |
675 | if (!xfer->tx_buf || !xfer->rx_buf) { | |
676 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; | |
677 | if (xfer->rx_buf) | |
678 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; | |
679 | } | |
680 | writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); | |
681 | } | |
682 | ||
a568231f LL |
683 | if (master->can_dma(master, spi, xfer)) |
684 | return mtk_spi_dma_transfer(master, spi, xfer); | |
685 | else | |
686 | return mtk_spi_fifo_transfer(master, spi, xfer); | |
687 | } | |
688 | ||
689 | static bool mtk_spi_can_dma(struct spi_master *master, | |
690 | struct spi_device *spi, | |
691 | struct spi_transfer *xfer) | |
692 | { | |
1ce24864 DK |
693 | /* Buffers for DMA transactions must be 4-byte aligned */ |
694 | return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && | |
695 | (unsigned long)xfer->tx_buf % 4 == 0 && | |
696 | (unsigned long)xfer->rx_buf % 4 == 0); | |
a568231f LL |
697 | } |
698 | ||
58a984c7 LL |
699 | static int mtk_spi_setup(struct spi_device *spi) |
700 | { | |
701 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
702 | ||
703 | if (!spi->controller_data) | |
704 | spi->controller_data = (void *)&mtk_default_chip_info; | |
705 | ||
1a5a87d5 LW |
706 | if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) |
707 | /* CS de-asserted, gpiolib will handle inversion */ | |
708 | gpiod_direction_output(spi->cs_gpiod, 0); | |
37457607 | 709 | |
58a984c7 LL |
710 | return 0; |
711 | } | |
712 | ||
a568231f LL |
713 | static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) |
714 | { | |
00bca73b | 715 | u32 cmd, reg_val, cnt, remainder, len; |
a568231f LL |
716 | struct spi_master *master = dev_id; |
717 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
718 | struct spi_transfer *trans = mdata->cur_transfer; | |
719 | ||
720 | reg_val = readl(mdata->base + SPI_STATUS0_REG); | |
50f8fec2 | 721 | if (reg_val & MTK_SPI_PAUSE_INT_STATUS) |
a568231f LL |
722 | mdata->state = MTK_SPI_PAUSED; |
723 | else | |
724 | mdata->state = MTK_SPI_IDLE; | |
725 | ||
9f763fd2 LL |
726 | /* SPI-MEM ops */ |
727 | if (mdata->use_spimem) { | |
728 | complete(&mdata->spimem_done); | |
729 | return IRQ_HANDLED; | |
730 | } | |
731 | ||
f83a96e5 | 732 | if (!master->can_dma(master, NULL, trans)) { |
a568231f | 733 | if (trans->rx_buf) { |
de327e49 | 734 | cnt = mdata->xfer_len / 4; |
44f636da | 735 | ioread32_rep(mdata->base + SPI_RX_DATA_REG, |
00bca73b | 736 | trans->rx_buf + mdata->num_xfered, cnt); |
de327e49 NB |
737 | remainder = mdata->xfer_len % 4; |
738 | if (remainder > 0) { | |
739 | reg_val = readl(mdata->base + SPI_RX_DATA_REG); | |
00bca73b PS |
740 | memcpy(trans->rx_buf + |
741 | mdata->num_xfered + | |
742 | (cnt * 4), | |
743 | ®_val, | |
744 | remainder); | |
de327e49 | 745 | } |
a568231f | 746 | } |
1ce24864 | 747 | |
00bca73b PS |
748 | mdata->num_xfered += mdata->xfer_len; |
749 | if (mdata->num_xfered == trans->len) { | |
1ce24864 DK |
750 | spi_finalize_current_transfer(master); |
751 | return IRQ_HANDLED; | |
752 | } | |
753 | ||
00bca73b PS |
754 | len = trans->len - mdata->num_xfered; |
755 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); | |
1ce24864 DK |
756 | mtk_spi_setup_packet(master); |
757 | ||
a4d8f64f | 758 | cnt = mdata->xfer_len / 4; |
00bca73b PS |
759 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, |
760 | trans->tx_buf + mdata->num_xfered, cnt); | |
1ce24864 | 761 | |
a4d8f64f | 762 | remainder = mdata->xfer_len % 4; |
1ce24864 DK |
763 | if (remainder > 0) { |
764 | reg_val = 0; | |
00bca73b PS |
765 | memcpy(®_val, |
766 | trans->tx_buf + (cnt * 4) + mdata->num_xfered, | |
767 | remainder); | |
1ce24864 DK |
768 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); |
769 | } | |
770 | ||
771 | mtk_spi_enable_transfer(master); | |
772 | ||
a568231f LL |
773 | return IRQ_HANDLED; |
774 | } | |
775 | ||
776 | if (mdata->tx_sgl) | |
777 | trans->tx_dma += mdata->xfer_len; | |
778 | if (mdata->rx_sgl) | |
779 | trans->rx_dma += mdata->xfer_len; | |
780 | ||
781 | if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { | |
782 | mdata->tx_sgl = sg_next(mdata->tx_sgl); | |
783 | if (mdata->tx_sgl) { | |
784 | trans->tx_dma = sg_dma_address(mdata->tx_sgl); | |
785 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
786 | } | |
787 | } | |
788 | if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { | |
789 | mdata->rx_sgl = sg_next(mdata->rx_sgl); | |
790 | if (mdata->rx_sgl) { | |
791 | trans->rx_dma = sg_dma_address(mdata->rx_sgl); | |
792 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
793 | } | |
794 | } | |
795 | ||
796 | if (!mdata->tx_sgl && !mdata->rx_sgl) { | |
797 | /* spi disable dma */ | |
798 | cmd = readl(mdata->base + SPI_CMD_REG); | |
799 | cmd &= ~SPI_CMD_TX_DMA; | |
800 | cmd &= ~SPI_CMD_RX_DMA; | |
801 | writel(cmd, mdata->base + SPI_CMD_REG); | |
802 | ||
803 | spi_finalize_current_transfer(master); | |
804 | return IRQ_HANDLED; | |
805 | } | |
806 | ||
807 | mtk_spi_update_mdata_len(master); | |
808 | mtk_spi_setup_packet(master); | |
809 | mtk_spi_setup_dma_addr(master, trans); | |
810 | mtk_spi_enable_transfer(master); | |
811 | ||
812 | return IRQ_HANDLED; | |
813 | } | |
814 | ||
9f763fd2 LL |
815 | static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, |
816 | struct spi_mem_op *op) | |
817 | { | |
818 | int opcode_len; | |
819 | ||
820 | if (op->data.dir != SPI_MEM_NO_DATA) { | |
821 | opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; | |
822 | if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { | |
823 | op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; | |
824 | /* force data buffer dma-aligned. */ | |
825 | op->data.nbytes -= op->data.nbytes % 4; | |
826 | } | |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static bool mtk_spi_mem_supports_op(struct spi_mem *mem, | |
833 | const struct spi_mem_op *op) | |
834 | { | |
835 | if (!spi_mem_default_supports_op(mem, op)) | |
836 | return false; | |
837 | ||
838 | if (op->addr.nbytes && op->dummy.nbytes && | |
839 | op->addr.buswidth != op->dummy.buswidth) | |
840 | return false; | |
841 | ||
842 | if (op->addr.nbytes + op->dummy.nbytes > 16) | |
843 | return false; | |
844 | ||
845 | if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { | |
846 | if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > | |
847 | MTK_SPI_IPM_PACKET_LOOP || | |
848 | op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) | |
849 | return false; | |
850 | } | |
851 | ||
852 | return true; | |
853 | } | |
854 | ||
855 | static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, | |
856 | const struct spi_mem_op *op) | |
857 | { | |
858 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
859 | ||
860 | writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), | |
861 | mdata->base + SPI_TX_SRC_REG); | |
862 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
863 | if (mdata->dev_comp->dma_ext) | |
864 | writel((u32)(mdata->tx_dma >> 32), | |
865 | mdata->base + SPI_TX_SRC_REG_64); | |
866 | #endif | |
867 | ||
868 | if (op->data.dir == SPI_MEM_DATA_IN) { | |
869 | writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), | |
870 | mdata->base + SPI_RX_DST_REG); | |
871 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
872 | if (mdata->dev_comp->dma_ext) | |
873 | writel((u32)(mdata->rx_dma >> 32), | |
874 | mdata->base + SPI_RX_DST_REG_64); | |
875 | #endif | |
876 | } | |
877 | } | |
878 | ||
879 | static int mtk_spi_transfer_wait(struct spi_mem *mem, | |
880 | const struct spi_mem_op *op) | |
881 | { | |
882 | struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); | |
883 | /* | |
884 | * For each byte we wait for 8 cycles of the SPI clock. | |
885 | * Since speed is defined in Hz and we want milliseconds, | |
886 | * so it should be 8 * 1000. | |
887 | */ | |
888 | u64 ms = 8000LL; | |
889 | ||
890 | if (op->data.dir == SPI_MEM_NO_DATA) | |
891 | ms *= 32; /* prevent we may get 0 for short transfers. */ | |
892 | else | |
893 | ms *= op->data.nbytes; | |
894 | ms = div_u64(ms, mem->spi->max_speed_hz); | |
895 | ms += ms + 1000; /* 1s tolerance */ | |
896 | ||
897 | if (ms > UINT_MAX) | |
898 | ms = UINT_MAX; | |
899 | ||
900 | if (!wait_for_completion_timeout(&mdata->spimem_done, | |
901 | msecs_to_jiffies(ms))) { | |
902 | dev_err(mdata->dev, "spi-mem transfer timeout\n"); | |
903 | return -ETIMEDOUT; | |
904 | } | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | static int mtk_spi_mem_exec_op(struct spi_mem *mem, | |
910 | const struct spi_mem_op *op) | |
911 | { | |
912 | struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); | |
913 | u32 reg_val, nio, tx_size; | |
914 | char *tx_tmp_buf, *rx_tmp_buf; | |
915 | int ret = 0; | |
916 | ||
917 | mdata->use_spimem = true; | |
918 | reinit_completion(&mdata->spimem_done); | |
919 | ||
920 | mtk_spi_reset(mdata); | |
921 | mtk_spi_hw_init(mem->spi->master, mem->spi); | |
922 | mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); | |
923 | ||
924 | reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); | |
925 | /* opcode byte len */ | |
926 | reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; | |
927 | reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; | |
928 | ||
929 | /* addr & dummy byte len */ | |
930 | reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; | |
931 | if (op->addr.nbytes || op->dummy.nbytes) | |
932 | reg_val |= (op->addr.nbytes + op->dummy.nbytes) << | |
933 | SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; | |
934 | ||
935 | /* data byte len */ | |
936 | if (op->data.dir == SPI_MEM_NO_DATA) { | |
937 | reg_val |= SPI_CFG3_IPM_NODATA_FLAG; | |
938 | writel(0, mdata->base + SPI_CFG1_REG); | |
939 | } else { | |
940 | reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; | |
941 | mdata->xfer_len = op->data.nbytes; | |
942 | mtk_spi_setup_packet(mem->spi->master); | |
943 | } | |
944 | ||
945 | if (op->addr.nbytes || op->dummy.nbytes) { | |
946 | if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) | |
947 | reg_val |= SPI_CFG3_IPM_XMODE_EN; | |
948 | else | |
949 | reg_val &= ~SPI_CFG3_IPM_XMODE_EN; | |
950 | } | |
951 | ||
952 | if (op->addr.buswidth == 2 || | |
953 | op->dummy.buswidth == 2 || | |
954 | op->data.buswidth == 2) | |
955 | nio = 2; | |
956 | else if (op->addr.buswidth == 4 || | |
957 | op->dummy.buswidth == 4 || | |
958 | op->data.buswidth == 4) | |
959 | nio = 4; | |
960 | else | |
961 | nio = 1; | |
962 | ||
963 | reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; | |
964 | reg_val |= PIN_MODE_CFG(nio); | |
965 | ||
966 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; | |
967 | if (op->data.dir == SPI_MEM_DATA_IN) | |
968 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; | |
969 | else | |
970 | reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; | |
971 | writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); | |
972 | ||
973 | tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; | |
974 | if (op->data.dir == SPI_MEM_DATA_OUT) | |
975 | tx_size += op->data.nbytes; | |
976 | ||
977 | tx_size = max_t(u32, tx_size, 32); | |
978 | ||
979 | tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); | |
980 | if (!tx_tmp_buf) { | |
981 | mdata->use_spimem = false; | |
982 | return -ENOMEM; | |
983 | } | |
984 | ||
985 | tx_tmp_buf[0] = op->cmd.opcode; | |
986 | ||
987 | if (op->addr.nbytes) { | |
988 | int i; | |
989 | ||
990 | for (i = 0; i < op->addr.nbytes; i++) | |
991 | tx_tmp_buf[i + 1] = op->addr.val >> | |
992 | (8 * (op->addr.nbytes - i - 1)); | |
993 | } | |
994 | ||
995 | if (op->dummy.nbytes) | |
996 | memset(tx_tmp_buf + op->addr.nbytes + 1, | |
997 | 0xff, | |
998 | op->dummy.nbytes); | |
999 | ||
1000 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) | |
1001 | memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, | |
1002 | op->data.buf.out, | |
1003 | op->data.nbytes); | |
1004 | ||
1005 | mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, | |
1006 | tx_size, DMA_TO_DEVICE); | |
1007 | if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { | |
1008 | ret = -ENOMEM; | |
1009 | goto err_exit; | |
1010 | } | |
1011 | ||
1012 | if (op->data.dir == SPI_MEM_DATA_IN) { | |
1013 | if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { | |
1014 | rx_tmp_buf = kzalloc(op->data.nbytes, | |
1015 | GFP_KERNEL | GFP_DMA); | |
1016 | if (!rx_tmp_buf) { | |
1017 | ret = -ENOMEM; | |
1018 | goto unmap_tx_dma; | |
1019 | } | |
1020 | } else { | |
1021 | rx_tmp_buf = op->data.buf.in; | |
1022 | } | |
1023 | ||
1024 | mdata->rx_dma = dma_map_single(mdata->dev, | |
1025 | rx_tmp_buf, | |
1026 | op->data.nbytes, | |
1027 | DMA_FROM_DEVICE); | |
1028 | if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { | |
1029 | ret = -ENOMEM; | |
1030 | goto kfree_rx_tmp_buf; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
1035 | reg_val |= SPI_CMD_TX_DMA; | |
1036 | if (op->data.dir == SPI_MEM_DATA_IN) | |
1037 | reg_val |= SPI_CMD_RX_DMA; | |
1038 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
1039 | ||
1040 | mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); | |
1041 | ||
1042 | mtk_spi_enable_transfer(mem->spi->master); | |
1043 | ||
1044 | /* Wait for the interrupt. */ | |
1045 | ret = mtk_spi_transfer_wait(mem, op); | |
1046 | if (ret) | |
1047 | goto unmap_rx_dma; | |
1048 | ||
1049 | /* spi disable dma */ | |
1050 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
1051 | reg_val &= ~SPI_CMD_TX_DMA; | |
1052 | if (op->data.dir == SPI_MEM_DATA_IN) | |
1053 | reg_val &= ~SPI_CMD_RX_DMA; | |
1054 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
1055 | ||
1056 | unmap_rx_dma: | |
1057 | if (op->data.dir == SPI_MEM_DATA_IN) { | |
1058 | dma_unmap_single(mdata->dev, mdata->rx_dma, | |
1059 | op->data.nbytes, DMA_FROM_DEVICE); | |
1060 | if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) | |
1061 | memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); | |
1062 | } | |
1063 | kfree_rx_tmp_buf: | |
1064 | if (op->data.dir == SPI_MEM_DATA_IN && | |
1065 | !IS_ALIGNED((size_t)op->data.buf.in, 4)) | |
1066 | kfree(rx_tmp_buf); | |
1067 | unmap_tx_dma: | |
1068 | dma_unmap_single(mdata->dev, mdata->tx_dma, | |
1069 | tx_size, DMA_TO_DEVICE); | |
1070 | err_exit: | |
1071 | kfree(tx_tmp_buf); | |
1072 | mdata->use_spimem = false; | |
1073 | ||
1074 | return ret; | |
1075 | } | |
1076 | ||
1077 | static const struct spi_controller_mem_ops mtk_spi_mem_ops = { | |
1078 | .adjust_op_size = mtk_spi_mem_adjust_op_size, | |
1079 | .supports_op = mtk_spi_mem_supports_op, | |
1080 | .exec_op = mtk_spi_mem_exec_op, | |
1081 | }; | |
1082 | ||
a568231f LL |
1083 | static int mtk_spi_probe(struct platform_device *pdev) |
1084 | { | |
6b444058 | 1085 | struct device *dev = &pdev->dev; |
a568231f LL |
1086 | struct spi_master *master; |
1087 | struct mtk_spi *mdata; | |
fdeae8f5 | 1088 | int i, irq, ret, addr_bits; |
a568231f | 1089 | |
6b444058 | 1090 | master = devm_spi_alloc_master(dev, sizeof(*mdata)); |
a568231f | 1091 | if (!master) { |
6b444058 | 1092 | dev_err(dev, "failed to alloc spi master\n"); |
a568231f LL |
1093 | return -ENOMEM; |
1094 | } | |
1095 | ||
1096 | master->auto_runtime_pm = true; | |
6b444058 | 1097 | master->dev.of_node = dev->of_node; |
3e582c6e | 1098 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
a568231f LL |
1099 | |
1100 | master->set_cs = mtk_spi_set_cs; | |
a568231f LL |
1101 | master->prepare_message = mtk_spi_prepare_message; |
1102 | master->transfer_one = mtk_spi_transfer_one; | |
1103 | master->can_dma = mtk_spi_can_dma; | |
58a984c7 | 1104 | master->setup = mtk_spi_setup; |
9f6e7e8d | 1105 | master->set_cs_timing = mtk_spi_set_hw_cs_timing; |
1a5a87d5 | 1106 | master->use_gpio_descriptors = true; |
a568231f | 1107 | |
a568231f | 1108 | mdata = spi_master_get_devdata(master); |
6b444058 | 1109 | mdata->dev_comp = device_get_match_data(dev); |
ae7c2d34 LX |
1110 | |
1111 | if (mdata->dev_comp->enhance_timing) | |
1112 | master->mode_bits |= SPI_CS_HIGH; | |
1113 | ||
a568231f LL |
1114 | if (mdata->dev_comp->must_tx) |
1115 | master->flags = SPI_MASTER_MUST_TX; | |
7e963fb2 LL |
1116 | if (mdata->dev_comp->ipm_design) |
1117 | master->mode_bits |= SPI_LOOP; | |
a568231f | 1118 | |
9f763fd2 | 1119 | if (mdata->dev_comp->ipm_design) { |
6b444058 | 1120 | mdata->dev = dev; |
9f763fd2 LL |
1121 | master->mem_ops = &mtk_spi_mem_ops; |
1122 | init_completion(&mdata->spimem_done); | |
1123 | } | |
1124 | ||
a568231f | 1125 | if (mdata->dev_comp->need_pad_sel) { |
6b444058 | 1126 | mdata->pad_num = of_property_count_u32_elems(dev->of_node, |
37457607 LL |
1127 | "mediatek,pad-select"); |
1128 | if (mdata->pad_num < 0) { | |
6b444058 | 1129 | dev_err(dev, |
37457607 | 1130 | "No 'mediatek,pad-select' property\n"); |
ace14580 | 1131 | return -EINVAL; |
a568231f LL |
1132 | } |
1133 | ||
6b444058 | 1134 | mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, |
37457607 | 1135 | sizeof(u32), GFP_KERNEL); |
ace14580 ADR |
1136 | if (!mdata->pad_sel) |
1137 | return -ENOMEM; | |
37457607 LL |
1138 | |
1139 | for (i = 0; i < mdata->pad_num; i++) { | |
6b444058 | 1140 | of_property_read_u32_index(dev->of_node, |
37457607 LL |
1141 | "mediatek,pad-select", |
1142 | i, &mdata->pad_sel[i]); | |
1143 | if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { | |
6b444058 | 1144 | dev_err(dev, "wrong pad-sel[%d]: %u\n", |
37457607 | 1145 | i, mdata->pad_sel[i]); |
ace14580 | 1146 | return -EINVAL; |
37457607 LL |
1147 | } |
1148 | } | |
a568231f LL |
1149 | } |
1150 | ||
1151 | platform_set_drvdata(pdev, master); | |
5dd381e7 | 1152 | mdata->base = devm_platform_ioremap_resource(pdev, 0); |
ace14580 ADR |
1153 | if (IS_ERR(mdata->base)) |
1154 | return PTR_ERR(mdata->base); | |
a568231f LL |
1155 | |
1156 | irq = platform_get_irq(pdev, 0); | |
ace14580 ADR |
1157 | if (irq < 0) |
1158 | return irq; | |
a568231f | 1159 | |
6b444058 ADR |
1160 | if (!dev->dma_mask) |
1161 | dev->dma_mask = &dev->coherent_dma_mask; | |
a568231f | 1162 | |
6b444058 ADR |
1163 | ret = devm_request_irq(dev, irq, mtk_spi_interrupt, |
1164 | IRQF_TRIGGER_NONE, dev_name(dev), master); | |
a568231f | 1165 | if (ret) { |
6b444058 | 1166 | dev_err(dev, "failed to register irq (%d)\n", ret); |
ace14580 | 1167 | return ret; |
a568231f LL |
1168 | } |
1169 | ||
6b444058 | 1170 | mdata->parent_clk = devm_clk_get(dev, "parent-clk"); |
a568231f LL |
1171 | if (IS_ERR(mdata->parent_clk)) { |
1172 | ret = PTR_ERR(mdata->parent_clk); | |
6b444058 | 1173 | dev_err(dev, "failed to get parent-clk: %d\n", ret); |
ace14580 | 1174 | return ret; |
a568231f LL |
1175 | } |
1176 | ||
6b444058 | 1177 | mdata->sel_clk = devm_clk_get(dev, "sel-clk"); |
adcbcfea | 1178 | if (IS_ERR(mdata->sel_clk)) { |
e26d15f7 | 1179 | ret = PTR_ERR(mdata->sel_clk); |
6b444058 | 1180 | dev_err(dev, "failed to get sel-clk: %d\n", ret); |
ace14580 | 1181 | return ret; |
a568231f LL |
1182 | } |
1183 | ||
6b444058 | 1184 | mdata->spi_clk = devm_clk_get(dev, "spi-clk"); |
adcbcfea | 1185 | if (IS_ERR(mdata->spi_clk)) { |
e26d15f7 | 1186 | ret = PTR_ERR(mdata->spi_clk); |
6b444058 | 1187 | dev_err(dev, "failed to get spi-clk: %d\n", ret); |
ace14580 | 1188 | return ret; |
a568231f LL |
1189 | } |
1190 | ||
6b444058 | 1191 | mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); |
a740f4e6 LL |
1192 | if (IS_ERR(mdata->spi_hclk)) { |
1193 | ret = PTR_ERR(mdata->spi_hclk); | |
6b444058 | 1194 | dev_err(dev, "failed to get hclk: %d\n", ret); |
ace14580 | 1195 | return ret; |
a740f4e6 LL |
1196 | } |
1197 | ||
1198 | ret = clk_prepare_enable(mdata->spi_hclk); | |
1199 | if (ret < 0) { | |
6b444058 | 1200 | dev_err(dev, "failed to enable hclk (%d)\n", ret); |
ace14580 | 1201 | return ret; |
a740f4e6 LL |
1202 | } |
1203 | ||
a568231f LL |
1204 | ret = clk_prepare_enable(mdata->spi_clk); |
1205 | if (ret < 0) { | |
6b444058 | 1206 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); |
a740f4e6 | 1207 | goto err_disable_spi_hclk; |
a568231f LL |
1208 | } |
1209 | ||
adcbcfea | 1210 | ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); |
a568231f | 1211 | if (ret < 0) { |
6b444058 | 1212 | dev_err(dev, "failed to clk_set_parent (%d)\n", ret); |
a740f4e6 | 1213 | goto err_disable_spi_clk; |
a568231f LL |
1214 | } |
1215 | ||
162a31ef MZ |
1216 | mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); |
1217 | ||
a740f4e6 | 1218 | if (mdata->dev_comp->no_need_unprepare) { |
162a31ef | 1219 | clk_disable(mdata->spi_clk); |
a740f4e6 LL |
1220 | clk_disable(mdata->spi_hclk); |
1221 | } else { | |
162a31ef | 1222 | clk_disable_unprepare(mdata->spi_clk); |
a740f4e6 LL |
1223 | clk_disable_unprepare(mdata->spi_hclk); |
1224 | } | |
a568231f | 1225 | |
6b444058 | 1226 | pm_runtime_enable(dev); |
a568231f | 1227 | |
37457607 LL |
1228 | if (mdata->dev_comp->need_pad_sel) { |
1229 | if (mdata->pad_num != master->num_chipselect) { | |
6b444058 | 1230 | dev_err(dev, |
37457607 LL |
1231 | "pad_num does not match num_chipselect(%d != %d)\n", |
1232 | mdata->pad_num, master->num_chipselect); | |
1233 | ret = -EINVAL; | |
e38da37f | 1234 | goto err_disable_runtime_pm; |
37457607 LL |
1235 | } |
1236 | ||
1a5a87d5 | 1237 | if (!master->cs_gpiods && master->num_chipselect > 1) { |
6b444058 | 1238 | dev_err(dev, |
98c8dccf NB |
1239 | "cs_gpios not specified and num_chipselect > 1\n"); |
1240 | ret = -EINVAL; | |
e38da37f | 1241 | goto err_disable_runtime_pm; |
98c8dccf | 1242 | } |
37457607 LL |
1243 | } |
1244 | ||
fdeae8f5 | 1245 | if (mdata->dev_comp->dma_ext) |
1246 | addr_bits = DMA_ADDR_EXT_BITS; | |
1247 | else | |
1248 | addr_bits = DMA_ADDR_DEF_BITS; | |
6b444058 | 1249 | ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits)); |
fdeae8f5 | 1250 | if (ret) |
6b444058 | 1251 | dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n", |
fdeae8f5 | 1252 | addr_bits, ret); |
1253 | ||
6b444058 | 1254 | ret = devm_spi_register_master(dev, master); |
c934fec1 | 1255 | if (ret) { |
6b444058 | 1256 | dev_err(dev, "failed to register master (%d)\n", ret); |
c934fec1 MZ |
1257 | goto err_disable_runtime_pm; |
1258 | } | |
1259 | ||
a568231f LL |
1260 | return 0; |
1261 | ||
e38da37f | 1262 | err_disable_runtime_pm: |
6b444058 | 1263 | pm_runtime_disable(dev); |
a740f4e6 LL |
1264 | err_disable_spi_clk: |
1265 | clk_disable_unprepare(mdata->spi_clk); | |
1266 | err_disable_spi_hclk: | |
1267 | clk_disable_unprepare(mdata->spi_hclk); | |
a568231f LL |
1268 | |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | static int mtk_spi_remove(struct platform_device *pdev) | |
1273 | { | |
1274 | struct spi_master *master = platform_get_drvdata(pdev); | |
1275 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1276 | ||
1277 | pm_runtime_disable(&pdev->dev); | |
1278 | ||
1279 | mtk_spi_reset(mdata); | |
a568231f | 1280 | |
a740f4e6 | 1281 | if (mdata->dev_comp->no_need_unprepare) { |
162a31ef | 1282 | clk_unprepare(mdata->spi_clk); |
a740f4e6 LL |
1283 | clk_unprepare(mdata->spi_hclk); |
1284 | } | |
162a31ef | 1285 | |
a568231f LL |
1286 | return 0; |
1287 | } | |
1288 | ||
1289 | #ifdef CONFIG_PM_SLEEP | |
1290 | static int mtk_spi_suspend(struct device *dev) | |
1291 | { | |
1292 | int ret; | |
1293 | struct spi_master *master = dev_get_drvdata(dev); | |
1294 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1295 | ||
1296 | ret = spi_master_suspend(master); | |
1297 | if (ret) | |
1298 | return ret; | |
1299 | ||
a740f4e6 | 1300 | if (!pm_runtime_suspended(dev)) { |
a568231f | 1301 | clk_disable_unprepare(mdata->spi_clk); |
a740f4e6 LL |
1302 | clk_disable_unprepare(mdata->spi_hclk); |
1303 | } | |
a568231f LL |
1304 | |
1305 | return ret; | |
1306 | } | |
1307 | ||
1308 | static int mtk_spi_resume(struct device *dev) | |
1309 | { | |
1310 | int ret; | |
1311 | struct spi_master *master = dev_get_drvdata(dev); | |
1312 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1313 | ||
1314 | if (!pm_runtime_suspended(dev)) { | |
1315 | ret = clk_prepare_enable(mdata->spi_clk); | |
13da5a0b LL |
1316 | if (ret < 0) { |
1317 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
a568231f | 1318 | return ret; |
13da5a0b | 1319 | } |
a740f4e6 LL |
1320 | |
1321 | ret = clk_prepare_enable(mdata->spi_hclk); | |
1322 | if (ret < 0) { | |
1323 | dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); | |
1324 | clk_disable_unprepare(mdata->spi_clk); | |
1325 | return ret; | |
1326 | } | |
a568231f LL |
1327 | } |
1328 | ||
1329 | ret = spi_master_resume(master); | |
a740f4e6 | 1330 | if (ret < 0) { |
a568231f | 1331 | clk_disable_unprepare(mdata->spi_clk); |
a740f4e6 LL |
1332 | clk_disable_unprepare(mdata->spi_hclk); |
1333 | } | |
a568231f LL |
1334 | |
1335 | return ret; | |
1336 | } | |
1337 | #endif /* CONFIG_PM_SLEEP */ | |
1338 | ||
1339 | #ifdef CONFIG_PM | |
1340 | static int mtk_spi_runtime_suspend(struct device *dev) | |
1341 | { | |
1342 | struct spi_master *master = dev_get_drvdata(dev); | |
1343 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1344 | ||
a740f4e6 | 1345 | if (mdata->dev_comp->no_need_unprepare) { |
162a31ef | 1346 | clk_disable(mdata->spi_clk); |
a740f4e6 LL |
1347 | clk_disable(mdata->spi_hclk); |
1348 | } else { | |
162a31ef | 1349 | clk_disable_unprepare(mdata->spi_clk); |
a740f4e6 LL |
1350 | clk_disable_unprepare(mdata->spi_hclk); |
1351 | } | |
a568231f LL |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static int mtk_spi_runtime_resume(struct device *dev) | |
1357 | { | |
1358 | struct spi_master *master = dev_get_drvdata(dev); | |
1359 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
13da5a0b LL |
1360 | int ret; |
1361 | ||
a740f4e6 | 1362 | if (mdata->dev_comp->no_need_unprepare) { |
162a31ef | 1363 | ret = clk_enable(mdata->spi_clk); |
a740f4e6 LL |
1364 | if (ret < 0) { |
1365 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
1366 | return ret; | |
1367 | } | |
1368 | ret = clk_enable(mdata->spi_hclk); | |
1369 | if (ret < 0) { | |
1370 | dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); | |
1371 | clk_disable(mdata->spi_clk); | |
1372 | return ret; | |
1373 | } | |
1374 | } else { | |
162a31ef | 1375 | ret = clk_prepare_enable(mdata->spi_clk); |
a740f4e6 LL |
1376 | if (ret < 0) { |
1377 | dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); | |
1378 | return ret; | |
1379 | } | |
1380 | ||
1381 | ret = clk_prepare_enable(mdata->spi_hclk); | |
1382 | if (ret < 0) { | |
1383 | dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); | |
1384 | clk_disable_unprepare(mdata->spi_clk); | |
1385 | return ret; | |
1386 | } | |
13da5a0b | 1387 | } |
a568231f | 1388 | |
13da5a0b | 1389 | return 0; |
a568231f LL |
1390 | } |
1391 | #endif /* CONFIG_PM */ | |
1392 | ||
1393 | static const struct dev_pm_ops mtk_spi_pm = { | |
1394 | SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) | |
1395 | SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, | |
1396 | mtk_spi_runtime_resume, NULL) | |
1397 | }; | |
1398 | ||
4299aaaa | 1399 | static struct platform_driver mtk_spi_driver = { |
a568231f LL |
1400 | .driver = { |
1401 | .name = "mtk-spi", | |
1402 | .pm = &mtk_spi_pm, | |
1403 | .of_match_table = mtk_spi_of_match, | |
1404 | }, | |
1405 | .probe = mtk_spi_probe, | |
1406 | .remove = mtk_spi_remove, | |
1407 | }; | |
1408 | ||
1409 | module_platform_driver(mtk_spi_driver); | |
1410 | ||
1411 | MODULE_DESCRIPTION("MTK SPI Controller driver"); | |
1412 | MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); | |
1413 | MODULE_LICENSE("GPL v2"); | |
e4001885 | 1414 | MODULE_ALIAS("platform:mtk-spi"); |