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Merge tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[linux-2.6-block.git] / drivers / spi / spi-mt65xx.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
a568231f
LL		 2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
a568231f
LL		 5 */
6
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
dd69a0a6 11#include <linux/io.h>
a568231f
LL		 12#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/of.h>
37457607 15#include <linux/of_gpio.h>
a568231f
LL		 16#include <linux/platform_device.h>
17#include <linux/platform_data/spi-mt65xx.h>
18#include <linux/pm_runtime.h>
19#include <linux/spi/spi.h>
fdeae8f5 20#include <linux/dma-mapping.h>
a568231f
LL		 21
22#define SPI_CFG0_REG 0x0000
23#define SPI_CFG1_REG 0x0004
24#define SPI_TX_SRC_REG 0x0008
25#define SPI_RX_DST_REG 0x000c
26#define SPI_TX_DATA_REG 0x0010
27#define SPI_RX_DATA_REG 0x0014
28#define SPI_CMD_REG 0x0018
29#define SPI_STATUS0_REG 0x001c
30#define SPI_PAD_SEL_REG 0x0024
058fe49d 31#define SPI_CFG2_REG 0x0028
fdeae8f5 32#define SPI_TX_SRC_REG_64 0x002c
33#define SPI_RX_DST_REG_64 0x0030
a568231f
LL		 34
35#define SPI_CFG0_SCK_HIGH_OFFSET 0
36#define SPI_CFG0_SCK_LOW_OFFSET 8
37#define SPI_CFG0_CS_HOLD_OFFSET 16
38#define SPI_CFG0_CS_SETUP_OFFSET 24
058fe49d
LL		 39#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
40#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
a568231f
LL		 41
42#define SPI_CFG1_CS_IDLE_OFFSET 0
43#define SPI_CFG1_PACKET_LOOP_OFFSET 8
44#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
46
47#define SPI_CFG1_CS_IDLE_MASK 0xff
48#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
49#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
44b37eb7 50#define SPI_CFG2_SCK_HIGH_OFFSET 0
51#define SPI_CFG2_SCK_LOW_OFFSET 16
a568231f 52
a71d6ea6
LL		 53#define SPI_CMD_ACT BIT(0)
54#define SPI_CMD_RESUME BIT(1)
a568231f
LL		 55#define SPI_CMD_RST BIT(2)
56#define SPI_CMD_PAUSE_EN BIT(4)
57#define SPI_CMD_DEASSERT BIT(5)
058fe49d
LL		 58#define SPI_CMD_SAMPLE_SEL BIT(6)
59#define SPI_CMD_CS_POL BIT(7)
a568231f
LL		 60#define SPI_CMD_CPHA BIT(8)
61#define SPI_CMD_CPOL BIT(9)
62#define SPI_CMD_RX_DMA BIT(10)
63#define SPI_CMD_TX_DMA BIT(11)
64#define SPI_CMD_TXMSBF BIT(12)
65#define SPI_CMD_RXMSBF BIT(13)
66#define SPI_CMD_RX_ENDIAN BIT(14)
67#define SPI_CMD_TX_ENDIAN BIT(15)
68#define SPI_CMD_FINISH_IE BIT(16)
69#define SPI_CMD_PAUSE_IE BIT(17)
70
a568231f
LL		 71#define MT8173_SPI_MAX_PAD_SEL 3
72
50f8fec2
LL		 73#define MTK_SPI_PAUSE_INT_STATUS 0x2
74
a568231f
LL		 75#define MTK_SPI_IDLE 0
76#define MTK_SPI_PAUSED 1
77
1ce24864 78#define MTK_SPI_MAX_FIFO_SIZE 32U
a568231f 79#define MTK_SPI_PACKET_SIZE 1024
fdeae8f5 80#define MTK_SPI_32BITS_MASK (0xffffffff)
81
82#define DMA_ADDR_EXT_BITS (36)
83#define DMA_ADDR_DEF_BITS (32)
a568231f
LL		 84
85struct mtk_spi_compatible {
af57937e
LL		 86 bool need_pad_sel;
87 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
88 bool must_tx;
058fe49d
LL		 89 /* some IC design adjust cfg register to enhance time accuracy */
90 bool enhance_timing;
fdeae8f5 91 /* some IC support DMA addr extension */
92 bool dma_ext;
a568231f
LL		 93};
94
95struct mtk_spi {
96 void __iomem *base;
97 u32 state;
37457607
LL		 98 int pad_num;
99 u32 *pad_sel;
adcbcfea 100 struct clk *parent_clk, *sel_clk, *spi_clk;
a568231f
LL		 101 struct spi_transfer *cur_transfer;
102 u32 xfer_len;
00bca73b 103 u32 num_xfered;
a568231f
LL		 104 struct scatterlist *tx_sgl, *rx_sgl;
105 u32 tx_sgl_len, rx_sgl_len;
106 const struct mtk_spi_compatible *dev_comp;
107};
108
4eaf6f73 109static const struct mtk_spi_compatible mtk_common_compat;
fc4f226f 110
b6b1f2d9 111static const struct mtk_spi_compatible mt2712_compat = {
112 .must_tx = true,
113};
114
2c231e0a 115static const struct mtk_spi_compatible mt6765_compat = {
116 .need_pad_sel = true,
117 .must_tx = true,
118 .enhance_timing = true,
fdeae8f5 119 .dma_ext = true,
2c231e0a 120};
121
fc4f226f
LL		 122static const struct mtk_spi_compatible mt7622_compat = {
123 .must_tx = true,
124 .enhance_timing = true,
125};
126
a568231f 127static const struct mtk_spi_compatible mt8173_compat = {
af57937e
LL		 128 .need_pad_sel = true,
129 .must_tx = true,
a568231f
LL		 130};
131
b654aa6f
LL		 132static const struct mtk_spi_compatible mt8183_compat = {
133 .need_pad_sel = true,
134 .must_tx = true,
135 .enhance_timing = true,
136};
137
a568231f
LL		 138/*
139 * A piece of default chip info unless the platform
140 * supplies it.
141 */
142static const struct mtk_chip_config mtk_default_chip_info = {
058fe49d 143 .sample_sel = 0,
a568231f
LL		 144};
145
146static const struct of_device_id mtk_spi_of_match[] = {
15bcdefd
LL		 147 { .compatible = "mediatek,mt2701-spi",
148 .data = (void *)&mtk_common_compat,
149 },
b6b1f2d9 150 { .compatible = "mediatek,mt2712-spi",
151 .data = (void *)&mt2712_compat,
152 },
4eaf6f73
LL		 153 { .compatible = "mediatek,mt6589-spi",
154 .data = (void *)&mtk_common_compat,
155 },
2c231e0a 156 { .compatible = "mediatek,mt6765-spi",
157 .data = (void *)&mt6765_compat,
158 },
fc4f226f
LL		 159 { .compatible = "mediatek,mt7622-spi",
160 .data = (void *)&mt7622_compat,
161 },
942779c6
LL		 162 { .compatible = "mediatek,mt7629-spi",
163 .data = (void *)&mt7622_compat,
164 },
4eaf6f73
LL		 165 { .compatible = "mediatek,mt8135-spi",
166 .data = (void *)&mtk_common_compat,
167 },
168 { .compatible = "mediatek,mt8173-spi",
169 .data = (void *)&mt8173_compat,
170 },
b654aa6f
LL		 171 { .compatible = "mediatek,mt8183-spi",
172 .data = (void *)&mt8183_compat,
173 },
8cf125c4 174 { .compatible = "mediatek,mt8192-spi",
175 .data = (void *)&mt6765_compat,
176 },
a568231f
LL		 177 {}
178};
179MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
180
181static void mtk_spi_reset(struct mtk_spi *mdata)
182{
183 u32 reg_val;
184
185 /* set the software reset bit in SPI_CMD_REG. */
186 reg_val = readl(mdata->base + SPI_CMD_REG);
187 reg_val |= SPI_CMD_RST;
188 writel(reg_val, mdata->base + SPI_CMD_REG);
189
190 reg_val = readl(mdata->base + SPI_CMD_REG);
191 reg_val &= ~SPI_CMD_RST;
192 writel(reg_val, mdata->base + SPI_CMD_REG);
193}
194
79b5d3f2
LL		 195static int mtk_spi_prepare_message(struct spi_master *master,
196 struct spi_message *msg)
a568231f 197{
79b5d3f2 198 u16 cpha, cpol;
a568231f 199 u32 reg_val;
79b5d3f2 200 struct spi_device *spi = msg->spi;
58a984c7 201 struct mtk_chip_config *chip_config = spi->controller_data;
79b5d3f2
LL		 202 struct mtk_spi *mdata = spi_master_get_devdata(master);
203
204 cpha = spi->mode & SPI_CPHA ? 1 : 0;
205 cpol = spi->mode & SPI_CPOL ? 1 : 0;
206
79b5d3f2
LL		 207 reg_val = readl(mdata->base + SPI_CMD_REG);
208 if (cpha)
209 reg_val |= SPI_CMD_CPHA;
210 else
211 reg_val &= ~SPI_CMD_CPHA;
212 if (cpol)
213 reg_val |= SPI_CMD_CPOL;
214 else
215 reg_val &= ~SPI_CMD_CPOL;
a568231f
LL		 216
217 /* set the mlsbx and mlsbtx */
3e582c6e 218 if (spi->mode & SPI_LSB_FIRST) {
a71d6ea6 219 reg_val &= ~SPI_CMD_TXMSBF;
a71d6ea6 220 reg_val &= ~SPI_CMD_RXMSBF;
3e582c6e
LL		 221 } else {
222 reg_val |= SPI_CMD_TXMSBF;
223 reg_val |= SPI_CMD_RXMSBF;
224 }
a568231f
LL		 225
226 /* set the tx/rx endian */
44f636da
LL		 227#ifdef __LITTLE_ENDIAN
228 reg_val &= ~SPI_CMD_TX_ENDIAN;
229 reg_val &= ~SPI_CMD_RX_ENDIAN;
230#else
231 reg_val |= SPI_CMD_TX_ENDIAN;
232 reg_val |= SPI_CMD_RX_ENDIAN;
233#endif
a568231f 234
058fe49d 235 if (mdata->dev_comp->enhance_timing) {
ae7c2d34
LX		 236 /* set CS polarity */
237 if (spi->mode & SPI_CS_HIGH)
058fe49d
LL		 238 reg_val |= SPI_CMD_CS_POL;
239 else
240 reg_val &= ~SPI_CMD_CS_POL;
ae7c2d34 241
058fe49d
LL		 242 if (chip_config->sample_sel)
243 reg_val |= SPI_CMD_SAMPLE_SEL;
244 else
245 reg_val &= ~SPI_CMD_SAMPLE_SEL;
246 }
247
a568231f 248 /* set finish and pause interrupt always enable */
15293324 249 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
a568231f
LL		 250
251 /* disable dma mode */
252 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
253
254 /* disable deassert mode */
255 reg_val &= ~SPI_CMD_DEASSERT;
256
257 writel(reg_val, mdata->base + SPI_CMD_REG);
258
259 /* pad select */
260 if (mdata->dev_comp->need_pad_sel)
37457607
LL		 261 writel(mdata->pad_sel[spi->chip_select],
262 mdata->base + SPI_PAD_SEL_REG);
a568231f
LL		 263
264 return 0;
265}
266
267static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
268{
269 u32 reg_val;
270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
271
ae7c2d34
LX		 272 if (spi->mode & SPI_CS_HIGH)
273 enable = !enable;
274
a568231f 275 reg_val = readl(mdata->base + SPI_CMD_REG);
6583d203 276 if (!enable) {
a568231f 277 reg_val |= SPI_CMD_PAUSE_EN;
6583d203
LL		 278 writel(reg_val, mdata->base + SPI_CMD_REG);
279 } else {
a568231f 280 reg_val &= ~SPI_CMD_PAUSE_EN;
6583d203
LL		 281 writel(reg_val, mdata->base + SPI_CMD_REG);
282 mdata->state = MTK_SPI_IDLE;
283 mtk_spi_reset(mdata);
284 }
a568231f
LL		 285}
286
287static void mtk_spi_prepare_transfer(struct spi_master *master,
288 struct spi_transfer *xfer)
289{
9f6e7e8d 290 u32 spi_clk_hz, div, sck_time, reg_val;
a568231f
LL		 291 struct mtk_spi *mdata = spi_master_get_devdata(master);
292
293 spi_clk_hz = clk_get_rate(mdata->spi_clk);
294 if (xfer->speed_hz < spi_clk_hz / 2)
295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
296 else
297 div = 1;
298
2ce0acf5 299 sck_time = (div + 1) / 2;
a568231f 300
058fe49d 301 if (mdata->dev_comp->enhance_timing) {
9f6e7e8d 302 reg_val = readl(mdata->base + SPI_CFG2_REG);
303 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
304 reg_val |= (((sck_time - 1) & 0xffff)
44b37eb7 305 << SPI_CFG2_SCK_HIGH_OFFSET);
9f6e7e8d 306 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
058fe49d 307 reg_val |= (((sck_time - 1) & 0xffff)
44b37eb7 308 << SPI_CFG2_SCK_LOW_OFFSET);
058fe49d 309 writel(reg_val, mdata->base + SPI_CFG2_REG);
058fe49d 310 } else {
9f6e7e8d 311 reg_val = readl(mdata->base + SPI_CFG0_REG);
312 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
313 reg_val |= (((sck_time - 1) & 0xff)
058fe49d 314 << SPI_CFG0_SCK_HIGH_OFFSET);
9f6e7e8d 315 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
058fe49d 316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
058fe49d
LL		 317 writel(reg_val, mdata->base + SPI_CFG0_REG);
318 }
a568231f
LL		 319}
320
321static void mtk_spi_setup_packet(struct spi_master *master)
322{
323 u32 packet_size, packet_loop, reg_val;
324 struct mtk_spi *mdata = spi_master_get_devdata(master);
325
50f8fec2 326 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
a568231f
LL		 327 packet_loop = mdata->xfer_len / packet_size;
328
329 reg_val = readl(mdata->base + SPI_CFG1_REG);
50f8fec2 330 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
a568231f
LL		 331 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
332 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
333 writel(reg_val, mdata->base + SPI_CFG1_REG);
334}
335
336static void mtk_spi_enable_transfer(struct spi_master *master)
337{
50f8fec2 338 u32 cmd;
a568231f
LL		 339 struct mtk_spi *mdata = spi_master_get_devdata(master);
340
341 cmd = readl(mdata->base + SPI_CMD_REG);
342 if (mdata->state == MTK_SPI_IDLE)
a71d6ea6 343 cmd |= SPI_CMD_ACT;
a568231f 344 else
a71d6ea6 345 cmd |= SPI_CMD_RESUME;
a568231f
LL		 346 writel(cmd, mdata->base + SPI_CMD_REG);
347}
348
50f8fec2 349static int mtk_spi_get_mult_delta(u32 xfer_len)
a568231f 350{
50f8fec2 351 u32 mult_delta;
a568231f
LL		 352
353 if (xfer_len > MTK_SPI_PACKET_SIZE)
354 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
355 else
356 mult_delta = 0;
357
358 return mult_delta;
359}
360
361static void mtk_spi_update_mdata_len(struct spi_master *master)
362{
363 int mult_delta;
364 struct mtk_spi *mdata = spi_master_get_devdata(master);
365
366 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
367 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
368 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
369 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
370 mdata->rx_sgl_len = mult_delta;
371 mdata->tx_sgl_len -= mdata->xfer_len;
372 } else {
373 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
374 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
375 mdata->tx_sgl_len = mult_delta;
376 mdata->rx_sgl_len -= mdata->xfer_len;
377 }
378 } else if (mdata->tx_sgl_len) {
379 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
380 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
381 mdata->tx_sgl_len = mult_delta;
382 } else if (mdata->rx_sgl_len) {
383 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
384 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
385 mdata->rx_sgl_len = mult_delta;
386 }
387}
388
389static void mtk_spi_setup_dma_addr(struct spi_master *master,
390 struct spi_transfer *xfer)
391{
392 struct mtk_spi *mdata = spi_master_get_devdata(master);
393
fdeae8f5 394 if (mdata->tx_sgl) {
395 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
396 mdata->base + SPI_TX_SRC_REG);
397#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
398 if (mdata->dev_comp->dma_ext)
399 writel((u32)(xfer->tx_dma >> 32),
400 mdata->base + SPI_TX_SRC_REG_64);
401#endif
402 }
403
404 if (mdata->rx_sgl) {
405 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
406 mdata->base + SPI_RX_DST_REG);
407#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
408 if (mdata->dev_comp->dma_ext)
409 writel((u32)(xfer->rx_dma >> 32),
410 mdata->base + SPI_RX_DST_REG_64);
411#endif
412 }
a568231f
LL		 413}
414
415static int mtk_spi_fifo_transfer(struct spi_master *master,
416 struct spi_device *spi,
417 struct spi_transfer *xfer)
418{
de327e49
NB		 419 int cnt, remainder;
420 u32 reg_val;
a568231f
LL		 421 struct mtk_spi *mdata = spi_master_get_devdata(master);
422
423 mdata->cur_transfer = xfer;
1ce24864 424 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
00bca73b 425 mdata->num_xfered = 0;
a568231f
LL		 426 mtk_spi_prepare_transfer(master, xfer);
427 mtk_spi_setup_packet(master);
428
de327e49 429 cnt = xfer->len / 4;
44f636da 430 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
a568231f 431
de327e49
NB		 432 remainder = xfer->len % 4;
433 if (remainder > 0) {
434 reg_val = 0;
435 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
436 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
437 }
438
a568231f
LL		 439 mtk_spi_enable_transfer(master);
440
441 return 1;
442}
443
444static int mtk_spi_dma_transfer(struct spi_master *master,
445 struct spi_device *spi,
446 struct spi_transfer *xfer)
447{
448 int cmd;
449 struct mtk_spi *mdata = spi_master_get_devdata(master);
450
451 mdata->tx_sgl = NULL;
452 mdata->rx_sgl = NULL;
453 mdata->tx_sgl_len = 0;
454 mdata->rx_sgl_len = 0;
455 mdata->cur_transfer = xfer;
00bca73b 456 mdata->num_xfered = 0;
a568231f
LL		 457
458 mtk_spi_prepare_transfer(master, xfer);
459
460 cmd = readl(mdata->base + SPI_CMD_REG);
461 if (xfer->tx_buf)
462 cmd |= SPI_CMD_TX_DMA;
463 if (xfer->rx_buf)
464 cmd |= SPI_CMD_RX_DMA;
465 writel(cmd, mdata->base + SPI_CMD_REG);
466
467 if (xfer->tx_buf)
468 mdata->tx_sgl = xfer->tx_sg.sgl;
469 if (xfer->rx_buf)
470 mdata->rx_sgl = xfer->rx_sg.sgl;
471
472 if (mdata->tx_sgl) {
473 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
474 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
475 }
476 if (mdata->rx_sgl) {
477 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
478 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
479 }
480
481 mtk_spi_update_mdata_len(master);
482 mtk_spi_setup_packet(master);
483 mtk_spi_setup_dma_addr(master, xfer);
484 mtk_spi_enable_transfer(master);
485
486 return 1;
487}
488
489static int mtk_spi_transfer_one(struct spi_master *master,
490 struct spi_device *spi,
491 struct spi_transfer *xfer)
492{
493 if (master->can_dma(master, spi, xfer))
494 return mtk_spi_dma_transfer(master, spi, xfer);
495 else
496 return mtk_spi_fifo_transfer(master, spi, xfer);
497}
498
499static bool mtk_spi_can_dma(struct spi_master *master,
500 struct spi_device *spi,
501 struct spi_transfer *xfer)
502{
1ce24864
DK		 503 /* Buffers for DMA transactions must be 4-byte aligned */
504 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
505 (unsigned long)xfer->tx_buf % 4 == 0 &&
506 (unsigned long)xfer->rx_buf % 4 == 0);
a568231f
LL		 507}
508
9f6e7e8d 509static int mtk_spi_set_hw_cs_timing(struct spi_device *spi,
510 struct spi_delay *setup,
511 struct spi_delay *hold,
512 struct spi_delay *inactive)
513{
514 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
515 u16 setup_dly, hold_dly, inactive_dly;
516 u32 reg_val;
517
518 if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
519 (hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
520 (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
521 dev_err(&spi->dev,
522 "Invalid delay unit, should be SPI_DELAY_UNIT_SCK\n");
523 return -EINVAL;
524 }
525
526 setup_dly = setup ? setup->value : 1;
527 hold_dly = hold ? hold->value : 1;
528 inactive_dly = inactive ? inactive->value : 1;
529
530 reg_val = readl(mdata->base + SPI_CFG0_REG);
531 if (mdata->dev_comp->enhance_timing) {
532 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
533 reg_val |= (((hold_dly - 1) & 0xffff)
534 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
535 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
536 reg_val |= (((setup_dly - 1) & 0xffff)
537 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
538 } else {
539 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
540 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
541 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
542 reg_val |= (((setup_dly - 1) & 0xff)
543 << SPI_CFG0_CS_SETUP_OFFSET);
544 }
545 writel(reg_val, mdata->base + SPI_CFG0_REG);
546
547 reg_val = readl(mdata->base + SPI_CFG1_REG);
548 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
549 reg_val |= (((inactive_dly - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
550 writel(reg_val, mdata->base + SPI_CFG1_REG);
551
552 return 0;
553}
554
58a984c7
LL		 555static int mtk_spi_setup(struct spi_device *spi)
556{
557 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
558
559 if (!spi->controller_data)
560 spi->controller_data = (void *)&mtk_default_chip_info;
561
98c8dccf 562 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
37457607
LL		 563 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
564
58a984c7
LL		 565 return 0;
566}
567
a568231f
LL		 568static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
569{
00bca73b 570 u32 cmd, reg_val, cnt, remainder, len;
a568231f
LL		 571 struct spi_master *master = dev_id;
572 struct mtk_spi *mdata = spi_master_get_devdata(master);
573 struct spi_transfer *trans = mdata->cur_transfer;
574
575 reg_val = readl(mdata->base + SPI_STATUS0_REG);
50f8fec2 576 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
a568231f
LL		 577 mdata->state = MTK_SPI_PAUSED;
578 else
579 mdata->state = MTK_SPI_IDLE;
580
581 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
a568231f 582 if (trans->rx_buf) {
de327e49 583 cnt = mdata->xfer_len / 4;
44f636da 584 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
00bca73b 585 trans->rx_buf + mdata->num_xfered, cnt);
de327e49
NB		 586 remainder = mdata->xfer_len % 4;
587 if (remainder > 0) {
588 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
00bca73b
PS		 589 memcpy(trans->rx_buf +
590 mdata->num_xfered +
591 (cnt * 4),
592 &reg_val,
593 remainder);
de327e49 594 }
a568231f 595 }
1ce24864 596
00bca73b
PS		 597 mdata->num_xfered += mdata->xfer_len;
598 if (mdata->num_xfered == trans->len) {
1ce24864
DK		 599 spi_finalize_current_transfer(master);
600 return IRQ_HANDLED;
601 }
602
00bca73b
PS		 603 len = trans->len - mdata->num_xfered;
604 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
1ce24864
DK		 605 mtk_spi_setup_packet(master);
606
a4d8f64f 607 cnt = mdata->xfer_len / 4;
00bca73b
PS		 608 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
609 trans->tx_buf + mdata->num_xfered, cnt);
1ce24864 610
a4d8f64f 611 remainder = mdata->xfer_len % 4;
1ce24864
DK		 612 if (remainder > 0) {
613 reg_val = 0;
00bca73b
PS		 614 memcpy(&reg_val,
615 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
616 remainder);
1ce24864
DK		 617 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
618 }
619
620 mtk_spi_enable_transfer(master);
621
a568231f
LL		 622 return IRQ_HANDLED;
623 }
624
625 if (mdata->tx_sgl)
626 trans->tx_dma += mdata->xfer_len;
627 if (mdata->rx_sgl)
628 trans->rx_dma += mdata->xfer_len;
629
630 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
631 mdata->tx_sgl = sg_next(mdata->tx_sgl);
632 if (mdata->tx_sgl) {
633 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
634 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
635 }
636 }
637 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
638 mdata->rx_sgl = sg_next(mdata->rx_sgl);
639 if (mdata->rx_sgl) {
640 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
641 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
642 }
643 }
644
645 if (!mdata->tx_sgl && !mdata->rx_sgl) {
646 /* spi disable dma */
647 cmd = readl(mdata->base + SPI_CMD_REG);
648 cmd &= ~SPI_CMD_TX_DMA;
649 cmd &= ~SPI_CMD_RX_DMA;
650 writel(cmd, mdata->base + SPI_CMD_REG);
651
652 spi_finalize_current_transfer(master);
653 return IRQ_HANDLED;
654 }
655
656 mtk_spi_update_mdata_len(master);
657 mtk_spi_setup_packet(master);
658 mtk_spi_setup_dma_addr(master, trans);
659 mtk_spi_enable_transfer(master);
660
661 return IRQ_HANDLED;
662}
663
664static int mtk_spi_probe(struct platform_device *pdev)
665{
666 struct spi_master *master;
667 struct mtk_spi *mdata;
668 const struct of_device_id *of_id;
fdeae8f5 669 int i, irq, ret, addr_bits;
a568231f
LL		 670
671 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
672 if (!master) {
673 dev_err(&pdev->dev, "failed to alloc spi master\n");
674 return -ENOMEM;
675 }
676
677 master->auto_runtime_pm = true;
678 master->dev.of_node = pdev->dev.of_node;
3e582c6e 679 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
a568231f
LL		 680
681 master->set_cs = mtk_spi_set_cs;
a568231f
LL		 682 master->prepare_message = mtk_spi_prepare_message;
683 master->transfer_one = mtk_spi_transfer_one;
684 master->can_dma = mtk_spi_can_dma;
58a984c7 685 master->setup = mtk_spi_setup;
9f6e7e8d 686 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
a568231f
LL		 687
688 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
689 if (!of_id) {
690 dev_err(&pdev->dev, "failed to probe of_node\n");
691 ret = -EINVAL;
692 goto err_put_master;
693 }
694
695 mdata = spi_master_get_devdata(master);
696 mdata->dev_comp = of_id->data;
ae7c2d34
LX		 697
698 if (mdata->dev_comp->enhance_timing)
699 master->mode_bits |= SPI_CS_HIGH;
700
a568231f
LL		 701 if (mdata->dev_comp->must_tx)
702 master->flags = SPI_MASTER_MUST_TX;
703
704 if (mdata->dev_comp->need_pad_sel) {
37457607
LL		 705 mdata->pad_num = of_property_count_u32_elems(
706 pdev->dev.of_node,
707 "mediatek,pad-select");
708 if (mdata->pad_num < 0) {
709 dev_err(&pdev->dev,
710 "No 'mediatek,pad-select' property\n");
711 ret = -EINVAL;
a568231f
LL		 712 goto err_put_master;
713 }
714
37457607
LL		 715 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
716 sizeof(u32), GFP_KERNEL);
717 if (!mdata->pad_sel) {
718 ret = -ENOMEM;
a568231f
LL		 719 goto err_put_master;
720 }
37457607
LL		 721
722 for (i = 0; i < mdata->pad_num; i++) {
723 of_property_read_u32_index(pdev->dev.of_node,
724 "mediatek,pad-select",
725 i, &mdata->pad_sel[i]);
726 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
727 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
728 i, mdata->pad_sel[i]);
729 ret = -EINVAL;
730 goto err_put_master;
731 }
732 }
a568231f
LL		 733 }
734
735 platform_set_drvdata(pdev, master);
5dd381e7 736 mdata->base = devm_platform_ioremap_resource(pdev, 0);
a568231f
LL		 737 if (IS_ERR(mdata->base)) {
738 ret = PTR_ERR(mdata->base);
739 goto err_put_master;
740 }
741
742 irq = platform_get_irq(pdev, 0);
743 if (irq < 0) {
a568231f
LL		 744 ret = irq;
745 goto err_put_master;
746 }
747
748 if (!pdev->dev.dma_mask)
749 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
750
751 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
752 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
753 if (ret) {
754 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
755 goto err_put_master;
756 }
757
a568231f
LL		 758 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
759 if (IS_ERR(mdata->parent_clk)) {
760 ret = PTR_ERR(mdata->parent_clk);
761 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
762 goto err_put_master;
763 }
764
adcbcfea
LL		 765 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
766 if (IS_ERR(mdata->sel_clk)) {
e26d15f7 767 ret = PTR_ERR(mdata->sel_clk);
adcbcfea 768 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
a568231f
LL		 769 goto err_put_master;
770 }
771
adcbcfea
LL		 772 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
773 if (IS_ERR(mdata->spi_clk)) {
e26d15f7 774 ret = PTR_ERR(mdata->spi_clk);
adcbcfea 775 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
a568231f
LL		 776 goto err_put_master;
777 }
778
779 ret = clk_prepare_enable(mdata->spi_clk);
780 if (ret < 0) {
781 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
782 goto err_put_master;
783 }
784
adcbcfea 785 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
a568231f
LL		 786 if (ret < 0) {
787 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
e38da37f
LL		 788 clk_disable_unprepare(mdata->spi_clk);
789 goto err_put_master;
a568231f
LL		 790 }
791
792 clk_disable_unprepare(mdata->spi_clk);
793
794 pm_runtime_enable(&pdev->dev);
795
796 ret = devm_spi_register_master(&pdev->dev, master);
797 if (ret) {
798 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
e38da37f 799 goto err_disable_runtime_pm;
a568231f
LL		 800 }
801
37457607
LL		 802 if (mdata->dev_comp->need_pad_sel) {
803 if (mdata->pad_num != master->num_chipselect) {
804 dev_err(&pdev->dev,
805 "pad_num does not match num_chipselect(%d != %d)\n",
806 mdata->pad_num, master->num_chipselect);
807 ret = -EINVAL;
e38da37f 808 goto err_disable_runtime_pm;
37457607
LL		 809 }
810
98c8dccf
NB		 811 if (!master->cs_gpios && master->num_chipselect > 1) {
812 dev_err(&pdev->dev,
813 "cs_gpios not specified and num_chipselect > 1\n");
814 ret = -EINVAL;
e38da37f 815 goto err_disable_runtime_pm;
98c8dccf
NB		 816 }
817
818 if (master->cs_gpios) {
819 for (i = 0; i < master->num_chipselect; i++) {
820 ret = devm_gpio_request(&pdev->dev,
821 master->cs_gpios[i],
822 dev_name(&pdev->dev));
823 if (ret) {
824 dev_err(&pdev->dev,
825 "can't get CS GPIO %i\n", i);
e38da37f 826 goto err_disable_runtime_pm;
98c8dccf 827 }
37457607
LL		 828 }
829 }
830 }
831
fdeae8f5 832 if (mdata->dev_comp->dma_ext)
833 addr_bits = DMA_ADDR_EXT_BITS;
834 else
835 addr_bits = DMA_ADDR_DEF_BITS;
836 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
837 if (ret)
838 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
839 addr_bits, ret);
840
a568231f
LL		 841 return 0;
842
e38da37f
LL		 843err_disable_runtime_pm:
844 pm_runtime_disable(&pdev->dev);
a568231f
LL		 845err_put_master:
846 spi_master_put(master);
847
848 return ret;
849}
850
851static int mtk_spi_remove(struct platform_device *pdev)
852{
853 struct spi_master *master = platform_get_drvdata(pdev);
854 struct mtk_spi *mdata = spi_master_get_devdata(master);
855
856 pm_runtime_disable(&pdev->dev);
857
858 mtk_spi_reset(mdata);
a568231f
LL		 859
860 return 0;
861}
862
863#ifdef CONFIG_PM_SLEEP
864static int mtk_spi_suspend(struct device *dev)
865{
866 int ret;
867 struct spi_master *master = dev_get_drvdata(dev);
868 struct mtk_spi *mdata = spi_master_get_devdata(master);
869
870 ret = spi_master_suspend(master);
871 if (ret)
872 return ret;
873
874 if (!pm_runtime_suspended(dev))
875 clk_disable_unprepare(mdata->spi_clk);
876
877 return ret;
878}
879
880static int mtk_spi_resume(struct device *dev)
881{
882 int ret;
883 struct spi_master *master = dev_get_drvdata(dev);
884 struct mtk_spi *mdata = spi_master_get_devdata(master);
885
886 if (!pm_runtime_suspended(dev)) {
887 ret = clk_prepare_enable(mdata->spi_clk);
13da5a0b
LL		 888 if (ret < 0) {
889 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
a568231f 890 return ret;
13da5a0b 891 }
a568231f
LL		 892 }
893
894 ret = spi_master_resume(master);
895 if (ret < 0)
896 clk_disable_unprepare(mdata->spi_clk);
897
898 return ret;
899}
900#endif /* CONFIG_PM_SLEEP */
901
902#ifdef CONFIG_PM
903static int mtk_spi_runtime_suspend(struct device *dev)
904{
905 struct spi_master *master = dev_get_drvdata(dev);
906 struct mtk_spi *mdata = spi_master_get_devdata(master);
907
908 clk_disable_unprepare(mdata->spi_clk);
909
910 return 0;
911}
912
913static int mtk_spi_runtime_resume(struct device *dev)
914{
915 struct spi_master *master = dev_get_drvdata(dev);
916 struct mtk_spi *mdata = spi_master_get_devdata(master);
13da5a0b
LL		 917 int ret;
918
919 ret = clk_prepare_enable(mdata->spi_clk);
920 if (ret < 0) {
921 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
922 return ret;
923 }
a568231f 924
13da5a0b 925 return 0;
a568231f
LL		 926}
927#endif /* CONFIG_PM */
928
929static const struct dev_pm_ops mtk_spi_pm = {
930 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
931 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
932 mtk_spi_runtime_resume, NULL)
933};
934
4299aaaa 935static struct platform_driver mtk_spi_driver = {
a568231f
LL		 936 .driver = {
937 .name = "mtk-spi",
938 .pm = &mtk_spi_pm,
939 .of_match_table = mtk_spi_of_match,
940 },
941 .probe = mtk_spi_probe,
942 .remove = mtk_spi_remove,
943};
944
945module_platform_driver(mtk_spi_driver);
946
947MODULE_DESCRIPTION("MTK SPI Controller driver");
948MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
949MODULE_LICENSE("GPL v2");
e4001885 950MODULE_ALIAS("platform:mtk-spi");
Linux 6.x block layer and io_uring tree(s)