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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a568231f LL |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
4 | * Author: Leilk Liu <leilk.liu@mediatek.com> | |
a568231f LL |
5 | */ |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/device.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/interrupt.h> | |
dd69a0a6 | 11 | #include <linux/io.h> |
a568231f LL |
12 | #include <linux/ioport.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
1a5a87d5 | 15 | #include <linux/gpio/consumer.h> |
a568231f LL |
16 | #include <linux/platform_device.h> |
17 | #include <linux/platform_data/spi-mt65xx.h> | |
18 | #include <linux/pm_runtime.h> | |
19 | #include <linux/spi/spi.h> | |
fdeae8f5 | 20 | #include <linux/dma-mapping.h> |
a568231f LL |
21 | |
22 | #define SPI_CFG0_REG 0x0000 | |
23 | #define SPI_CFG1_REG 0x0004 | |
24 | #define SPI_TX_SRC_REG 0x0008 | |
25 | #define SPI_RX_DST_REG 0x000c | |
26 | #define SPI_TX_DATA_REG 0x0010 | |
27 | #define SPI_RX_DATA_REG 0x0014 | |
28 | #define SPI_CMD_REG 0x0018 | |
29 | #define SPI_STATUS0_REG 0x001c | |
30 | #define SPI_PAD_SEL_REG 0x0024 | |
058fe49d | 31 | #define SPI_CFG2_REG 0x0028 |
fdeae8f5 | 32 | #define SPI_TX_SRC_REG_64 0x002c |
33 | #define SPI_RX_DST_REG_64 0x0030 | |
7e963fb2 | 34 | #define SPI_CFG3_IPM_REG 0x0040 |
a568231f LL |
35 | |
36 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 | |
37 | #define SPI_CFG0_SCK_LOW_OFFSET 8 | |
38 | #define SPI_CFG0_CS_HOLD_OFFSET 16 | |
39 | #define SPI_CFG0_CS_SETUP_OFFSET 24 | |
058fe49d LL |
40 | #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 |
41 | #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 | |
a568231f LL |
42 | |
43 | #define SPI_CFG1_CS_IDLE_OFFSET 0 | |
44 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 | |
45 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 | |
f84d866a | 46 | #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 |
03b1be37 | 47 | #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 |
a568231f | 48 | |
f84d866a | 49 | #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 |
03b1be37 LL |
50 | #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 |
51 | ||
a568231f LL |
52 | #define SPI_CFG1_CS_IDLE_MASK 0xff |
53 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 | |
54 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 | |
7e963fb2 | 55 | #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) |
44b37eb7 | 56 | #define SPI_CFG2_SCK_HIGH_OFFSET 0 |
57 | #define SPI_CFG2_SCK_LOW_OFFSET 16 | |
a568231f | 58 | |
a71d6ea6 LL |
59 | #define SPI_CMD_ACT BIT(0) |
60 | #define SPI_CMD_RESUME BIT(1) | |
a568231f LL |
61 | #define SPI_CMD_RST BIT(2) |
62 | #define SPI_CMD_PAUSE_EN BIT(4) | |
63 | #define SPI_CMD_DEASSERT BIT(5) | |
058fe49d LL |
64 | #define SPI_CMD_SAMPLE_SEL BIT(6) |
65 | #define SPI_CMD_CS_POL BIT(7) | |
a568231f LL |
66 | #define SPI_CMD_CPHA BIT(8) |
67 | #define SPI_CMD_CPOL BIT(9) | |
68 | #define SPI_CMD_RX_DMA BIT(10) | |
69 | #define SPI_CMD_TX_DMA BIT(11) | |
70 | #define SPI_CMD_TXMSBF BIT(12) | |
71 | #define SPI_CMD_RXMSBF BIT(13) | |
72 | #define SPI_CMD_RX_ENDIAN BIT(14) | |
73 | #define SPI_CMD_TX_ENDIAN BIT(15) | |
74 | #define SPI_CMD_FINISH_IE BIT(16) | |
75 | #define SPI_CMD_PAUSE_IE BIT(17) | |
7e963fb2 LL |
76 | #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) |
77 | #define SPI_CMD_IPM_SPIM_LOOP BIT(21) | |
78 | #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 | |
a568231f | 79 | |
7e963fb2 LL |
80 | #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) |
81 | #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) | |
82 | #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) | |
a568231f LL |
83 | #define MT8173_SPI_MAX_PAD_SEL 3 |
84 | ||
50f8fec2 LL |
85 | #define MTK_SPI_PAUSE_INT_STATUS 0x2 |
86 | ||
a568231f LL |
87 | #define MTK_SPI_IDLE 0 |
88 | #define MTK_SPI_PAUSED 1 | |
89 | ||
1ce24864 | 90 | #define MTK_SPI_MAX_FIFO_SIZE 32U |
a568231f | 91 | #define MTK_SPI_PACKET_SIZE 1024 |
7e963fb2 | 92 | #define MTK_SPI_IPM_PACKET_SIZE SZ_64K |
fdeae8f5 | 93 | #define MTK_SPI_32BITS_MASK (0xffffffff) |
94 | ||
95 | #define DMA_ADDR_EXT_BITS (36) | |
96 | #define DMA_ADDR_DEF_BITS (32) | |
a568231f LL |
97 | |
98 | struct mtk_spi_compatible { | |
af57937e LL |
99 | bool need_pad_sel; |
100 | /* Must explicitly send dummy Tx bytes to do Rx only transfer */ | |
101 | bool must_tx; | |
058fe49d LL |
102 | /* some IC design adjust cfg register to enhance time accuracy */ |
103 | bool enhance_timing; | |
fdeae8f5 | 104 | /* some IC support DMA addr extension */ |
105 | bool dma_ext; | |
162a31ef MZ |
106 | /* some IC no need unprepare SPI clk */ |
107 | bool no_need_unprepare; | |
7e963fb2 LL |
108 | /* IPM design adjust and extend register to support more features */ |
109 | bool ipm_design; | |
110 | ||
a568231f LL |
111 | }; |
112 | ||
113 | struct mtk_spi { | |
114 | void __iomem *base; | |
115 | u32 state; | |
37457607 LL |
116 | int pad_num; |
117 | u32 *pad_sel; | |
adcbcfea | 118 | struct clk *parent_clk, *sel_clk, *spi_clk; |
a568231f LL |
119 | struct spi_transfer *cur_transfer; |
120 | u32 xfer_len; | |
00bca73b | 121 | u32 num_xfered; |
a568231f LL |
122 | struct scatterlist *tx_sgl, *rx_sgl; |
123 | u32 tx_sgl_len, rx_sgl_len; | |
124 | const struct mtk_spi_compatible *dev_comp; | |
162a31ef | 125 | u32 spi_clk_hz; |
a568231f LL |
126 | }; |
127 | ||
4eaf6f73 | 128 | static const struct mtk_spi_compatible mtk_common_compat; |
fc4f226f | 129 | |
b6b1f2d9 | 130 | static const struct mtk_spi_compatible mt2712_compat = { |
131 | .must_tx = true, | |
132 | }; | |
133 | ||
7e963fb2 LL |
134 | static const struct mtk_spi_compatible mtk_ipm_compat = { |
135 | .enhance_timing = true, | |
136 | .dma_ext = true, | |
137 | .ipm_design = true, | |
138 | }; | |
139 | ||
2c231e0a | 140 | static const struct mtk_spi_compatible mt6765_compat = { |
141 | .need_pad_sel = true, | |
142 | .must_tx = true, | |
143 | .enhance_timing = true, | |
fdeae8f5 | 144 | .dma_ext = true, |
2c231e0a | 145 | }; |
146 | ||
fc4f226f LL |
147 | static const struct mtk_spi_compatible mt7622_compat = { |
148 | .must_tx = true, | |
149 | .enhance_timing = true, | |
150 | }; | |
151 | ||
a568231f | 152 | static const struct mtk_spi_compatible mt8173_compat = { |
af57937e LL |
153 | .need_pad_sel = true, |
154 | .must_tx = true, | |
a568231f LL |
155 | }; |
156 | ||
b654aa6f LL |
157 | static const struct mtk_spi_compatible mt8183_compat = { |
158 | .need_pad_sel = true, | |
159 | .must_tx = true, | |
160 | .enhance_timing = true, | |
161 | }; | |
162 | ||
162a31ef MZ |
163 | static const struct mtk_spi_compatible mt6893_compat = { |
164 | .need_pad_sel = true, | |
165 | .must_tx = true, | |
166 | .enhance_timing = true, | |
167 | .dma_ext = true, | |
168 | .no_need_unprepare = true, | |
169 | }; | |
170 | ||
a568231f LL |
171 | /* |
172 | * A piece of default chip info unless the platform | |
173 | * supplies it. | |
174 | */ | |
175 | static const struct mtk_chip_config mtk_default_chip_info = { | |
058fe49d | 176 | .sample_sel = 0, |
f84d866a | 177 | .tick_delay = 0, |
a568231f LL |
178 | }; |
179 | ||
180 | static const struct of_device_id mtk_spi_of_match[] = { | |
7e963fb2 LL |
181 | { .compatible = "mediatek,spi-ipm", |
182 | .data = (void *)&mtk_ipm_compat, | |
183 | }, | |
15bcdefd LL |
184 | { .compatible = "mediatek,mt2701-spi", |
185 | .data = (void *)&mtk_common_compat, | |
186 | }, | |
b6b1f2d9 | 187 | { .compatible = "mediatek,mt2712-spi", |
188 | .data = (void *)&mt2712_compat, | |
189 | }, | |
4eaf6f73 LL |
190 | { .compatible = "mediatek,mt6589-spi", |
191 | .data = (void *)&mtk_common_compat, | |
192 | }, | |
2c231e0a | 193 | { .compatible = "mediatek,mt6765-spi", |
194 | .data = (void *)&mt6765_compat, | |
195 | }, | |
fc4f226f LL |
196 | { .compatible = "mediatek,mt7622-spi", |
197 | .data = (void *)&mt7622_compat, | |
198 | }, | |
942779c6 LL |
199 | { .compatible = "mediatek,mt7629-spi", |
200 | .data = (void *)&mt7622_compat, | |
201 | }, | |
4eaf6f73 LL |
202 | { .compatible = "mediatek,mt8135-spi", |
203 | .data = (void *)&mtk_common_compat, | |
204 | }, | |
205 | { .compatible = "mediatek,mt8173-spi", | |
206 | .data = (void *)&mt8173_compat, | |
207 | }, | |
b654aa6f LL |
208 | { .compatible = "mediatek,mt8183-spi", |
209 | .data = (void *)&mt8183_compat, | |
210 | }, | |
8cf125c4 | 211 | { .compatible = "mediatek,mt8192-spi", |
212 | .data = (void *)&mt6765_compat, | |
213 | }, | |
162a31ef MZ |
214 | { .compatible = "mediatek,mt6893-spi", |
215 | .data = (void *)&mt6893_compat, | |
216 | }, | |
a568231f LL |
217 | {} |
218 | }; | |
219 | MODULE_DEVICE_TABLE(of, mtk_spi_of_match); | |
220 | ||
221 | static void mtk_spi_reset(struct mtk_spi *mdata) | |
222 | { | |
223 | u32 reg_val; | |
224 | ||
225 | /* set the software reset bit in SPI_CMD_REG. */ | |
226 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
227 | reg_val |= SPI_CMD_RST; | |
228 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
229 | ||
230 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
231 | reg_val &= ~SPI_CMD_RST; | |
232 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
233 | } | |
234 | ||
04e6bb0d MZ |
235 | static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) |
236 | { | |
237 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
238 | struct spi_delay *cs_setup = &spi->cs_setup; | |
239 | struct spi_delay *cs_hold = &spi->cs_hold; | |
240 | struct spi_delay *cs_inactive = &spi->cs_inactive; | |
5c842e51 | 241 | u32 setup, hold, inactive; |
04e6bb0d MZ |
242 | u32 reg_val; |
243 | int delay; | |
244 | ||
245 | delay = spi_delay_to_ns(cs_setup, NULL); | |
246 | if (delay < 0) | |
247 | return delay; | |
248 | setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
249 | ||
250 | delay = spi_delay_to_ns(cs_hold, NULL); | |
251 | if (delay < 0) | |
252 | return delay; | |
253 | hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
254 | ||
255 | delay = spi_delay_to_ns(cs_inactive, NULL); | |
256 | if (delay < 0) | |
257 | return delay; | |
258 | inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; | |
259 | ||
3672bb82 DH |
260 | if (hold || setup) { |
261 | reg_val = readl(mdata->base + SPI_CFG0_REG); | |
262 | if (mdata->dev_comp->enhance_timing) { | |
263 | if (hold) { | |
264 | hold = min_t(u32, hold, 0x10000); | |
265 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); | |
266 | reg_val |= (((hold - 1) & 0xffff) | |
267 | << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); | |
268 | } | |
269 | if (setup) { | |
270 | setup = min_t(u32, setup, 0x10000); | |
271 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); | |
272 | reg_val |= (((setup - 1) & 0xffff) | |
273 | << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); | |
274 | } | |
275 | } else { | |
276 | if (hold) { | |
277 | hold = min_t(u32, hold, 0x100); | |
278 | reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); | |
279 | reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); | |
280 | } | |
281 | if (setup) { | |
282 | setup = min_t(u32, setup, 0x100); | |
283 | reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); | |
284 | reg_val |= (((setup - 1) & 0xff) | |
285 | << SPI_CFG0_CS_SETUP_OFFSET); | |
286 | } | |
287 | } | |
288 | writel(reg_val, mdata->base + SPI_CFG0_REG); | |
04e6bb0d | 289 | } |
04e6bb0d | 290 | |
3672bb82 DH |
291 | if (inactive) { |
292 | inactive = min_t(u32, inactive, 0x100); | |
293 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
294 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; | |
295 | reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); | |
296 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
297 | } | |
04e6bb0d MZ |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
7e963fb2 LL |
302 | static int mtk_spi_hw_init(struct spi_master *master, |
303 | struct spi_device *spi) | |
a568231f | 304 | { |
79b5d3f2 | 305 | u16 cpha, cpol; |
a568231f | 306 | u32 reg_val; |
58a984c7 | 307 | struct mtk_chip_config *chip_config = spi->controller_data; |
79b5d3f2 LL |
308 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
309 | ||
310 | cpha = spi->mode & SPI_CPHA ? 1 : 0; | |
311 | cpol = spi->mode & SPI_CPOL ? 1 : 0; | |
312 | ||
79b5d3f2 | 313 | reg_val = readl(mdata->base + SPI_CMD_REG); |
7e963fb2 LL |
314 | if (mdata->dev_comp->ipm_design) { |
315 | /* SPI transfer without idle time until packet length done */ | |
316 | reg_val |= SPI_CMD_IPM_NONIDLE_MODE; | |
317 | if (spi->mode & SPI_LOOP) | |
318 | reg_val |= SPI_CMD_IPM_SPIM_LOOP; | |
319 | else | |
320 | reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; | |
321 | } | |
322 | ||
79b5d3f2 LL |
323 | if (cpha) |
324 | reg_val |= SPI_CMD_CPHA; | |
325 | else | |
326 | reg_val &= ~SPI_CMD_CPHA; | |
327 | if (cpol) | |
328 | reg_val |= SPI_CMD_CPOL; | |
329 | else | |
330 | reg_val &= ~SPI_CMD_CPOL; | |
a568231f LL |
331 | |
332 | /* set the mlsbx and mlsbtx */ | |
3e582c6e | 333 | if (spi->mode & SPI_LSB_FIRST) { |
a71d6ea6 | 334 | reg_val &= ~SPI_CMD_TXMSBF; |
a71d6ea6 | 335 | reg_val &= ~SPI_CMD_RXMSBF; |
3e582c6e LL |
336 | } else { |
337 | reg_val |= SPI_CMD_TXMSBF; | |
338 | reg_val |= SPI_CMD_RXMSBF; | |
339 | } | |
a568231f LL |
340 | |
341 | /* set the tx/rx endian */ | |
44f636da LL |
342 | #ifdef __LITTLE_ENDIAN |
343 | reg_val &= ~SPI_CMD_TX_ENDIAN; | |
344 | reg_val &= ~SPI_CMD_RX_ENDIAN; | |
345 | #else | |
346 | reg_val |= SPI_CMD_TX_ENDIAN; | |
347 | reg_val |= SPI_CMD_RX_ENDIAN; | |
348 | #endif | |
a568231f | 349 | |
058fe49d | 350 | if (mdata->dev_comp->enhance_timing) { |
ae7c2d34 LX |
351 | /* set CS polarity */ |
352 | if (spi->mode & SPI_CS_HIGH) | |
058fe49d LL |
353 | reg_val |= SPI_CMD_CS_POL; |
354 | else | |
355 | reg_val &= ~SPI_CMD_CS_POL; | |
ae7c2d34 | 356 | |
058fe49d LL |
357 | if (chip_config->sample_sel) |
358 | reg_val |= SPI_CMD_SAMPLE_SEL; | |
359 | else | |
360 | reg_val &= ~SPI_CMD_SAMPLE_SEL; | |
361 | } | |
362 | ||
a568231f | 363 | /* set finish and pause interrupt always enable */ |
15293324 | 364 | reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; |
a568231f LL |
365 | |
366 | /* disable dma mode */ | |
367 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); | |
368 | ||
369 | /* disable deassert mode */ | |
370 | reg_val &= ~SPI_CMD_DEASSERT; | |
371 | ||
372 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
373 | ||
374 | /* pad select */ | |
375 | if (mdata->dev_comp->need_pad_sel) | |
37457607 LL |
376 | writel(mdata->pad_sel[spi->chip_select], |
377 | mdata->base + SPI_PAD_SEL_REG); | |
a568231f | 378 | |
f84d866a | 379 | /* tick delay */ |
03b1be37 | 380 | if (mdata->dev_comp->enhance_timing) { |
7e963fb2 LL |
381 | if (mdata->dev_comp->ipm_design) { |
382 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
383 | reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; | |
384 | reg_val |= ((chip_config->tick_delay & 0x7) | |
385 | << SPI_CMD_IPM_GET_TICKDLY_OFFSET); | |
386 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
387 | } else { | |
388 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
389 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; | |
390 | reg_val |= ((chip_config->tick_delay & 0x7) | |
391 | << SPI_CFG1_GET_TICK_DLY_OFFSET); | |
392 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
393 | } | |
03b1be37 | 394 | } else { |
7e963fb2 | 395 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
03b1be37 LL |
396 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; |
397 | reg_val |= ((chip_config->tick_delay & 0x3) | |
398 | << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); | |
7e963fb2 | 399 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
03b1be37 | 400 | } |
f84d866a | 401 | |
04e6bb0d MZ |
402 | /* set hw cs timing */ |
403 | mtk_spi_set_hw_cs_timing(spi); | |
a568231f LL |
404 | return 0; |
405 | } | |
406 | ||
7e963fb2 LL |
407 | static int mtk_spi_prepare_message(struct spi_master *master, |
408 | struct spi_message *msg) | |
409 | { | |
410 | return mtk_spi_hw_init(master, msg->spi); | |
411 | } | |
412 | ||
a568231f LL |
413 | static void mtk_spi_set_cs(struct spi_device *spi, bool enable) |
414 | { | |
415 | u32 reg_val; | |
416 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
417 | ||
ae7c2d34 LX |
418 | if (spi->mode & SPI_CS_HIGH) |
419 | enable = !enable; | |
420 | ||
a568231f | 421 | reg_val = readl(mdata->base + SPI_CMD_REG); |
6583d203 | 422 | if (!enable) { |
a568231f | 423 | reg_val |= SPI_CMD_PAUSE_EN; |
6583d203 LL |
424 | writel(reg_val, mdata->base + SPI_CMD_REG); |
425 | } else { | |
a568231f | 426 | reg_val &= ~SPI_CMD_PAUSE_EN; |
6583d203 LL |
427 | writel(reg_val, mdata->base + SPI_CMD_REG); |
428 | mdata->state = MTK_SPI_IDLE; | |
429 | mtk_spi_reset(mdata); | |
430 | } | |
a568231f LL |
431 | } |
432 | ||
433 | static void mtk_spi_prepare_transfer(struct spi_master *master, | |
7e963fb2 | 434 | u32 speed_hz) |
a568231f | 435 | { |
162a31ef | 436 | u32 div, sck_time, reg_val; |
a568231f LL |
437 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
438 | ||
7e963fb2 LL |
439 | if (speed_hz < mdata->spi_clk_hz / 2) |
440 | div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); | |
a568231f LL |
441 | else |
442 | div = 1; | |
443 | ||
2ce0acf5 | 444 | sck_time = (div + 1) / 2; |
a568231f | 445 | |
058fe49d | 446 | if (mdata->dev_comp->enhance_timing) { |
9f6e7e8d | 447 | reg_val = readl(mdata->base + SPI_CFG2_REG); |
448 | reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); | |
449 | reg_val |= (((sck_time - 1) & 0xffff) | |
44b37eb7 | 450 | << SPI_CFG2_SCK_HIGH_OFFSET); |
9f6e7e8d | 451 | reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); |
058fe49d | 452 | reg_val |= (((sck_time - 1) & 0xffff) |
44b37eb7 | 453 | << SPI_CFG2_SCK_LOW_OFFSET); |
058fe49d | 454 | writel(reg_val, mdata->base + SPI_CFG2_REG); |
058fe49d | 455 | } else { |
9f6e7e8d | 456 | reg_val = readl(mdata->base + SPI_CFG0_REG); |
457 | reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); | |
458 | reg_val |= (((sck_time - 1) & 0xff) | |
058fe49d | 459 | << SPI_CFG0_SCK_HIGH_OFFSET); |
9f6e7e8d | 460 | reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); |
058fe49d | 461 | reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); |
058fe49d LL |
462 | writel(reg_val, mdata->base + SPI_CFG0_REG); |
463 | } | |
a568231f LL |
464 | } |
465 | ||
466 | static void mtk_spi_setup_packet(struct spi_master *master) | |
467 | { | |
468 | u32 packet_size, packet_loop, reg_val; | |
469 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
470 | ||
7e963fb2 LL |
471 | if (mdata->dev_comp->ipm_design) |
472 | packet_size = min_t(u32, | |
473 | mdata->xfer_len, | |
474 | MTK_SPI_IPM_PACKET_SIZE); | |
475 | else | |
476 | packet_size = min_t(u32, | |
477 | mdata->xfer_len, | |
478 | MTK_SPI_PACKET_SIZE); | |
479 | ||
a568231f LL |
480 | packet_loop = mdata->xfer_len / packet_size; |
481 | ||
482 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
7e963fb2 LL |
483 | if (mdata->dev_comp->ipm_design) |
484 | reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; | |
485 | else | |
486 | reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; | |
a568231f | 487 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; |
7e963fb2 | 488 | reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; |
a568231f LL |
489 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; |
490 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
491 | } | |
492 | ||
493 | static void mtk_spi_enable_transfer(struct spi_master *master) | |
494 | { | |
50f8fec2 | 495 | u32 cmd; |
a568231f LL |
496 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
497 | ||
498 | cmd = readl(mdata->base + SPI_CMD_REG); | |
499 | if (mdata->state == MTK_SPI_IDLE) | |
a71d6ea6 | 500 | cmd |= SPI_CMD_ACT; |
a568231f | 501 | else |
a71d6ea6 | 502 | cmd |= SPI_CMD_RESUME; |
a568231f LL |
503 | writel(cmd, mdata->base + SPI_CMD_REG); |
504 | } | |
505 | ||
50f8fec2 | 506 | static int mtk_spi_get_mult_delta(u32 xfer_len) |
a568231f | 507 | { |
50f8fec2 | 508 | u32 mult_delta; |
a568231f LL |
509 | |
510 | if (xfer_len > MTK_SPI_PACKET_SIZE) | |
511 | mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; | |
512 | else | |
513 | mult_delta = 0; | |
514 | ||
515 | return mult_delta; | |
516 | } | |
517 | ||
518 | static void mtk_spi_update_mdata_len(struct spi_master *master) | |
519 | { | |
520 | int mult_delta; | |
521 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
522 | ||
523 | if (mdata->tx_sgl_len && mdata->rx_sgl_len) { | |
524 | if (mdata->tx_sgl_len > mdata->rx_sgl_len) { | |
525 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
526 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
527 | mdata->rx_sgl_len = mult_delta; | |
528 | mdata->tx_sgl_len -= mdata->xfer_len; | |
529 | } else { | |
530 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
531 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
532 | mdata->tx_sgl_len = mult_delta; | |
533 | mdata->rx_sgl_len -= mdata->xfer_len; | |
534 | } | |
535 | } else if (mdata->tx_sgl_len) { | |
536 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
537 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
538 | mdata->tx_sgl_len = mult_delta; | |
539 | } else if (mdata->rx_sgl_len) { | |
540 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
541 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
542 | mdata->rx_sgl_len = mult_delta; | |
543 | } | |
544 | } | |
545 | ||
546 | static void mtk_spi_setup_dma_addr(struct spi_master *master, | |
547 | struct spi_transfer *xfer) | |
548 | { | |
549 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
550 | ||
fdeae8f5 | 551 | if (mdata->tx_sgl) { |
552 | writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), | |
553 | mdata->base + SPI_TX_SRC_REG); | |
554 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
555 | if (mdata->dev_comp->dma_ext) | |
556 | writel((u32)(xfer->tx_dma >> 32), | |
557 | mdata->base + SPI_TX_SRC_REG_64); | |
558 | #endif | |
559 | } | |
560 | ||
561 | if (mdata->rx_sgl) { | |
562 | writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), | |
563 | mdata->base + SPI_RX_DST_REG); | |
564 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
565 | if (mdata->dev_comp->dma_ext) | |
566 | writel((u32)(xfer->rx_dma >> 32), | |
567 | mdata->base + SPI_RX_DST_REG_64); | |
568 | #endif | |
569 | } | |
a568231f LL |
570 | } |
571 | ||
572 | static int mtk_spi_fifo_transfer(struct spi_master *master, | |
573 | struct spi_device *spi, | |
574 | struct spi_transfer *xfer) | |
575 | { | |
de327e49 NB |
576 | int cnt, remainder; |
577 | u32 reg_val; | |
a568231f LL |
578 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
579 | ||
580 | mdata->cur_transfer = xfer; | |
1ce24864 | 581 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); |
00bca73b | 582 | mdata->num_xfered = 0; |
7e963fb2 | 583 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
a568231f LL |
584 | mtk_spi_setup_packet(master); |
585 | ||
0d5c3954 GR |
586 | if (xfer->tx_buf) { |
587 | cnt = xfer->len / 4; | |
3a70dd2d | 588 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); |
0d5c3954 GR |
589 | remainder = xfer->len % 4; |
590 | if (remainder > 0) { | |
591 | reg_val = 0; | |
3a70dd2d PH |
592 | memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); |
593 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); | |
594 | } | |
de327e49 NB |
595 | } |
596 | ||
a568231f LL |
597 | mtk_spi_enable_transfer(master); |
598 | ||
599 | return 1; | |
600 | } | |
601 | ||
602 | static int mtk_spi_dma_transfer(struct spi_master *master, | |
603 | struct spi_device *spi, | |
604 | struct spi_transfer *xfer) | |
605 | { | |
606 | int cmd; | |
607 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
608 | ||
609 | mdata->tx_sgl = NULL; | |
610 | mdata->rx_sgl = NULL; | |
611 | mdata->tx_sgl_len = 0; | |
612 | mdata->rx_sgl_len = 0; | |
613 | mdata->cur_transfer = xfer; | |
00bca73b | 614 | mdata->num_xfered = 0; |
a568231f | 615 | |
7e963fb2 | 616 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
a568231f LL |
617 | |
618 | cmd = readl(mdata->base + SPI_CMD_REG); | |
619 | if (xfer->tx_buf) | |
620 | cmd |= SPI_CMD_TX_DMA; | |
621 | if (xfer->rx_buf) | |
622 | cmd |= SPI_CMD_RX_DMA; | |
623 | writel(cmd, mdata->base + SPI_CMD_REG); | |
624 | ||
625 | if (xfer->tx_buf) | |
626 | mdata->tx_sgl = xfer->tx_sg.sgl; | |
627 | if (xfer->rx_buf) | |
628 | mdata->rx_sgl = xfer->rx_sg.sgl; | |
629 | ||
630 | if (mdata->tx_sgl) { | |
631 | xfer->tx_dma = sg_dma_address(mdata->tx_sgl); | |
632 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
633 | } | |
634 | if (mdata->rx_sgl) { | |
635 | xfer->rx_dma = sg_dma_address(mdata->rx_sgl); | |
636 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
637 | } | |
638 | ||
639 | mtk_spi_update_mdata_len(master); | |
640 | mtk_spi_setup_packet(master); | |
641 | mtk_spi_setup_dma_addr(master, xfer); | |
642 | mtk_spi_enable_transfer(master); | |
643 | ||
644 | return 1; | |
645 | } | |
646 | ||
647 | static int mtk_spi_transfer_one(struct spi_master *master, | |
648 | struct spi_device *spi, | |
649 | struct spi_transfer *xfer) | |
650 | { | |
7e963fb2 LL |
651 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
652 | u32 reg_val = 0; | |
653 | ||
654 | /* prepare xfer direction and duplex mode */ | |
655 | if (mdata->dev_comp->ipm_design) { | |
656 | if (!xfer->tx_buf || !xfer->rx_buf) { | |
657 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; | |
658 | if (xfer->rx_buf) | |
659 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; | |
660 | } | |
661 | writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); | |
662 | } | |
663 | ||
a568231f LL |
664 | if (master->can_dma(master, spi, xfer)) |
665 | return mtk_spi_dma_transfer(master, spi, xfer); | |
666 | else | |
667 | return mtk_spi_fifo_transfer(master, spi, xfer); | |
668 | } | |
669 | ||
670 | static bool mtk_spi_can_dma(struct spi_master *master, | |
671 | struct spi_device *spi, | |
672 | struct spi_transfer *xfer) | |
673 | { | |
1ce24864 DK |
674 | /* Buffers for DMA transactions must be 4-byte aligned */ |
675 | return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && | |
676 | (unsigned long)xfer->tx_buf % 4 == 0 && | |
677 | (unsigned long)xfer->rx_buf % 4 == 0); | |
a568231f LL |
678 | } |
679 | ||
58a984c7 LL |
680 | static int mtk_spi_setup(struct spi_device *spi) |
681 | { | |
682 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
683 | ||
684 | if (!spi->controller_data) | |
685 | spi->controller_data = (void *)&mtk_default_chip_info; | |
686 | ||
1a5a87d5 LW |
687 | if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) |
688 | /* CS de-asserted, gpiolib will handle inversion */ | |
689 | gpiod_direction_output(spi->cs_gpiod, 0); | |
37457607 | 690 | |
58a984c7 LL |
691 | return 0; |
692 | } | |
693 | ||
a568231f LL |
694 | static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) |
695 | { | |
00bca73b | 696 | u32 cmd, reg_val, cnt, remainder, len; |
a568231f LL |
697 | struct spi_master *master = dev_id; |
698 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
699 | struct spi_transfer *trans = mdata->cur_transfer; | |
700 | ||
701 | reg_val = readl(mdata->base + SPI_STATUS0_REG); | |
50f8fec2 | 702 | if (reg_val & MTK_SPI_PAUSE_INT_STATUS) |
a568231f LL |
703 | mdata->state = MTK_SPI_PAUSED; |
704 | else | |
705 | mdata->state = MTK_SPI_IDLE; | |
706 | ||
f83a96e5 | 707 | if (!master->can_dma(master, NULL, trans)) { |
a568231f | 708 | if (trans->rx_buf) { |
de327e49 | 709 | cnt = mdata->xfer_len / 4; |
44f636da | 710 | ioread32_rep(mdata->base + SPI_RX_DATA_REG, |
00bca73b | 711 | trans->rx_buf + mdata->num_xfered, cnt); |
de327e49 NB |
712 | remainder = mdata->xfer_len % 4; |
713 | if (remainder > 0) { | |
714 | reg_val = readl(mdata->base + SPI_RX_DATA_REG); | |
00bca73b PS |
715 | memcpy(trans->rx_buf + |
716 | mdata->num_xfered + | |
717 | (cnt * 4), | |
718 | ®_val, | |
719 | remainder); | |
de327e49 | 720 | } |
a568231f | 721 | } |
1ce24864 | 722 | |
00bca73b PS |
723 | mdata->num_xfered += mdata->xfer_len; |
724 | if (mdata->num_xfered == trans->len) { | |
1ce24864 DK |
725 | spi_finalize_current_transfer(master); |
726 | return IRQ_HANDLED; | |
727 | } | |
728 | ||
00bca73b PS |
729 | len = trans->len - mdata->num_xfered; |
730 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); | |
1ce24864 DK |
731 | mtk_spi_setup_packet(master); |
732 | ||
a4d8f64f | 733 | cnt = mdata->xfer_len / 4; |
00bca73b PS |
734 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, |
735 | trans->tx_buf + mdata->num_xfered, cnt); | |
1ce24864 | 736 | |
a4d8f64f | 737 | remainder = mdata->xfer_len % 4; |
1ce24864 DK |
738 | if (remainder > 0) { |
739 | reg_val = 0; | |
00bca73b PS |
740 | memcpy(®_val, |
741 | trans->tx_buf + (cnt * 4) + mdata->num_xfered, | |
742 | remainder); | |
1ce24864 DK |
743 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); |
744 | } | |
745 | ||
746 | mtk_spi_enable_transfer(master); | |
747 | ||
a568231f LL |
748 | return IRQ_HANDLED; |
749 | } | |
750 | ||
751 | if (mdata->tx_sgl) | |
752 | trans->tx_dma += mdata->xfer_len; | |
753 | if (mdata->rx_sgl) | |
754 | trans->rx_dma += mdata->xfer_len; | |
755 | ||
756 | if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { | |
757 | mdata->tx_sgl = sg_next(mdata->tx_sgl); | |
758 | if (mdata->tx_sgl) { | |
759 | trans->tx_dma = sg_dma_address(mdata->tx_sgl); | |
760 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
761 | } | |
762 | } | |
763 | if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { | |
764 | mdata->rx_sgl = sg_next(mdata->rx_sgl); | |
765 | if (mdata->rx_sgl) { | |
766 | trans->rx_dma = sg_dma_address(mdata->rx_sgl); | |
767 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
768 | } | |
769 | } | |
770 | ||
771 | if (!mdata->tx_sgl && !mdata->rx_sgl) { | |
772 | /* spi disable dma */ | |
773 | cmd = readl(mdata->base + SPI_CMD_REG); | |
774 | cmd &= ~SPI_CMD_TX_DMA; | |
775 | cmd &= ~SPI_CMD_RX_DMA; | |
776 | writel(cmd, mdata->base + SPI_CMD_REG); | |
777 | ||
778 | spi_finalize_current_transfer(master); | |
779 | return IRQ_HANDLED; | |
780 | } | |
781 | ||
782 | mtk_spi_update_mdata_len(master); | |
783 | mtk_spi_setup_packet(master); | |
784 | mtk_spi_setup_dma_addr(master, trans); | |
785 | mtk_spi_enable_transfer(master); | |
786 | ||
787 | return IRQ_HANDLED; | |
788 | } | |
789 | ||
790 | static int mtk_spi_probe(struct platform_device *pdev) | |
791 | { | |
792 | struct spi_master *master; | |
793 | struct mtk_spi *mdata; | |
794 | const struct of_device_id *of_id; | |
fdeae8f5 | 795 | int i, irq, ret, addr_bits; |
a568231f LL |
796 | |
797 | master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); | |
798 | if (!master) { | |
799 | dev_err(&pdev->dev, "failed to alloc spi master\n"); | |
800 | return -ENOMEM; | |
801 | } | |
802 | ||
803 | master->auto_runtime_pm = true; | |
804 | master->dev.of_node = pdev->dev.of_node; | |
3e582c6e | 805 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
a568231f LL |
806 | |
807 | master->set_cs = mtk_spi_set_cs; | |
a568231f LL |
808 | master->prepare_message = mtk_spi_prepare_message; |
809 | master->transfer_one = mtk_spi_transfer_one; | |
810 | master->can_dma = mtk_spi_can_dma; | |
58a984c7 | 811 | master->setup = mtk_spi_setup; |
9f6e7e8d | 812 | master->set_cs_timing = mtk_spi_set_hw_cs_timing; |
1a5a87d5 | 813 | master->use_gpio_descriptors = true; |
a568231f LL |
814 | |
815 | of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); | |
816 | if (!of_id) { | |
817 | dev_err(&pdev->dev, "failed to probe of_node\n"); | |
818 | ret = -EINVAL; | |
819 | goto err_put_master; | |
820 | } | |
821 | ||
822 | mdata = spi_master_get_devdata(master); | |
823 | mdata->dev_comp = of_id->data; | |
ae7c2d34 LX |
824 | |
825 | if (mdata->dev_comp->enhance_timing) | |
826 | master->mode_bits |= SPI_CS_HIGH; | |
827 | ||
a568231f LL |
828 | if (mdata->dev_comp->must_tx) |
829 | master->flags = SPI_MASTER_MUST_TX; | |
7e963fb2 LL |
830 | if (mdata->dev_comp->ipm_design) |
831 | master->mode_bits |= SPI_LOOP; | |
a568231f LL |
832 | |
833 | if (mdata->dev_comp->need_pad_sel) { | |
37457607 LL |
834 | mdata->pad_num = of_property_count_u32_elems( |
835 | pdev->dev.of_node, | |
836 | "mediatek,pad-select"); | |
837 | if (mdata->pad_num < 0) { | |
838 | dev_err(&pdev->dev, | |
839 | "No 'mediatek,pad-select' property\n"); | |
840 | ret = -EINVAL; | |
a568231f LL |
841 | goto err_put_master; |
842 | } | |
843 | ||
37457607 LL |
844 | mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, |
845 | sizeof(u32), GFP_KERNEL); | |
846 | if (!mdata->pad_sel) { | |
847 | ret = -ENOMEM; | |
a568231f LL |
848 | goto err_put_master; |
849 | } | |
37457607 LL |
850 | |
851 | for (i = 0; i < mdata->pad_num; i++) { | |
852 | of_property_read_u32_index(pdev->dev.of_node, | |
853 | "mediatek,pad-select", | |
854 | i, &mdata->pad_sel[i]); | |
855 | if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { | |
856 | dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", | |
857 | i, mdata->pad_sel[i]); | |
858 | ret = -EINVAL; | |
859 | goto err_put_master; | |
860 | } | |
861 | } | |
a568231f LL |
862 | } |
863 | ||
864 | platform_set_drvdata(pdev, master); | |
5dd381e7 | 865 | mdata->base = devm_platform_ioremap_resource(pdev, 0); |
a568231f LL |
866 | if (IS_ERR(mdata->base)) { |
867 | ret = PTR_ERR(mdata->base); | |
868 | goto err_put_master; | |
869 | } | |
870 | ||
871 | irq = platform_get_irq(pdev, 0); | |
872 | if (irq < 0) { | |
a568231f LL |
873 | ret = irq; |
874 | goto err_put_master; | |
875 | } | |
876 | ||
877 | if (!pdev->dev.dma_mask) | |
878 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
879 | ||
880 | ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, | |
881 | IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); | |
882 | if (ret) { | |
883 | dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); | |
884 | goto err_put_master; | |
885 | } | |
886 | ||
a568231f LL |
887 | mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); |
888 | if (IS_ERR(mdata->parent_clk)) { | |
889 | ret = PTR_ERR(mdata->parent_clk); | |
890 | dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); | |
891 | goto err_put_master; | |
892 | } | |
893 | ||
adcbcfea LL |
894 | mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); |
895 | if (IS_ERR(mdata->sel_clk)) { | |
e26d15f7 | 896 | ret = PTR_ERR(mdata->sel_clk); |
adcbcfea | 897 | dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); |
a568231f LL |
898 | goto err_put_master; |
899 | } | |
900 | ||
adcbcfea LL |
901 | mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); |
902 | if (IS_ERR(mdata->spi_clk)) { | |
e26d15f7 | 903 | ret = PTR_ERR(mdata->spi_clk); |
adcbcfea | 904 | dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); |
a568231f LL |
905 | goto err_put_master; |
906 | } | |
907 | ||
908 | ret = clk_prepare_enable(mdata->spi_clk); | |
909 | if (ret < 0) { | |
910 | dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); | |
911 | goto err_put_master; | |
912 | } | |
913 | ||
adcbcfea | 914 | ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); |
a568231f LL |
915 | if (ret < 0) { |
916 | dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); | |
e38da37f LL |
917 | clk_disable_unprepare(mdata->spi_clk); |
918 | goto err_put_master; | |
a568231f LL |
919 | } |
920 | ||
162a31ef MZ |
921 | mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); |
922 | ||
923 | if (mdata->dev_comp->no_need_unprepare) | |
924 | clk_disable(mdata->spi_clk); | |
925 | else | |
926 | clk_disable_unprepare(mdata->spi_clk); | |
a568231f LL |
927 | |
928 | pm_runtime_enable(&pdev->dev); | |
929 | ||
37457607 LL |
930 | if (mdata->dev_comp->need_pad_sel) { |
931 | if (mdata->pad_num != master->num_chipselect) { | |
932 | dev_err(&pdev->dev, | |
933 | "pad_num does not match num_chipselect(%d != %d)\n", | |
934 | mdata->pad_num, master->num_chipselect); | |
935 | ret = -EINVAL; | |
e38da37f | 936 | goto err_disable_runtime_pm; |
37457607 LL |
937 | } |
938 | ||
1a5a87d5 | 939 | if (!master->cs_gpiods && master->num_chipselect > 1) { |
98c8dccf NB |
940 | dev_err(&pdev->dev, |
941 | "cs_gpios not specified and num_chipselect > 1\n"); | |
942 | ret = -EINVAL; | |
e38da37f | 943 | goto err_disable_runtime_pm; |
98c8dccf | 944 | } |
37457607 LL |
945 | } |
946 | ||
fdeae8f5 | 947 | if (mdata->dev_comp->dma_ext) |
948 | addr_bits = DMA_ADDR_EXT_BITS; | |
949 | else | |
950 | addr_bits = DMA_ADDR_DEF_BITS; | |
951 | ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); | |
952 | if (ret) | |
953 | dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", | |
954 | addr_bits, ret); | |
955 | ||
c934fec1 MZ |
956 | ret = devm_spi_register_master(&pdev->dev, master); |
957 | if (ret) { | |
958 | dev_err(&pdev->dev, "failed to register master (%d)\n", ret); | |
959 | goto err_disable_runtime_pm; | |
960 | } | |
961 | ||
a568231f LL |
962 | return 0; |
963 | ||
e38da37f LL |
964 | err_disable_runtime_pm: |
965 | pm_runtime_disable(&pdev->dev); | |
a568231f LL |
966 | err_put_master: |
967 | spi_master_put(master); | |
968 | ||
969 | return ret; | |
970 | } | |
971 | ||
972 | static int mtk_spi_remove(struct platform_device *pdev) | |
973 | { | |
974 | struct spi_master *master = platform_get_drvdata(pdev); | |
975 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
976 | ||
977 | pm_runtime_disable(&pdev->dev); | |
978 | ||
979 | mtk_spi_reset(mdata); | |
a568231f | 980 | |
162a31ef MZ |
981 | if (mdata->dev_comp->no_need_unprepare) |
982 | clk_unprepare(mdata->spi_clk); | |
983 | ||
a568231f LL |
984 | return 0; |
985 | } | |
986 | ||
987 | #ifdef CONFIG_PM_SLEEP | |
988 | static int mtk_spi_suspend(struct device *dev) | |
989 | { | |
990 | int ret; | |
991 | struct spi_master *master = dev_get_drvdata(dev); | |
992 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
993 | ||
994 | ret = spi_master_suspend(master); | |
995 | if (ret) | |
996 | return ret; | |
997 | ||
998 | if (!pm_runtime_suspended(dev)) | |
999 | clk_disable_unprepare(mdata->spi_clk); | |
1000 | ||
1001 | return ret; | |
1002 | } | |
1003 | ||
1004 | static int mtk_spi_resume(struct device *dev) | |
1005 | { | |
1006 | int ret; | |
1007 | struct spi_master *master = dev_get_drvdata(dev); | |
1008 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1009 | ||
1010 | if (!pm_runtime_suspended(dev)) { | |
1011 | ret = clk_prepare_enable(mdata->spi_clk); | |
13da5a0b LL |
1012 | if (ret < 0) { |
1013 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
a568231f | 1014 | return ret; |
13da5a0b | 1015 | } |
a568231f LL |
1016 | } |
1017 | ||
1018 | ret = spi_master_resume(master); | |
1019 | if (ret < 0) | |
1020 | clk_disable_unprepare(mdata->spi_clk); | |
1021 | ||
1022 | return ret; | |
1023 | } | |
1024 | #endif /* CONFIG_PM_SLEEP */ | |
1025 | ||
1026 | #ifdef CONFIG_PM | |
1027 | static int mtk_spi_runtime_suspend(struct device *dev) | |
1028 | { | |
1029 | struct spi_master *master = dev_get_drvdata(dev); | |
1030 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
1031 | ||
162a31ef MZ |
1032 | if (mdata->dev_comp->no_need_unprepare) |
1033 | clk_disable(mdata->spi_clk); | |
1034 | else | |
1035 | clk_disable_unprepare(mdata->spi_clk); | |
a568231f LL |
1036 | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int mtk_spi_runtime_resume(struct device *dev) | |
1041 | { | |
1042 | struct spi_master *master = dev_get_drvdata(dev); | |
1043 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
13da5a0b LL |
1044 | int ret; |
1045 | ||
162a31ef MZ |
1046 | if (mdata->dev_comp->no_need_unprepare) |
1047 | ret = clk_enable(mdata->spi_clk); | |
1048 | else | |
1049 | ret = clk_prepare_enable(mdata->spi_clk); | |
13da5a0b LL |
1050 | if (ret < 0) { |
1051 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
1052 | return ret; | |
1053 | } | |
a568231f | 1054 | |
13da5a0b | 1055 | return 0; |
a568231f LL |
1056 | } |
1057 | #endif /* CONFIG_PM */ | |
1058 | ||
1059 | static const struct dev_pm_ops mtk_spi_pm = { | |
1060 | SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) | |
1061 | SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, | |
1062 | mtk_spi_runtime_resume, NULL) | |
1063 | }; | |
1064 | ||
4299aaaa | 1065 | static struct platform_driver mtk_spi_driver = { |
a568231f LL |
1066 | .driver = { |
1067 | .name = "mtk-spi", | |
1068 | .pm = &mtk_spi_pm, | |
1069 | .of_match_table = mtk_spi_of_match, | |
1070 | }, | |
1071 | .probe = mtk_spi_probe, | |
1072 | .remove = mtk_spi_remove, | |
1073 | }; | |
1074 | ||
1075 | module_platform_driver(mtk_spi_driver); | |
1076 | ||
1077 | MODULE_DESCRIPTION("MTK SPI Controller driver"); | |
1078 | MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); | |
1079 | MODULE_LICENSE("GPL v2"); | |
e4001885 | 1080 | MODULE_ALIAS("platform:mtk-spi"); |